Synchronous Latency Insensitive Design - ICS
Synchronous Latency Insensitive Design - ICS
Synchronous Latency Insensitive Design - ICS
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Introduction<br />
The wire delay problem was recognized very early (Anceau 1982)<br />
Wire delay ~ L 2 /s 2 , Gate delay ~s α , s=feature size, α=1..2<br />
In spite of the “alarm” 1982, we still manage multigigahertz synchronous<br />
designs, BUT today with considerable problems.<br />
ASIC style designs normally limited to 300-500MHz clock, with severe<br />
“timing closure” problems.<br />
Multigigahertz designs very demanding full custom design style.<br />
Christer Svensson, ASYNC 2004 3
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