Synchronous Latency Insensitive Design - ICS

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Architectural view of future systems Wire delays are inevitable: we must accept latency. The latency/delay problem should be managed at two levels • System level (predictability) • Implementation level (error-free) Christer Svensson, ASYNC 2004 20
Architectural view of future systems System level. Partition the system into blocks of limited size. (Preferably natural partition, processors, memories, IP-blocks etc.) We may define a system where only order of events is important. (“Classical” asynchronous, Patient systems (Carloni et al 1999)) We may then accept any latency between blocks. We may define a system with fixed latency between blocks. (If fixed latency is n clock cycles, the system is synchronous) We may then accept any latency < nT c between blocks. Christer Svensson, ASYNC 2004 21
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19: Architectural view of future system
Page 23 and 24: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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