Synchronous Latency Insensitive Design - ICS

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Overview of wire properties Delay or latency, RC-wire High loss case (RC-case), r DC L/Z 0 >2ln2. Elmore delay good approximation: t d ⎛ ⎜ R ⎝ ⎛ C ⎜ ⎝ 2 ⎞⎞ ⎟ ⎠⎠ w ( C + C + C ) + R + C ⎟ln 2 = S S w L w L <strong>Latency</strong> can be improved by repeaters Delay or latency, LC-wire Low loss case (LC-case), r DC L/Z 0
Overview of wire properties Capacity or maximum data rate T S(T) Single pulse Eye diagram Eye opening Eye opening = 2S(T)-1, S(t) step response, T symbol time We need a minimum opening for safe data detection, say 64% For long wires we may afford a simple equalizer, allowing 0% Christer Svensson, ASYNC 2004 9
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7: Overview of wire properties We disc
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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