Synchronous Latency Insensitive Design - ICS
Synchronous Latency Insensitive Design - ICS
Synchronous Latency Insensitive Design - ICS
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
<strong>Synchronous</strong> <strong>Latency</strong> <strong>Insensitive</strong> <strong>Design</strong><br />
System<br />
partition<br />
<strong>Design</strong> flow<br />
“Natural” partition (processors, memories,<br />
IP-blocks…) into isochronous regions<br />
Clock-true<br />
model &<br />
verification<br />
NEW: Insertion of dummy delays between<br />
isochronic regions. Clock-true verification.<br />
Synthesis &<br />
Back-end<br />
Replace dummy delays with elastic FIFO’s<br />
Timing<br />
verification<br />
Considerably easier, feedback can be avoided<br />
Christer Svensson, ASYNC 2004 26