Synchronous Latency Insensitive Design - ICS

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Synchronous Latency Insensitive Design Implementation System reset used as initialization mechanism (example n=2) clk Tx1 rst written into FIFO(2) by strobe reset clk at root data at Tx1 data at Rx Tx2 read from FIFO(2) by Rx clk after 2 counts FIFO(2) clk at Rx Rx data in Rx Note that data relation to clk period number predictable Christer Svensson, ASYNC 2004 28
Synchronous Latency Insensitive Design Simulation clk Tx1 Clk Tx1 out Rx1 in Tx2 out Rx2 in Rx1 out Rx2 out Rx1 in count Rx1 out count Rx2 in count Rx2 out count 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 00 01 10 11 00 01 10 11 00 01 10 10 11 00 01 10 11 00 01 10 11 00 01 Rx Tx2 0 20 ns 40 ns 60 ns Clk Tx1 out Rx1 in Tx2 out Rx2 in Rx1 out Rx2 out Rx1 in count 00 01 10 11 00 01 10 11 00 01 Rx1 out count 10 11 00 01 10 11 00 01 10 11 Rx2 in count 00 01 10 11 00 01 10 11 00 01 10 11 Rx2 out count 10 11 00 01 10 11 00 01 10 0 20 ns 40 ns 60 ns Christer Svensson, ASYNC 2004 29
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 27: Synchronous Latency Insensitive Des
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

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