Synchronous Latency Insensitive Design - ICS

More documents

Recommendations

Info

Architectural view of future systems Implementation level (We must avoid synchronization errors) Use synchronizers with long decision time (extra latency, nonzero error probability) Use stoppable clocks to synchronize communication (Classical GALS, Chapiro 1984) Adapt clock phase to data (mesochronous clocks) (Mu 2001) Use FIFO’s to isolate clock regions (FIFO’s initialized with synchronizers, Chakraborty 2001) (FIFO’s initialized via system reset, Edman 2004) Christer Svensson, ASYNC 2004 22
Architectural view of future systems Implementation level, Examples Data in Choise of clock phase (Mu 2001) Metastab. detector Data out Rx clk FIFO solution (Chakraborty 2001, Edman 2004) Data in Write pointer Read pointer Data out Tx clk Rx clk “Circular” FIFO Christer Svensson, ASYNC 2004 23
Page 1 and 2: Synchronous Latency Insensitive Des
Page 3 and 4: Introduction The wire delay problem
Page 5 and 6: Overview of wire properties Ground
Page 7 and 8: Overview of wire properties We disc
Page 9 and 10: Overview of wire properties Capacit
Page 11 and 12: Overview of wire properties Note th
Page 13 and 14: Overview of wire properties Low lev
Page 15 and 16: Overview of wire properties On-chip
Page 17 and 18: Overview of wire properties Upper w
Page 19 and 20: Architectural view of future system
Page 21: Architectural view of future system
Page 33 and 34: Multiple clocks FIFO synchronizatio
Page 35: References F. Anceau, "A Synchronou

Synchronous Latency Insensitive Design - ICS

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?