29.01.2014 Views

Errata Sheet - Infineon

Errata Sheet - Infineon

Errata Sheet - Infineon

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Errata</strong> <strong>Sheet</strong><br />

XC161CS-32F, (E)ES-BB, BB<br />

Functional Problems<br />

However, two pins (P9.2/CC18IO/CAN1_RxD and P9.4/CC20IO) have been identified<br />

that under exceptional conditions (e.g. massive low frequency noise) may cause side<br />

effects on internal flash (read or erase) operations before these overload limits are<br />

reached or exceeded, depending on the amplitude and width of the respective input<br />

signal:<br />

No problem will occur<br />

• when the input levels on pin P9.2/CC18IO/CAN1_RxD do not exceed the positive or<br />

negative supply voltages V SSP or V DDP as listed in the table below.<br />

Otherwise, incorrect data may be read from the internal flash module, or program or<br />

erase operations may fail if this condition is present while the respective operation is<br />

in progress.<br />

• when the input low level on pin P9.4/CC20IO does not exceed the negative supply<br />

voltage V SSP as listed in the table below.<br />

Otherwise, an erase operation of the internal flash module may fail if this condition is<br />

present while an erase operation is in progress.<br />

Conditions for Amplitude and Width of Input Signal:<br />

No problem will occur for signals on pin P9.2/CC18IO/CAN1_RxD with the following<br />

characteristics:<br />

• for low or high pulses with an amplitude Vin < V DDP +0.5V or Vin > V SSP -0.5V and<br />

pulse width < 100 ns and duty cycle DC < 0.33 (e.g. high pulses < 100 ns with this<br />

amplitude are tolerated if the following low phase is > 200 ns)<br />

• for steady state signals or pulses > 100 ns with an amplitude Vin < V DDP +0.2V or Vin<br />

> V SSP -0.2V<br />

No problem will occur for signals on pin P9.4/CC20IO with the following characteristics:<br />

• for low pulses with an amplitude Vin > V SSP -0.5V and pulse width < 1 µs and duty<br />

cycle DC < 0.33 (e.g. low pulses < 1 µs with this amplitude are tolerated if the<br />

following high phase is > 2 µs)<br />

• for steady state signals or low pulses > 1 µs with an amplitude Vin > V SSP -0.3V.<br />

Typical overshoot/undershoot after signal transitions is normally uncritical (covered by<br />

duty cycle specification, see notes 1) and 2) below).<br />

<strong>Errata</strong> <strong>Sheet</strong> 17/50 V1.1, 2007-06-21

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!