Errata Sheet - Infineon

Errata Sheet
XC161CS-32F, (E)ES-BB, BB
Functional Problems
• If hardware traps (including NMI) can occur, add the corresponding interrupt vectors
to PRAM and modify register VECSEG to point to the PRAM space.
• In order to support return to idle/sleep mode after a PEC transfer, e.g. a semaphore
bit may be used. This bit may be set to '1' before the IDLE instruction is executed. All
trap and interrupt service routines invoked after wake up from idle/sleep should clear
this bit to '0'. After having returned to the program in the internal flash and having
enabled the interrupt system, this bit should be tested (allow a sufficient time of e.g.
12 cycles for interrupt arbitration), and if it is still at '1' (i.e. no interrupts/traps have
occurred), repeat the auxiliary routine that prepares for re-entry into idle/sleep mode.
ASC_X.001 ASC Autobaud Detection in 8-bit Modes with Parity
The Autobaud Detection feature of the Asynchronous/Synchronous Serial Interface
(ASC) does not work correctly for 8-bit modes with even or odd parity.
The Autobaud Detection feature works correctly for 7-bit modes with even or odd parity,
and for 8-bit modes without parity.
GPT12E_X.001 T5/T6 in Counter Mode with BPS2 = 1X B
When T5 and/or T6 are configured for counter mode (bit field TxM = 001 B in register
GPT12E_TxCON, x = 5, 6), and bit field BPS2 = 1X B in register GPT12E_T6CON, then
edge detection for the following count input and control signals does not work correctly:
T5IN, T6IN, T5EUD, T6EUD.
Note: The configuration where T5 counts the overflow/underflow events of T6 is not
affected by this problem.
Workaround
Do not set bit field BPS2 = 1X B in register GPT12E_T6CON when T5 and/or T6 are
configured for counter mode. Use only settings BPS2 = 0X B when T5 and/or T6 are
configured for counter mode.
Errata Sheet 24/50 V1.1, 2007-06-21