DEPFET Pixel Vertex Detector for the ILC - MPG HLL

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Figure 7: Layout of a double pixel. (Left: detailed view, right: simplified geometry) Figure 8: Photograph of a double pixel 10
Figure 9: 3d simulation of the electron density in a rectangular DEPFET lengths L=5µm...60µm and widths W=25µm ...120µm). During normal operation at the ILC, the DEPFET is in charge collection mode, i.e. fully depleted with empty internal gate and switched off by means of a positive gate voltage with respect to the source. The transistors of a row are only switched on during the short read out period. The off/on ratio in the first layer of the ILC vertex detector (assuming a 512 × 4096 pixel array read out at both sides) is in the order of 1000. Thus the irradiation of six test devices was done with the transistors in ‘off’ state with an empty internal gate to test for the radiation tolerance in this most frequent operation mode. To investigate the implication of the biasing conditions on radiation tolerance, some transistors were also irradiated in ‘on’ state, others with all terminals grounded, and one transistor being first in ‘off’ state then switched ‘on’ during irradiation. Table 1 lists the irradiated devices, the irradiation source, and the biasing conditions during irradiation. For the 60 Co irradiation, the dose rate was 20 krad(SiO 2 )/h. The dosimetry was provided by the staff of the National Research Center for Environment and Health (GSF) by means of a calibrated ionization chamber. The input characteristic of the devices were measured immediately (approximately 1 min) after each irradiation period and the threshold voltage was extracted by a quadratic extrapolation of the I D (V G )-curve to I D = 0. Figure 10 shows the threshold voltage shift and the density of the oxide trapped charge of 11
Page 1 and 2: DESY PRC R&D 03/01 Update 1(05) Pro
Page 3 and 4: 1 Introduction This status report s
Page 5 and 6: Figure 1: The DEPFET detector and a
Page 7 and 8: clear gate and DEPMOS gate, respect
Page 9 and 10: impact on the clear efficiency. A n
Page 11: gate_2 drain_2 global source common
Page 15 and 16: the first 3.5h and the threshold vo
Page 17: with an electrically active backsid
Page 20 and 21: matrices, most notably the obtainab
Page 22 and 23: U (Cleargate) [V] 6 5 4 3 2 1 0 6 8
Page 24 and 25: of one module will have a size of
Page 26 and 27: Figure 22: Photograph of the SWITCH
Page 28 and 29: Figure 24: Micro photograph of the
Page 30 and 31: Figure 26: Radiogram of a 10µm thi
Page 32 and 33: The duty cycle of ≈ 1/200 given b
Page 34: [8] E. Gatti, P. Rehak: Semiconduct

DEPFET Pixel Vertex Detector for the ILC - MPG HLL

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