Book of abstracts - Euro-MBE 2011 - CNRS

Mo1.3
200 mm GaAs wafers by MBE on SGOI and Ge/Si substrates
M. Richter 1,* , T. Topuria 2 , C. Marchiori 1 , M. El-Kazzi 1 , C. Rossel 1 , C. Gerl 1 , D.J. Webb 1 ,
T. Smets 3 , C. Andersson 1 , M. Sousa 1 , D. Caimi 1 , L. Czornomaz 1 , H. Siegwart 1 ,
J.-F. Damlencourt 4 , J.-M. Hartmann 4 , P.M. Rice 2 , and J. Fompeyrine 1
1
IBM Research – Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
2 IBM Research – Almaden, 650 Harry Road, San Jose, California, USA
3 Kath. Uni. Leuven – Celestijnenlaan 200D, 3001 Heverlee, Belgium
4 CEA-LETI – Grenoble, 17 rue des Martyrs, 38054 Grenoble, France
The use of production size wafers is a prerequisite for the integration of III-V materials in future
CMOS technology. Besides obvious technical benefits to merge III-V with silicon process technology,
it also allows to economize on scarce materials. In this presentation, GaAs heterogeneous integration
on 200 mm Si and SGOI wafers via Ge buffers will be discussed.
In our previous work, we have studied thin (≤ 250 nm) MBE-grown Ge buffers. This had the
advantage to rely on the use of two UHV-connected MBE chambers, thus limiting air exposure
between Ge buffer and GaAs growth [1]. In this paper, we discuss an alternative approach which
consists in combining Ge growth by reduced pressure-chemical vapor deposition (RP-CVD) with
subsequent, ex-situ MBE GaAs deposition. CVD growth allows for thicker Ge layers and anneals in
the H 2 carrier gas. By this means reduced defect densities [2] and flatter surfaces due to the surfactant
action of H 2 [3] can be achieved. In a first series of samples, we use 200 mm Si(001) wafers with 1.5
µm Ge. In a second series of sample, we use 200 mm SGOI wafers, which feature improved insulation
to the Si substrate and optional co-integration of fully depleted GOI p-FETs [4].
Special care needs to be taken to clean the Ge/Si or SGOI wafers before the GaAs MBE growth. The
anneal temperature should be minimized to take account of the limited temperature stability. All
wafers were prepared with an HF-dip as last cleaning step. Then, they were either exposed to a remote
hydrogen plasma [5] or annealed at 600 °C in UHV. The removal of oxides and carbon was monitored
with x-ray photoelectron spectroscopy (XPS). The H plasma efficiently removes oxide species at
temperatures as low as 250 °C on both Ge/Si and SGOI substrates (spectra in Fig. 1). Only traces of C
contamination are observed after such cleaning treatment. As opposed to that, after sample flash
substantial amounts of SiOx are observed (Fig. 1(b)).
For the SGOI wafers, either 200 nm Ge were deposited in a UHV-connected Si/Ge MBE system or
SGOI wafers capped with 20 nm CVD-grown Ge were used. Then, the wafers were directly
transferred under UHV conditions for epitaxy of 500 nm GaAs. Fig. 2 shows corresponding reflection
high energetic electron diffraction (RHEED) images after the individual steps.
We will discuss the impact of the substrate, its cleaning and of the different buffers on the GaAs
structural quality. Cross-sectional transmission electron microscopy (XTEM) and atomic force
microscope (AFM) images of a first sample of 500 nm GaAs on 20 nm Ge CVD-capped SGOI are
shown in Fig. 3 (a) and (b), respectively.
TEM specimen preparation by L.M. Clark and L.E. Krupp (IBM Research - Almaden) as well as
financial support by the European Commission in frame of the FP7 project DUALLOGIC is gratefully
acknowledged.
[1] M. Richter, C. Rossel, D.J. Webb, T. Topuria, C. Gerl, M. Sousa, C. Marchiori, D. Caimi, H. Siegwart, P.M. Rice and J.
Fompeyrine, “GaAs on 200 mm Si wafers via thin temperature graded Ge buffers by molecular beam epitaxy” submitted to J.
Cryst. Growth and abstract MBE 2010 conference.
[2] J.M. Hartmann, A. Abbadie, N. Cherkashin, H. Grampeix, and L. Clavelier, Semicond. Sci. Technol., 24, 055002 (2009).
[3] L. Colace, G. Masini, F. Galluzzi, G. Assanto, G. Capellini, L. Di Gaspare, E. Palange, and F. Evangelisti, Appl. Phys.
Lett., 72, 3175 (1998).
[4] W. Van Den Daele, E. Augendre, K. Romanjek, C. Le Royer, L. Clavelier, J.-F. Damlencourt, E. Guiot, B. Ghyselen, and
S. Cristoloveanu, ECS Trans., 19, 145 (2009).
[5] C. Marchiori, D. J. Webb, C. Rossel, M. Richter, M. Sousa, C. Gerl, R. Germann, C. Andersson, and J. Fompeyrine, J.
Appl. Phys., 106, 114112 (2009).
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* Contact: mri@zurich.ibm.com