M68000 Microprocessor User's Manual

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shifted by, rotated by — The source operand is shifted or rotated by the number of positions specified by the second operand Notation for single-operand operations: ~ — The operand is logically complemented sign-extended — The operand is sign-extended, all bits of the upper portion are made equal to the high-order bit of the lower portion tested — The operand is compared to zero and the condition codes are set appropriately Notation for other operations: TRAP — Equivalent to Format/Offset Word → (SSP); SSP–2 → SSP; PC → (SSP); SSP–4 → SSP; SR → (SSP); SSP–2 → SSP; (vector) → PC STOP — Enter the stopped state, waiting for interrupts If then — The condition is tested. If true, the operations after "then" else are performed. If the condition is false and the optional "else" clause is present, the operations after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. 2-10 <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Table 2-2. Instruction Set Summary (Sheet 1 of 4) Opcode Operation Syntax ABCD Source10 + Destination10 + X → Destination ABCD Dy,Dx ABCD –(Ay), –(Ax) ADD Source + Destination → Destination ADD ,Dn ADD Dn, ADDA Source + Destination → Destination ADDA ,An ADDI Immediate Data + Destination → Destination ADDI # , ADDQ Immediate Data + Destination → Destination ADDQ # , ADDX Source + Destination + X → Destination ADDX Dy, Dx ADDX –(Ay), –(Ax) AND Source Λ Destination → Destination AND ,Dn AND Dn, ANDI Immediate Data Λ Destination → Destination ANDI # , ANDI to CCR Source Λ CCR → CCR ANDI # , CCR ANDI to SR If supervisor state then Source Λ SR → SR else TRAP ANDI # , SR ASL, ASR Destination Shifted by → Destination ASd Dx,Dy ASd # ,Dy ASd Bcc If (condition true) then PC + d → PC Bcc BCHG ~ ( of Destination) → Z; ~ ( of Destination) → of Destination BCLR ~ ( of Destination) → Z; 0 → of Destination BKPT Run breakpoint acknowledge cycle; TRAP as illegal instruction BCHG Dn, BCHG # , BCLR Dn, BCLR # , BKPT # BRA PC + d → PC BRA BSET ~ ( of Destination) → Z; 1 → of Destination BSET Dn, BSET # , BSR SP – 4 → SP; PC → (SP); PC + d → PC BSR BTST – ( of Destination) → Z; BTST Dn, BTST # , CHK If Dn < 0 or Dn > Source then TRAP CHK ,Dn CLR 0 → Destination CLR CMP Destination—Source → cc CMP ,Dn CMPA Destination—Source CMPA ,An CMPI Destination —Immediate Data CMPI # , CMPM Destination—Source → cc CMPM (Ay)+, (Ax)+ DBcc If condition false then (Dn – 1 → Dn; If Dn ≠ –1 then PC + d → PC) DBcc Dn, MOTOROLA <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-11
Page 1 and 2: µ MOTOROLA M68000 8-/16-/32-Bit Mi
Page 3 and 4: TABLE OF CONTENTS (Continued) Parag
Page 5 and 6: TABLE OF CONTENTS (Continued) Parag
Page 7 and 8: LIST OF ILLUSTRATIONS Figure Page N
Page 9 and 10: LIST OF ILLUSTRATIONS (Concluded) F
Page 11 and 12: LIST OF TABLES (Concluded) Table Pa
Page 13 and 14: 1.1 MC68000 The MC68000 is the firs
Page 15 and 16: SECTION 2 INTRODUCTION The section
Page 17 and 18: tables. The SFC and DFC registers a
Page 19 and 20: Register Direct Addressing Data Reg
Page 21 and 22: BIT DATA 1 BYTE = 8 BITS 7 6 5 4 3
Page 23: Notation for operands: PC — Progr
Page 27 and 28: Table 2-2. Instruction Set Summary
Page 29 and 30: SECTION 3 SIGNAL DESCRIPTION This s
Page 31 and 32: V CC (2) GND(2) CLK ADDRESS BUS DAT
Page 33 and 34: Table 3-1. Data Strobe Control of D
Page 35 and 36: 3.6 SYSTEM CONTROL The system contr
Page 37 and 38: Table 3-3. Function Code Outputs Fu
Page 39 and 40: SECTION 4 8-BIT BUS OPERATION The f
Page 41 and 42: A bus cycle consists of eight state
Page 43 and 44: The descriptions of the eight state
Page 45 and 46: CLK S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S
Page 47 and 48: SECTION 5 16-BIT BUS OPERATION The
Page 49 and 50: CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S
Page 51 and 52: The word and byte write-cycle timin
Page 53 and 54: STATE 7 On the falling edge of the
Page 55 and 56: STATE 12 STATE 13 STATE 14 STATE 15
Page 57 and 58: The breakpoint acknowledge cycle is
Page 59 and 60: PROCESSOR REQUESTING DEVICE REQUEST
Page 61 and 62: us request signal. When no acknowle
Page 63 and 64: RA 1 RA GT 1 XA RA GT RA GT RA XX R
Page 65 and 66: BUS RELEASED FROM THREE STATE AND P
Page 67 and 68: BUS THREE-STATED BG ASSERTED BR VAL
Page 69 and 70: BUS THREE-STATED BG ASSERTED BR VAL
Page 71 and 72: CLK S0 S2 S4 S6 FC2-FC0 A23-A1 AS U
Page 73 and 74: CLK S0 S2 S4 S6 S0 S2 S4 S6 FC2-FC0
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A double bus fault occurs during a
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Case No. Control Signal 1 DTACK BER
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ADDR AS R/W UDS/LDS DATA DTACK Figu
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ADDR 11 AS 20A R/W 22 UDS/LDS 55 26
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On the rising edge of the clock, at
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Parameter #47 of Section 10 Electri
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The privilege mode is a mechanism f
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6.2 EXCEPTION PROCESSING The proces
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equests from peripheral devices for
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6.2.3 Multiple Exceptions These par
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SSP EVEN BYTE ODD BYTE 7 0 7 0 15 0
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interrupt priority mask is set at l
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A signed divide (DIVS) or unsigned
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After the execution of the instruct
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. 15 14 13 12 11 10 9 8 7 6 5 4 3 2
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6.4 RETURN FROM EXCEPTION (MC68010)
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Table 7-1. Effective Address Calcul
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In Table 7-5, the following notatio
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CLR Table 7-7. Single Operand Instr
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7.9 JMP, JSR, LEA, PEA, AND MOVEM I
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Table 7-13. Miscellaneous Instructi
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SECTION 8 16-BIT INSTRUCTION EXECUT
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Table 8-3. Move Long Instruction Ex
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Table 8-5. Immediate Instruction Ex
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8.7 BIT MANIPULATION INSTRUCTION EX
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Table 8-11. Multiprecision Instruct
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the handler routine. The total numb
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9.1 OPERAND EFFECTIVE ADDRESS CALCU
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Table 9-4. Move Long Instruction Ex
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9.4 IMMEDIATE INSTRUCTION EXECUTION
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Table 9-11. Single Operand Instruct
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Table 9-15. Conditional Instruction
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Table 9-18. Miscellaneous Instructi
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SECTION 10 ELECTRICAL AND THERMAL C
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Table 10-1 summarizes maximum power
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is lost through the active P-channe
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10.6 MC68000/68008/68010 DC ELECTRI
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. 10.9 MC68008 AC ELECTRICAL SPECIF
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Num Characteristic 8 MHz* 10 MHz* 1
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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10.11 AC ELECTRICAL SPECIFICATIONS
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10.12 AC ELECTRICAL SPECIFICATIONS
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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10.13 MC68EC000 DC ELECTRICAL SPECI
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Num Characteristic 8 MHz 10 MHz 12.
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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CLK 47 33 BR 34 35 36 BG 39 38 58 A
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11-2 M68000 8-/16-/32-BIT MICROPROC
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R/W LDS UDS AS D0 D1 D2 D3 D4 D5 D6
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A3 1 48 A2 A4 2 47 A1 A5 3 46 A0 A6
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64 33 L SUFFIX 746-03 B 1 32 A F C
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64 33 L SUFFIX 746-01 B 1 32 A F C
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Figure 11-11. Case 765A-05—RC Suf
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1. Fetch the MOVE instruction. 2. F
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M68000 Microprocessor User's Manual

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