M68000 Microprocessor User's Manual

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Table 2-2. Instruction Set Summary (Sheet 2 of 4) Opcode Operation Syntax DIVS Destination/Source → Destination DIVS.W ,Dn 32/16 → 16r:16q DIVU Destination/Source → Destination DIVU.W ,Dn 32/16 → 16r:16q EOR Source ⊕ Destination → Destination EOR Dn, EORI Immediate Data ⊕ Destination → Destination EORI # , EORI to CCR Source ⊕ CCR → CCR EORI # ,CCR EORI to SR If supervisor state then Source ⊕SR → SR else TRAP EORI # ,SR EXG Rx ↔ Ry EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT Destination Sign-Extended → Destination EXT.W Dn extend byte to word EXT.L Dn extend word to long word ILLEGAL SSP – 2 → SSP; Vector Offset → (SSP); SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP; SR → (SSP); Illegal Instruction Vector Address → PC ILLEGAL JMP Destination Address → PC JMP JSR SP – 4 → SP; PC → (SP) Destination Address → PC JSR LEA → An LEA ,An LINK SP – 4 → SP; An → (SP) SP → An, SP + d → SP LINK An, # LSL,LSR Destination Shifted by → Destination LSd 1 Dx,Dy LSd 1 # ,Dy LSd 1 MOVE Source → Destination MOVE , MOVEA Source → Destination MOVEA ,An MOVE from CCR MOVE to CCR MOVE from SR MOVE to SR CCR → Destination Source → CCR SR → Destination If supervisor state then SR → Destination else TRAP (MC68010 only) If supervisor state then Source → SR else TRAP MOVE CCR, MOVE ,CCR MOVE SR, MOVE ,SR 2-12 <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Table 2-2. Instruction Set Summary (Sheet 3 of 4) Opcode Operation Syntax MOVE USP MOVEC MOVEM If supervisor state then USP → An or An → USP else TRAP If supervisor state then Rc → Rn or Rn → Rc else TRAP Registers → Destination Source → Registers MOVE USP,An MOVE An,USP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM register list, MOVEM ,register list MOVEP Source → Destination MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ Immediate Data → Destination MOVEQ # ,Dn MOVES If supervisor state then Rn → Destination [DFC] or Source [SFC] → Rn else TRAP MOVES Rn, MOVES ,Rn MULS Source × Destination → Destination MULS.W ,Dn 16 x 16 → 32 MULU Source × Destination → Destination MULU.W ,Dn 16 x 16 → 32 NBCD 0 – (Destination10) – X → Destination NBCD NEG 0 – (Destination) → Destination NEG NEGX 0 – (Destination) – X → Destination NEGX NOP None NOP NOT ~Destination → Destination NOT OR Source V Destination → Destination OR ,Dn OR Dn, ORI Immediate Data V Destination → Destination ORI # , ORI to CCR Source V CCR → CCR ORI # ,CCR ORI to SR If supervisor state then Source V SR → SR else TRAP ORI # ,SR PEA Sp – 4 → SP; → (SP) PEA RESET If supervisor state then Assert RESET Line else TRAP RESET ROL, ROR Destination Rotated by → Destination ROd 1 Rx,Dy ROd 1 # ,Dy ROd 1 ROXL, ROXR Destination Rotated with X by → Destination ROXd 1 Dx,Dy ROXd 1 # ,Dy ROXd 1 RTD (SP) → PC; SP + 4 + d → SP RTD # MOTOROLA <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-13
Page 1 and 2: µ MOTOROLA M68000 8-/16-/32-Bit Mi
Page 3 and 4: TABLE OF CONTENTS (Continued) Parag
Page 5 and 6: TABLE OF CONTENTS (Continued) Parag
Page 7 and 8: LIST OF ILLUSTRATIONS Figure Page N
Page 9 and 10: LIST OF ILLUSTRATIONS (Concluded) F
Page 11 and 12: LIST OF TABLES (Concluded) Table Pa
Page 13 and 14: 1.1 MC68000 The MC68000 is the firs
Page 15 and 16: SECTION 2 INTRODUCTION The section
Page 17 and 18: tables. The SFC and DFC registers a
Page 19 and 20: Register Direct Addressing Data Reg
Page 21 and 22: BIT DATA 1 BYTE = 8 BITS 7 6 5 4 3
Page 23 and 24: Notation for operands: PC — Progr
Page 25: Table 2-2. Instruction Set Summary
Page 29 and 30: SECTION 3 SIGNAL DESCRIPTION This s
Page 31 and 32: V CC (2) GND(2) CLK ADDRESS BUS DAT
Page 33 and 34: Table 3-1. Data Strobe Control of D
Page 35 and 36: 3.6 SYSTEM CONTROL The system contr
Page 37 and 38: Table 3-3. Function Code Outputs Fu
Page 39 and 40: SECTION 4 8-BIT BUS OPERATION The f
Page 41 and 42: A bus cycle consists of eight state
Page 43 and 44: The descriptions of the eight state
Page 45 and 46: CLK S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S
Page 47 and 48: SECTION 5 16-BIT BUS OPERATION The
Page 49 and 50: CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S
Page 51 and 52: The word and byte write-cycle timin
Page 53 and 54: STATE 7 On the falling edge of the
Page 55 and 56: STATE 12 STATE 13 STATE 14 STATE 15
Page 57 and 58: The breakpoint acknowledge cycle is
Page 59 and 60: PROCESSOR REQUESTING DEVICE REQUEST
Page 61 and 62: us request signal. When no acknowle
Page 63 and 64: RA 1 RA GT 1 XA RA GT RA GT RA XX R
Page 65 and 66: BUS RELEASED FROM THREE STATE AND P
Page 67 and 68: BUS THREE-STATED BG ASSERTED BR VAL
Page 69 and 70: BUS THREE-STATED BG ASSERTED BR VAL
Page 71 and 72: CLK S0 S2 S4 S6 FC2-FC0 A23-A1 AS U
Page 73 and 74: CLK S0 S2 S4 S6 S0 S2 S4 S6 FC2-FC0
Page 75 and 76: A double bus fault occurs during a
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Case No. Control Signal 1 DTACK BER
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ADDR AS R/W UDS/LDS DATA DTACK Figu
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ADDR 11 AS 20A R/W 22 UDS/LDS 55 26
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On the rising edge of the clock, at
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Parameter #47 of Section 10 Electri
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The privilege mode is a mechanism f
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6.2 EXCEPTION PROCESSING The proces
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equests from peripheral devices for
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6.2.3 Multiple Exceptions These par
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SSP EVEN BYTE ODD BYTE 7 0 7 0 15 0
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interrupt priority mask is set at l
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A signed divide (DIVS) or unsigned
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After the execution of the instruct
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. 15 14 13 12 11 10 9 8 7 6 5 4 3 2
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6.4 RETURN FROM EXCEPTION (MC68010)
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Table 7-1. Effective Address Calcul
Page 109 and 110:
In Table 7-5, the following notatio
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CLR Table 7-7. Single Operand Instr
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7.9 JMP, JSR, LEA, PEA, AND MOVEM I
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Table 7-13. Miscellaneous Instructi
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SECTION 8 16-BIT INSTRUCTION EXECUT
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Table 8-3. Move Long Instruction Ex
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Table 8-5. Immediate Instruction Ex
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8.7 BIT MANIPULATION INSTRUCTION EX
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Table 8-11. Multiprecision Instruct
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the handler routine. The total numb
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9.1 OPERAND EFFECTIVE ADDRESS CALCU
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Table 9-4. Move Long Instruction Ex
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9.4 IMMEDIATE INSTRUCTION EXECUTION
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Table 9-11. Single Operand Instruct
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Table 9-15. Conditional Instruction
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Table 9-18. Miscellaneous Instructi
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SECTION 10 ELECTRICAL AND THERMAL C
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Table 10-1 summarizes maximum power
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is lost through the active P-channe
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10.6 MC68000/68008/68010 DC ELECTRI
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. 10.9 MC68008 AC ELECTRICAL SPECIF
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Num Characteristic 8 MHz* 10 MHz* 1
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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10.11 AC ELECTRICAL SPECIFICATIONS
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10.12 AC ELECTRICAL SPECIFICATIONS
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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10.13 MC68EC000 DC ELECTRICAL SPECI
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Num Characteristic 8 MHz 10 MHz 12.
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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CLK 47 33 BR 34 35 36 BG 39 38 58 A
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11-2 M68000 8-/16-/32-BIT MICROPROC
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R/W LDS UDS AS D0 D1 D2 D3 D4 D5 D6
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A3 1 48 A2 A4 2 47 A1 A5 3 46 A0 A6
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64 33 L SUFFIX 746-03 B 1 32 A F C
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64 33 L SUFFIX 746-01 B 1 32 A F C
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Figure 11-11. Case 765A-05—RC Suf
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1. Fetch the MOVE instruction. 2. F
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