M68000 Microprocessor User's Manual

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Table 2-2. Instruction Set Summary (Sheet 4 of 4) Opcode Operation Syntax RTE RTR If supervisor state then (SP) → SR; SP + 2 → SP; (SP) → PC; SP + 4 → SP; restore state and deallocate stack according to (SP) else TRAP (SP) → CCR; SP + 2 → SP; (SP) → PC; SP + 4 → SP RTE RTR RTS (SP) → PC; SP + 4 → SP RTS SBCD Destination10 – Source10 – X → Destination SBCD Dx,Dy SBCD –(Ax),–(Ay) Scc STOP If condition true then 1s → Destination else 0s → Destination If supervisor state then Immediate Data → SR; STOP else TRAP Scc STOP # SUB Destination – Source → Destination SUB ,Dn SUB Dn, SUBA Destination – Source → Destination SUBA ,An SUBI Destination – Immediate Data → Destination SUBI # , SUBQ Destination – Immediate Data → Destination SUBQ # , SUBX Destination – Source – X → Destination SUBX Dx,Dy SUBX –(Ax),–(Ay) SWAP Register [31:16] ↔ Register [15:0] SWAP Dn TAS TRAP Destination Tested → Condition Codes; 1 → bit 7 of Destination SSP – 2 → SSP; Format/Offset → (SSP); SSP – 4 → SSP; PC → (SSP); SSP–2 → SSP; SR → (SSP); Vector Address → PC TAS TRAPV If V then TRAP TRAPV TRAP # TST Destination Tested → Condition Codes TST UNLK An → SP; (SP) → An; SP + 4 → SP UNLK An NOTE: d is direction, L or R. 2-14 <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
SECTION 3 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals. The input and output signals can be functionally organized into the groups shown in Figure 3-1 (for the MC68000, the MC68HC000 and the MC68010), Figure 3-2 ( for the MC68HC001), Figure 3-3 (for the MC68EC000), Figure 3-4 (for the MC68008, 48-pin version), and Figure 3-5 (for the MC68008, 52-pin version). The following paragraphs provide brief descriptions of the signals and references (where applicable) to other paragraphs that contain more information about the signals. NOTE The terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of "active-low" and "active-high" signals. The term assert or assertion is used to indicate that a signal is active or true, independently of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. V CC (2) GND(2) CLK ADDRESS BUS A23–A1 DATA BUS D15–D0 AS PROCESSOR STATUS FC0 FC1 FC2 R/W UDS LDS DTACK ASYNCHRONOUS BUS CONTROL MC6800 PERIPHERAL CONTROL E VMA VPA BR BG BGACK BUS ARBITRATION CONTROL SYSTEM CONTROL BERR RESET HALT IPL0 IPL1 IPL2 INTERRUPT CONTROL Figure 3-1. Input and Output Signals (MC68000, MC68HC000 and MC68010) MOTOROLA <strong>M68000</strong> 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3- 1
Page 1 and 2: µ MOTOROLA M68000 8-/16-/32-Bit Mi
Page 3 and 4: TABLE OF CONTENTS (Continued) Parag
Page 5 and 6: TABLE OF CONTENTS (Continued) Parag
Page 7 and 8: LIST OF ILLUSTRATIONS Figure Page N
Page 9 and 10: LIST OF ILLUSTRATIONS (Concluded) F
Page 11 and 12: LIST OF TABLES (Concluded) Table Pa
Page 13 and 14: 1.1 MC68000 The MC68000 is the firs
Page 15 and 16: SECTION 2 INTRODUCTION The section
Page 17 and 18: tables. The SFC and DFC registers a
Page 19 and 20: Register Direct Addressing Data Reg
Page 21 and 22: BIT DATA 1 BYTE = 8 BITS 7 6 5 4 3
Page 23 and 24: Notation for operands: PC — Progr
Page 25 and 26: Table 2-2. Instruction Set Summary
Page 27: Table 2-2. Instruction Set Summary
Page 31 and 32: V CC (2) GND(2) CLK ADDRESS BUS DAT
Page 33 and 34: Table 3-1. Data Strobe Control of D
Page 35 and 36: 3.6 SYSTEM CONTROL The system contr
Page 37 and 38: Table 3-3. Function Code Outputs Fu
Page 39 and 40: SECTION 4 8-BIT BUS OPERATION The f
Page 41 and 42: A bus cycle consists of eight state
Page 43 and 44: The descriptions of the eight state
Page 45 and 46: CLK S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S
Page 47 and 48: SECTION 5 16-BIT BUS OPERATION The
Page 49 and 50: CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S
Page 51 and 52: The word and byte write-cycle timin
Page 53 and 54: STATE 7 On the falling edge of the
Page 55 and 56: STATE 12 STATE 13 STATE 14 STATE 15
Page 57 and 58: The breakpoint acknowledge cycle is
Page 59 and 60: PROCESSOR REQUESTING DEVICE REQUEST
Page 61 and 62: us request signal. When no acknowle
Page 63 and 64: RA 1 RA GT 1 XA RA GT RA GT RA XX R
Page 65 and 66: BUS RELEASED FROM THREE STATE AND P
Page 67 and 68: BUS THREE-STATED BG ASSERTED BR VAL
Page 69 and 70: BUS THREE-STATED BG ASSERTED BR VAL
Page 71 and 72: CLK S0 S2 S4 S6 FC2-FC0 A23-A1 AS U
Page 73 and 74: CLK S0 S2 S4 S6 S0 S2 S4 S6 FC2-FC0
Page 75 and 76: A double bus fault occurs during a
Page 77 and 78: Case No. Control Signal 1 DTACK BER
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ADDR AS R/W UDS/LDS DATA DTACK Figu
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ADDR 11 AS 20A R/W 22 UDS/LDS 55 26
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On the rising edge of the clock, at
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Parameter #47 of Section 10 Electri
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The privilege mode is a mechanism f
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6.2 EXCEPTION PROCESSING The proces
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equests from peripheral devices for
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6.2.3 Multiple Exceptions These par
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SSP EVEN BYTE ODD BYTE 7 0 7 0 15 0
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interrupt priority mask is set at l
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A signed divide (DIVS) or unsigned
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After the execution of the instruct
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. 15 14 13 12 11 10 9 8 7 6 5 4 3 2
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6.4 RETURN FROM EXCEPTION (MC68010)
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Table 7-1. Effective Address Calcul
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In Table 7-5, the following notatio
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CLR Table 7-7. Single Operand Instr
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7.9 JMP, JSR, LEA, PEA, AND MOVEM I
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Table 7-13. Miscellaneous Instructi
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SECTION 8 16-BIT INSTRUCTION EXECUT
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Table 8-3. Move Long Instruction Ex
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Table 8-5. Immediate Instruction Ex
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8.7 BIT MANIPULATION INSTRUCTION EX
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Table 8-11. Multiprecision Instruct
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the handler routine. The total numb
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9.1 OPERAND EFFECTIVE ADDRESS CALCU
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Table 9-4. Move Long Instruction Ex
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9.4 IMMEDIATE INSTRUCTION EXECUTION
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Table 9-11. Single Operand Instruct
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Table 9-15. Conditional Instruction
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Table 9-18. Miscellaneous Instructi
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SECTION 10 ELECTRICAL AND THERMAL C
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Table 10-1 summarizes maximum power
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is lost through the active P-channe
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10.6 MC68000/68008/68010 DC ELECTRI
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. 10.9 MC68008 AC ELECTRICAL SPECIF
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Num Characteristic 8 MHz* 10 MHz* 1
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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10.11 AC ELECTRICAL SPECIFICATIONS
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10.12 AC ELECTRICAL SPECIFICATIONS
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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10.13 MC68EC000 DC ELECTRICAL SPECI
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Num Characteristic 8 MHz 10 MHz 12.
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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CLK 47 33 BR 34 35 36 BG 39 38 58 A
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11-2 M68000 8-/16-/32-BIT MICROPROC
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R/W LDS UDS AS D0 D1 D2 D3 D4 D5 D6
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A3 1 48 A2 A4 2 47 A1 A5 3 46 A0 A6
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64 33 L SUFFIX 746-03 B 1 32 A F C
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64 33 L SUFFIX 746-01 B 1 32 A F C
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Figure 11-11. Case 765A-05—RC Suf
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1. Fetch the MOVE instruction. 2. F
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