M68000 Microprocessor User's Manual

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TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 6 Exception Processing 6.2.4 Exception Stack Frames.......................................................................... 6-9 6.2.5 Exception Processing Sequence ............................................................ 6-11 6.3 Processing of Specific Exceptions ............................................................. 6-11 6.3.1 Reset ...................................................................................................... 6-11 6.3.2 Interrupts ................................................................................................ 6-12 6.3.3 Uninitialized Interrupt .............................................................................. 6-13 6.3.4 Spurious Interrupt ................................................................................... 6-13 6.3.5 Instruction Traps ..................................................................................... 6-13 6.3.6 Illegal and Unimplemented Instructions .................................................. 6-14 6.3.7 Privilege Violations ................................................................................. 6-15 6.3.8 Tracing .................................................................................................... 6-15 6.3.9 Bus Errors ............................................................................................... 6-16 6.3.9.1 Bus Error ............................................................................................. 6-16 6.3.9.2 Bus Error (MC68010) .......................................................................... 6-17 6.3.10 Address Error ......................................................................................... 6-19 6.4 Return From Exception (MC68010) ........................................................... 6-20 Section 7 8-Bit Instruction Timing 7.1 Operand Effective Address Calculation Times............................................ 7-1 7.2 Move Instruction Execution Times .............................................................. 7-2 7.3 Standard Instruction Execution Times......................................................... 7-3 7.4 Immediate Instruction Execution Times ...................................................... 7-4 7.5 Single Operand Instruction Execution Times .............................................. 7-5 7.6 Shift/Rotate Instruction Execution Times .................................................... 7-6 7.7 Bit Manipulation Instruction Execution Times ............................................. 7-7 7.8 Conditional Instruction Execution Times ..................................................... 7-7 7.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times............... 7-8 7.10 Multiprecision Instruction Execution Times ................................................. 7-8 7.11 Miscellaneous Instruction Execution Times ................................................ 7-9 7.12 Exception Processing Instruction Execution Times ................................... 7-10 MOTOROLA <strong>M68000</strong> USER’S MANUAL ix
TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 8 16-Bit Instruction Timing 8.1 Operand Effective Address Calculation Times ........................................... 8-1 8.2 Move Instruction Execution Times .............................................................. 8-2 8.3 Standard Instruction Execution Times ........................................................ 8-3 8.4 Immediate Instruction Execution Times ...................................................... 8-4 8.5 Single Operand Instruction Execution Times .............................................. 8-5 8.6 Shift/Rotate Instruction Execution Times .................................................... 8-6 8.7 Bit Manipulation Instruction Execution Times ............................................. 8-7 8.8 Conditional Instruction Execution Times ..................................................... 8-7 8.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .............. 8-8 8.10 Multiprecision Instruction Execution Times ................................................. 8-8 8.11 Miscellaneous Instruction Execution Times ................................................ 8-9 8.12 Exception Processing Instruction Execution Times .................................. 8-10 Section 9 MC68010 Instruction Timing 9.1 Operand Effective Address Calculation Times ........................................... 9-2 9.2 Move Instruction Execution Times .............................................................. 9-2 9.3 Standard Instruction Execution Times ........................................................ 9-4 9.4 Immediate Instruction Execution Times ...................................................... 9-6 9.5 Single Operand Instruction Execution Times .............................................. 9-6 9.6 Shift/Rotate Instruction Execution Times .................................................... 9-8 9.7 Bit Manipulation Instruction Execution Times ............................................. 9-9 9.8 Conditional Instruction Execution Times ..................................................... 9-9 9.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times ............ 9-10 9.10 Multiprecision Instruction Execution Times ...............................................9-11 9.11 Miscellaneous Instruction Execution Times .............................................. 9-11 9.12 Exception Processing Instruction Execution Times .................................. 9-13 Section 10 Electrical and Thermal Characteristics 10.1 Maximum Ratings ..................................................................................... 10-1 10.2 Thermal Characteristics ............................................................................ 10-1 10.3 Power Considerations ............................................................................... 10-2 10.4 CMOS Considerations .............................................................................. 10-4 10.5 AC Electrical Specifications Definitions.....................................................10-5 10.6 MC68000/68008/68010 DC Electrical Characteristics .............................. 10-7 10.7 DC Electrical Characteristics .................................................................... 10-8 10.8 AC Electrical Specifications—Clock Timing .............................................. 10-8 x <strong>M68000</strong> USER’S MANUAL MOTOROLA
Page 1 and 2: µ MOTOROLA M68000 8-/16-/32-Bit Mi
Page 3: TABLE OF CONTENTS (Continued) Parag
Page 7 and 8: LIST OF ILLUSTRATIONS Figure Page N
Page 9 and 10: LIST OF ILLUSTRATIONS (Concluded) F
Page 11 and 12: LIST OF TABLES (Concluded) Table Pa
Page 13 and 14: 1.1 MC68000 The MC68000 is the firs
Page 15 and 16: SECTION 2 INTRODUCTION The section
Page 17 and 18: tables. The SFC and DFC registers a
Page 19 and 20: Register Direct Addressing Data Reg
Page 21 and 22: BIT DATA 1 BYTE = 8 BITS 7 6 5 4 3
Page 23 and 24: Notation for operands: PC — Progr
Page 25 and 26: Table 2-2. Instruction Set Summary
Page 27 and 28: Table 2-2. Instruction Set Summary
Page 29 and 30: SECTION 3 SIGNAL DESCRIPTION This s
Page 31 and 32: V CC (2) GND(2) CLK ADDRESS BUS DAT
Page 33 and 34: Table 3-1. Data Strobe Control of D
Page 35 and 36: 3.6 SYSTEM CONTROL The system contr
Page 37 and 38: Table 3-3. Function Code Outputs Fu
Page 39 and 40: SECTION 4 8-BIT BUS OPERATION The f
Page 41 and 42: A bus cycle consists of eight state
Page 43 and 44: The descriptions of the eight state
Page 45 and 46: CLK S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S
Page 47 and 48: SECTION 5 16-BIT BUS OPERATION The
Page 49 and 50: CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S
Page 51 and 52: The word and byte write-cycle timin
Page 53 and 54: STATE 7 On the falling edge of the
Page 55 and 56:
STATE 12 STATE 13 STATE 14 STATE 15
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The breakpoint acknowledge cycle is
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PROCESSOR REQUESTING DEVICE REQUEST
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us request signal. When no acknowle
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RA 1 RA GT 1 XA RA GT RA GT RA XX R
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BUS RELEASED FROM THREE STATE AND P
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BUS THREE-STATED BG ASSERTED BR VAL
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BUS THREE-STATED BG ASSERTED BR VAL
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CLK S0 S2 S4 S6 FC2-FC0 A23-A1 AS U
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CLK S0 S2 S4 S6 S0 S2 S4 S6 FC2-FC0
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A double bus fault occurs during a
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Case No. Control Signal 1 DTACK BER
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ADDR AS R/W UDS/LDS DATA DTACK Figu
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ADDR 11 AS 20A R/W 22 UDS/LDS 55 26
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On the rising edge of the clock, at
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Parameter #47 of Section 10 Electri
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The privilege mode is a mechanism f
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6.2 EXCEPTION PROCESSING The proces
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equests from peripheral devices for
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6.2.3 Multiple Exceptions These par
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SSP EVEN BYTE ODD BYTE 7 0 7 0 15 0
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interrupt priority mask is set at l
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A signed divide (DIVS) or unsigned
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After the execution of the instruct
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. 15 14 13 12 11 10 9 8 7 6 5 4 3 2
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6.4 RETURN FROM EXCEPTION (MC68010)
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Table 7-1. Effective Address Calcul
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In Table 7-5, the following notatio
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CLR Table 7-7. Single Operand Instr
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7.9 JMP, JSR, LEA, PEA, AND MOVEM I
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Table 7-13. Miscellaneous Instructi
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SECTION 8 16-BIT INSTRUCTION EXECUT
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Table 8-3. Move Long Instruction Ex
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Table 8-5. Immediate Instruction Ex
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8.7 BIT MANIPULATION INSTRUCTION EX
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Table 8-11. Multiprecision Instruct
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the handler routine. The total numb
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9.1 OPERAND EFFECTIVE ADDRESS CALCU
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Table 9-4. Move Long Instruction Ex
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9.4 IMMEDIATE INSTRUCTION EXECUTION
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Table 9-11. Single Operand Instruct
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Table 9-15. Conditional Instruction
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Table 9-18. Miscellaneous Instructi
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SECTION 10 ELECTRICAL AND THERMAL C
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Table 10-1 summarizes maximum power
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is lost through the active P-channe
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10.6 MC68000/68008/68010 DC ELECTRI
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. 10.9 MC68008 AC ELECTRICAL SPECIF
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Num Characteristic 8 MHz* 10 MHz* 1
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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10.11 AC ELECTRICAL SPECIFICATIONS
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10.12 AC ELECTRICAL SPECIFICATIONS
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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CLK 47 33 BR BG 1 BGACK 35 47 34 37
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10.13 MC68EC000 DC ELECTRICAL SPECI
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Num Characteristic 8 MHz 10 MHz 12.
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S0 S1 S2 S3 S4 S5 S6 S7 CLK 6A FC2-
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CLK 47 33 BR 34 35 36 BG 39 38 58 A
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11-2 M68000 8-/16-/32-BIT MICROPROC
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R/W LDS UDS AS D0 D1 D2 D3 D4 D5 D6
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A3 1 48 A2 A4 2 47 A1 A5 3 46 A0 A6
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64 33 L SUFFIX 746-03 B 1 32 A F C
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64 33 L SUFFIX 746-01 B 1 32 A F C
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Figure 11-11. Case 765A-05—RC Suf
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1. Fetch the MOVE instruction. 2. F
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