FDD6682/FDU6682 30V N-Channel PowerTrench® MOSFET

FDD6682/FDU6682
30V N-Channel PowerTrench MOSFET
General Description
Features
June 2004
FDD6682/FDU6682
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
low gate charge, low RDS( ON) and fast switching speed.
Applications
• DC/DC converter
• Motor Drives
• 75 A, 30 V R DS(ON) = 6.2 mΩ @ V GS = 10 V
R DS(ON) = 8.0 mΩ @ V GS = 4.5 V
• Low gate charge
• Fast switching
• High performance trench technology for extremely
low R DS(ON)
D
G
D
S
D-PAK TO-252
(TO-252)
G D S
I-PAK
(TO-251AA)
G
S
Absolute Maximum Ratings
TA=25 o C unless otherwise noted
P D
Symbol Parameter Ratings Units
V DSS Drain-Source Voltage 30 V
V GSS Gate-Source Voltage ±20
I D Drain Current – Continuous (Note 3) 75 A
– Pulsed (Note 1a) 100
Power Dissipation for Single Operation (Note 1) 71
W
(Note 1a) 3.8
(Note 1b) 1.6
T J, T STG Operating and Storage Junction Temperature Range –55 to +175 °C
Thermal Characteristics
R θJC Thermal Resistance, Junction-to-Case (Note 1) 2.1 °C/W
R θJA Thermal Resistance, Junction-to-Ambient (Note 1a) 40
R θJA Thermal Resistance, Junction-to-Ambient (Note 1b) 96
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape width Quantity
FDD6682 FDD6682 D-PAK (TO-252) 13’’ 12mm 2500 units
FDU6682 FDU6682 I-PAK (TO-251) Tube N/A 75
©2004 Fairchild Semiconductor Corporation FDD6682/FDU6682 Rev H(W)

Electrical Characteristics
T A
= 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Drain-Source Avalanche Ratings (Note 2)
W DSS Drain-Source Avalanche Energy Single Pulse, V DD = 15 V, I D = 17 A 240 mJ
I AR Drain-Source Avalanche Current 17 A
Off Characteristics
BV DSS Drain–Source Breakdown Voltage V GS = 0 V, I D = 250 µA 30 V
∆BVDSS Breakdown Voltage Temperature I D = 250 µA, Referenced to 25°C 20 mV/°C
∆T J Coefficient
I DSS Zero Gate Voltage Drain Current V DS = 24 V, V GS = 0 V 1 µA
I GSS Gate–Body Leakage V GS = ±20 V, V DS = 0 V ±100 nA
FDD6682/FDU6682
On Characteristics (Note 2)
V GS(th) Gate Threshold Voltage V DS = V GS, I D = 250 µA 1 1.9 3 V
∆VGS(th) Gate Threshold Voltage
I D = 250 µA, Referenced to 25°C –7 mV/°C
∆T J
Temperature Coefficient
R DS(on) Static Drain–Source
V GS = 10 V, I D = 17 A
5.2 6.2 mΩ
On–Resistance
V GS = 4.5 V, I D = 15 A
6.4 8
V GS = 10 V, I D = 17 A, T J=125°C
8.0 11.9
I D(on) On–State Drain Current V GS = 10 V, V DS = 5 V 50 A
g FS Forward Transconductance V DS = 5 V, I D = 17 A 65 S
Dynamic Characteristics
C iss Input Capacitance 2400 pF
V DS = 15 V, V GS = 0 V,
C oss Output Capacitance 577 pF
f = 1.0 MHz
C rss Reverse Transfer Capacitance
258 pF
R G Gate Resistance V GS = 15 mV, f = 1.0 MHz 1.4 Ω
Switching Characteristics (Note 2)
t d(on) Turn–On Delay Time 14 20 ns
t r Turn–On Rise Time V DD = 15 V, I D = 1 A,
12 37 ns
t d(off) Turn–Off Delay Time V GS = 10 V, R GEN = 6 Ω
38 64 ns
t f
Turn–Off Fall Time
18 32 ns
Q g Total Gate Charge 24 31 nC
Q gs Gate–Source Charge
V DS = 15V,
V GS = 5 V
I D = 17 A,
6.5 nC
Gate–Drain Charge
8.1 nC
Q gd
FDD6682/FDU6682 Rev H(W)

Electrical Characteristics (continued)
T A
= 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Drain–Source Diode Characteristics and Maximum Ratings
I S Maximum Continuous Drain–Source Diode Forward Current 3.2 A
V SD Drain–Source Diode Forward V GS = 0 V, I S = 3.2 A (Note 2) 0.7 1.2 V
Voltage
t rr Diode Reverse Recovery Time I F = 17 A, d iF/d t = 100 A/µs 32 nS
Q rr Diode Reverse Recovery Charge 20 nC
FDD6682/FDU6682
Notes:
1. R θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θJC
is guaranteed by design while R θCA
is determined by the user's board design.
a) R θJA
= 40°C/W when mounted on a
1in 2 pad of 2 oz copper
b) R θJA
= 96°C/W when mounted
on a minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. Maximum current is calculated as:
PD
R DS(ON)
where PD is maximum power dissipation at TC = 25°C and RDS(on) is at TJ(max) and VGS = 10V. Package current limitation is 21A
FDD6682/FDU6682 Rev H(W)

Typical Characteristics
I D , DRAIN CURRENT (A)
100
V GS =10V
4.0V
80
6.0V
4.5V
60
40
20
3.5V
3.0V
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
2
1.8
1.6
1.4
1.2
1
V GS = 3.5V
4.0V
4.5V
5.0V
10V
FDD6682/FDU6682
0
0 1 2 3
V DS , DRAIN-SOURCE VOLTAGE (V)
0.8
0 20 40 60 80 100
I D , DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
2
0.02
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.8
1.6
1.4
1.2
1
0.8
I D = 17A
V GS = 10V
R DS(ON) , ON-RESISTANCE (OHM)
0.015
0.01
0.005
T A = 25 o C
T A = 125 o C
I D = 8.5A
0.6
-50 -25 0 25 50 75 100 125 150 175
T J, JUNCTION TEMPERATURE ( o C)
0
2 4 6 8 10
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
I D , DRAIN CURRENT (A)
80
V DS = 5V
60
40
20
T A =125 o C
25 o C
-55 o C
0
1 2 3 4
V GS , GATE TO SOURCE VOLTAGE (V)
I S, REVERSE DRAIN CURRENT (A)
100
10
1
0.1
0.01
0.001
0.0001
V GS = 0V
T A = 125 o C
25 o C
-55 o C
0 0.2 0.4 0.6 0.8 1 1.2
V SD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
FDD6682/FDU6682 Rev H(W)

Typical Characteristics
V GS, GATE-SOURCE VOLTAGE (V)
10
V
I D = 17A
DS = 10V
8
20V
6
4
2
15V
CAPACITANCE (pF)
3500
3000
2500
2000
1500
1000
500
C ISS
C OSS
C RSS
f = 1MHz
V GS = 0 V
FDD6682/FDU6682
0
0 10 20 30 40 50
Q g , GATE CHARGE (nC)
0
0 5 10 15 20 25 30
V DS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
1000
100
I D , DRAIN CURRENT (A)
100
10
1
0.1
R DS(ON) LIMIT
V GS = 10V
SINGLE PULSE
R θJA = 96 o C/W
T A = 25 o C
10s
DC
100ms
1s
1ms
10ms
100µs
P(pk), PEAK TRANSIENT POWER (W)
80
60
40
20
SINGLE PULSE
R θJA = 96°C/W
T A = 25°C
0.01
0.01 0.1 1 10 100
V DS , DRAIN-SOURCE VOLTAGE (V)
0
0.01 0.1 1 10 100 1000
t 1 , TIME (sec)
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum
Power Dissipation
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.001
0.001 0.01 0.1 1 10 100 1000
t 1, TIME (sec)
R θJA (t) = r(t) * R θJA
R θJA = 96 °C/W
P(pk)
t 1
t 2
T J - T A = P * R θJA (t)
Duty Cycle, D = t 1 / t 2
Figure 11. Transient Thermal Response Curve
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDD6682/FDU6682 Rev H(W)

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failure to perform when properly used in accordance
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PRODUCT STATUS DEFINITIONS
Definition of Terms
FAST ®
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FPS
FRFET
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GTO
HiSeC
I 2 C
i-Lo
ImpliedDisconnect
Across the board. Around the world.
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MicroPak
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POP
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RapidConfigure
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µSerDes
SILENT SWITCHER ®
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SPM
Stealth
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SuperFET
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
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TINYOPTO
TruTranslation
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UltraFET ®
VCX
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In Design
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Full Production
This datasheet contains the design specifications for
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This datasheet contains preliminary data, and
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changes at any time without notice in order to improve
design.
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Rev. I11