A Scalable Noise De-Embedding Technique for On ... - IEEE Xplore

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005 649
A Scalable Noise De-Embedding Technique for
On-Wafer Microwave Device Characterization
Ming-Hsiang Cho, Guo-Wei Huang, Member, IEEE, Yueh-Hua Wang, and Lin-Kun Wu, Member, IEEE
Abstract—In this letter, we present a scalable and efficient noise
de-embedding procedure, which is based on transmission-line
theory and cascade configurations, for on-wafer microwave measurements
of silicon MOSFETs. The proposed de-embedding
procedure utilizes one open and one thru dummy structures
to eliminate the parasitic effects from the probe pads and the
input/output interconnects of a device-under-test (DUT), respectively.
This method can generate the scalable distributed
interconnect parameters to efficiently and precisely remove the
redundant parasitics of the DUTs with various device sizes and
arbitrary interconnect dimensions.
Index Terms—Calibration, de-embedding, MOSFET, noise,
-parameters.
I. INTRODUCTION
WITH the downscaling device channel length as well
as the increasing operation frequency, on-wafer measurement
and device modeling work on silicon MOSFETs
have become more and more significant for RF/microwave
circuit design. To extract the intrinsic device performance
from measurements, the unnecessary parasitics of the probe
pads and input/output interconnects must be exactly removed
from the measured data. In previous literature [1]–[3], several
parasitic de-embedding methods based on physical equivalent-circuit
models have been developed and extensively
utilized over the past decade. These physics-based methods
treat the device-under-test (DUT) as an intrinsic device connected
to the external parasitics, which come from the probe
pads and interconnects, in parallel-series configurations. As the
operation frequency becomes higher and/or the interconnect
length becomes longer, nevertheless, these equivalent-circuit
assumptions may be inappropriate. Recently, a cascade-based
de-embedding scheme [4] has been presented, which models
the probe pads, interconnects, and the intrinsic device in cascade
configurations and does not require any equivalent-circuit
representation. On the other hand, for the characterization
of devices in various sizes, the conventional de-embedding
methods mentioned above may occupy considerable chip
area for their corresponding dummy structures. Although the
ground-shielded measuring technique has been introduced to
offer the fixture scalability and mitigate the chip-area consumption
[5], the scalability of the interconnect parameters
Manuscript received March 2, 2005; revised May 25, 2005. The review of
this letter was arranged by Associate Editor F. Ellinger.
M. H. Cho and G.-W. Huang are with National Nano Device Laboratories,
Hsinchu 300, Taiwan, R.O.C. (e-mail: mhcho@mail.ndl.org.tw).
Y.-H. Wang and L.-K. Wu are with the Department of Communication Engineering,
National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LMWC.2005.856685
Fig. 1. Proposed de-embedding method. (a) DUT and its corresponding
dummy structures. (b) Schematic diagram.
for parasitic de-embedding has not been comprehensively
studied yet. In our previous work [6], a scalable -parameter
de-embedding method based on transmission-line theory and
cascade-configuration concept [4] for microwave on-wafer
characterization has been presented, and the de-embedding
procedure has been verified using thru dummy devices. In this
study, we further take the noise parameters into account in the
de-embedding procedure and also validate the applicability of
the proposed method with measurements on silicon MOSFETs.
We find that this scalable de-embedding method is indeed
suitable for on-wafer -parameter and noise measurements,
especially the on-wafer automatic characterization [7], of
multitype and multisize devices. To substantiate the proposed
method, MOSFETs fabricated using a standard 0.25- m
five-level CMOS process were characterized from 1 to 18 GHz.
II. THEORY OF NOISE DE-EMBEDDING
The proposed de-embedding method is illustrated in Fig. 1.
It should be noted that the shield-based structures are not
employed in this work for more general consideration. The
on-wafer test structures were implemented on silicon substrate
for microwave characterization of active devices. Unlike
the conventional de-embedding methods, which consume a
great deal of chip area for dummy patterns, the proposed
new theory requires only two dummy structures for parasitic
subtraction. After taking away the probe-pad parasitics with the
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650 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005
open dummy, the per-unit-length transmission-line parameters
of the thru dummy can be evaluated [6]. Then, DUTs with
various device sizes and interconnect lengths can be individually
de-embedded with the application of the interconnect
scalability.
Similar to the conventional cascade-based method [4],
a thru device can be simply modeled in cascade connection.
After de-embedding the pad parasitics from
and converting
the chain matrix to its -parameter matrix
, where the superscript “ ” denotes the inverse of the
matrix and , , and are, respectively,
the chain matrices of the intrinsic interconnects,
probe pads, and thru dummy, the interconnect characteristic
impedance and propagation constant can be calculated as
[8]
and
where is the impedance of the -parameter measurement
system, is the interconnect length, and
For the extraction of and , the “ ” signs in (1) and (2)
are used to correct the unreasonable solutions, such as negative
attenuation constants [8].
Based on the above results, the chain matrices of the
input and output interconnects with arbitrary line lengths can be
generated by respectively substituting the interconnect lengths
and into the chain matrix of a lossy transmission
line as
(1)
(2)
(3)
5) Convert to its -parameter matrix and
calculate the interconnect characteristic impedance
and propagation constant based on (1) and (2).
6) Create the chain matrices and
of the input and output interconnects by, respectively,
substituting the interconnect lengths and into (4).
7) Calculate the chain matrices of the input port
and the output port using
and
, respectively.
8) Convert to its chain matrix and
calculate the chain matrix of the intrinsic
device using .
9) Convert to , where is the intrinsic scattering
matrix of the DUT.
10) Convert and to their impedance matrices
and , respectively.
11) Calculate the noise correlation matrices
and from and
, respectively, where is
the Boltzmann’s constant and is the absolute temperature.
12) Convert and to their chain matrices
and using
and
, respectively, where the superscript
“ ” denotes the Hermitian conjugate of the matrix, and
the transformation matrix and are
and
13) Calculate the intrinsic correlation matrix
[9].
14) Calculate the intrinsic noise parameters , , and
from the noise correlation matrix using
(6)
(7)
(4)
The proposed -parameter and noise de-embedding procedure
based on cascade connection is listed as follows.
1) Measure the scattering parameters , ,
and of the DUT, open, and thru, respectively.
2) Measure the noise parameters , , and
of the DUT and calculate the correlation matrix
[9].
3) Convert to its admittance matrix and
calculate the chain matrix of the probe
pads from
4) Calculate the intrinsic interconnect parameters using
.
(5)
and
III. RESULTS AND DISCUSSION
(8)
(9)
(10)
The on-wafer -parameter and noise measurements were
performed with ATN NP5B Noise Parameter Measurement
System. To validate the proposed scalable de-embedding procedure
for active devices, three n-MOSFETs with the same
device dimensions and various interconnect lengths between

CHO et al.: SCALABLE NOISE DE-EMBEDDING TECHNIQUE 651
optimized input reflection coefficient versus frequency
characteristics of the three MOSFETs biased at 1.5 V
and 1.15 V. These results indicate that the intrinsic
noise parameters obtained from the conventional cascade-based
method [4] and proposed method are in good agreement over
the entire frequency range. Fig. 3 exhibits the measured and
de-embedded noise parameters versus drain current characteristics
of the three MOSFETs at 18 GHz. The interconnects at
input port of LS are longer than those of SL and SS and thus
have more impact on the measured noise parameters. However,
after finishing the noise de-embedding, the intrinsic noise
parameters of the three MOSFETs obtained from the conventional
cascade-based method and proposed scalable method
are approximately the same. Based on the above findings, we
can use this proposed de-embedding method instead of the
conventional one to efficiently calculate the intrinsic noise
parameters of the MOSFETs.
Fig. 2. Noise parameters versus frequency characteristics (a) NF , (b) R ,
(c) j0 j, and (d) 0 of three different n-MOSFETs—LS, SL, and
SS obtained from measurement results (lines), conventional de-embedding
method (open symbols), and proposed de-embedding method (solid symbols).
The DUTs are biased at V = 1.5 V and V = 1.15 V (I = 13.3 mA).
Fig. 3. Noise parameters versus drain current characteristics (a) NF ,
(b) R , (c) j0 j, and (d) 0 of three different n-MOSFETs obtained
from measurement results (lines), conventional method (open symbols), and
proposed method (solid symbols) at 18 GHz. The DUTs are biased at V =
1.5 V and I = 1–30 mA.
the probe pads and DUT—LS ( 200 m, 20 m),
SL ( 20 m, 200 m), and SS ( 20 m,
20 m), and their corresponding dummy structures were
designed and fabricated. The channel length and width of
the n-MOSFET are 0.24 and 110 m (10 m 11), respectively.
The interconnect width and the dimensions of probe
pads are 10 and 70 m 70 m, respectively. Fig. 2 shows
the measured and de-embedded noise parameters—minimum
noise figure , equivalent noise resistance , and
IV. CONCLUSION
In this study, a general noise de-embedding method suitable
for on-wafer device characterization has been presented and
verified with various devices. This method requires only one
open and one thru dummy structures to generate the scalable
and repeatable interconnect parameters for parasitic subtraction.
Therefore, the consumption of chip area for dummy structures
can be minimized. Compared with the conventional cascadebased
method, the proposed one can eliminate the unwanted parasitics
of the DUTs more efficiently.
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