Podium Presentation Template - Semiconductor Wafer Test Workshop

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Initial Test Plan • First design compared CRES on custom test chip designed for bump wafers – CRES Values compared to Cantilever • Data was only used to validate the probe card design concept, early work had stuck pins but did function electrically as desired. June 8 to 11, 2008 IEEE SW Test Workshop 8
Test Plan • Test a Power Management chip using both a cantilever ring and new vertical probe card with the same wafers and compare the probe yield and needle performance. • Optimize the cleaning frequency as required – Started at once per wafer – later 3-4 times per wafer – settled for every 3,000 touchdowns • Forced Multi touchdown per DUT to accelerate wear & tear • Evaluate any degradation to the PCB and yields June 8 to 11, 2008 IEEE SW Test Workshop 9
Page 1 and 2: Robert Doherty Analog Devices, Inc.
Page 3 and 4: Overview • Analog Devices Inc. te
Page 5 and 6: Project Objective • Develop a low
Page 7: Vertical Probe Benefits • Longer
Page 11 and 12: Comparison of Substrate vs Direct D
Page 13 and 14: Comparison of Substrate vs Direct D
Page 15 and 16: Direct Dock PCB Design • Eliminat
Page 17 and 18: Vertical Direct Dock Probe Card •
Page 19 and 20: BeCu Pointed Saber ® Probe Propert
Page 21 and 22: Reduced Probe Marks • Pointed pro
Page 23 and 24: Results June 8 to 11, 2008 IEEE SW
Page 25 and 26: Results: Scrub Mark Comparison Vert
Page 27 and 28: Probe Mark Analysis - 5 um pad pene
Page 29 and 30: Cleaning Process Used • Using Int
Page 31 and 32: Testing Conclusions • Direct Dock
Page 33: Acknowledgements • John McHatton

Podium Presentation Template - Semiconductor Wafer Test Workshop

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