ARM Compiler toolchain v4.1 for µVision Using the Compiler

Compiler Coding Practices
5.44 Limitations on hardware handling of floating-point arithmetic
ARM Vector Floating-Point (VFP) coprocessors are optimized to process well-defined
floating-point code in hardware. Arithmetic operations that occur too rarely, or that are too
complex, are not handled in hardware. Instead, processing of these cases must be handled in
software. This approach minimizes the amount of coprocessor hardware required and reduces
costs.
Code provided to handle cases the VFP hardware is unable to process is known as VFP support
code. When the VFP hardware is unable to deal with a situation directly, it bounces the case to
VFP support code for more processing. For example, VFP support code might be called to
process any of the following:
• floating-point operations involving NaNs
• floating-point operations involving denormals.
• floating-point overflow
• floating-point underflow
• inexact results
• division-by-zero errors
• invalid operations.
When support code is in place, the VFP supports a fully IEEE 754-compliant floating-point
model.
5.44.1 See also
Concepts
• Compiler support for floating-point arithmetic on page 5-53
• Implementation of Vector Floating-Point (VFP) support code on page 5-60.
Other information
• Institute of Electrical and Electronics Engineers, http://www.ieee.org
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