ARM Compiler toolchain v4.1 for µVision Using the Compiler

Using the Inline and Embedded Assemblers of the ARM Compiler
7.30 Inline assembler and virtual registers
Inline assembly code for the compiler always specifies virtual registers. The compiler chooses
the physical registers to be used for each instruction during code generation, and enables the
compiler to fully optimize the assembly code and surrounding C or C++ code.
The pc (r15), lr (r14), and sp (r13) registers cannot be accessed at all. An error message is
generated when these registers are accessed.
The initial values of virtual registers are undefined. Therefore, you must write to virtual registers
before reading them. The compiler warns you if code reads a virtual register before writing to
it. The compiler also generates these warnings for legacy code that relies on particular values in
physical registers at the beginning of inline assembly code, for example:
int add(int i, int j)
{
int res;
__asm
{
ADD res, r0, r1
}
return res;
}
// relies on i passed in r0 and j passed in r1
This code generates warning and error messages.
The errors are generated because virtual registers r0 and r1 are read before writing to them. The
warnings are generated because r0 and r1 must be defined as C or C++ variables. The corrected
code is:
int add(int i, int j)
{
int res;
__asm
{
ADD res, i, j
}
return res;
}
7.30.1 See also
Concepts
• Inline assembler and register access in C and C++ code on page 7-18.
Other information
Migration and Compatibility:
• Chapter 2 Migrating from RVCT v4.0 for µVision to ARM Compiler v4.1 for µVision.
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