80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

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LITERATURE To order Intel Literature or obtain literature pricing information in the U.S. and Canada call or write Intel Literature Sales. In Europe and other international locations, please contact your local sales office or distributor. INTEL LITERATURE SALES P.O. BOX 7641 Mt. Prospect, IL 60056-7641 In the U.S. and Canada call toll free (800) 548-4725 CURRENT HANDBOOKS Product line handbooks contain data sheets, application notes, article reprints and other design information. TITLE SET OF 11 HANDBOOKS (Available in U.S. and Canada only) EMBEDDED APPLICATIONS 8-BIT EMBEDDED CONTROLLERS 16-BIT EMBEDDED CONTROLLERS 16/32-BIT EMBEDDED PROCESSORS MEMORY MICROCOMMUNICATIONS (2 volume set) MICROCOMPUTER BOARDS AND SYSTEMS MICROPROCESSORS PERIPHERALS PRODUCT GUIDE (Overview of Intel's complete product lines) PROGRAMMABLE LOGIC LITERATURE ORDER NUMBER 231003 270648 270645 270646 270647 210830 231658 280407 230843 296467 210846 296083 ADDITIONAL LITERATURE (Not included in handbook set) AUTOMOTIVE COMPONENTS QUALITY/RELIABILITY HANDBOOK INTERNATIONAL LITERATURE GUIDE LITERATURE PRICE LIST (U.S. and Canada) (Comprehensive list of current Intel Literature) MILITARY (2 volume set) SYSTEMS QUALITY/RELIABILITY 231792 210997 E00029 210620 210461 231762 LlTINCOV/010590
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Page 4 and 5: INTERNATIONAL LITERATURE ORDER FORM
Page 6 and 7: inter Intel Corporation makes no wa
Page 9 and 10: Table of Contents CHAPTER 1 INTRODU
Page 11 and 12: Table of Contents (continued) 8.1.2
Page 13: Table of Contents (continued) APPEN
Page 17 and 18: CHAPTER 1 INTRODUCTION The 80C 186E
Page 19 and 20: INTRODUCTION Some customers may not
Page 21: INTRODUCTION 80C186EB: This refers
Page 25 and 26: CHAPTER 2 OVERVIEW OF THE 80C186 FA
Page 27 and 28: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 33 and 34: inter OVERVIEW OF THE 80C186 FAMILY
Page 53 and 54:
OVERVIEW OF THE 80C186 FAMILY MODUL
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OVERVIEW OF THE 80C186 FAMILY MODUL
Page 57:
Bus Interface Unit 3
Page 60 and 61:
BUS INTERFACE UNIT '--lm I T. I~ I
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BUS INTERFACE UNIT 3.2 PHYSICAL ADD
Page 64 and 65:
BUS INTERFACE UNIT Non-pipelinedEA
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BUS INTERFACE UNIT Any 80C 188 Core
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BUS INTERFACE UNIT LATCH ALE ~ READ
Page 70 and 71:
BUS INTERFACE UNIT 3.4.3.1 TEST INP
Page 72 and 73:
BUS INTERFACE UNIT CPU·DERIVED SIG
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BUS INTERFACE UNIT CLOCK OUT READY
Page 76 and 77:
BUS INTERFACE UNIT 80C186 MODULAR C
Page 78 and 79:
BUS INTERFACE UNIT 3.7.3 WAIT STATE
Page 80 and 81:
BUS INTERFACE UNIT 1II0V mov out mo
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BUS INTERFACE UNIT 3.8.2 HOLD/HLDA
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BUS INTERFACE UNIT T,OR Tw T, CLOCK
Page 86 and 87:
BUS INTERFACE UNIT A special mechan
Page 89 and 90:
CHAPTER 4 CLOCK GENERATOR The clock
Page 91 and 92:
CLOCK GENERATOR The RC tank circuit
Page 93 and 94:
CLOCK GENERATOR ClKIN 1 1 1 1 Vee 1
Page 95:
CLOCK GENERATOR ClKIN RESIN RESYNC
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CHAPTERS PERIPHERAL CONTROL BLOCK A
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PERIPHERAL CONTROL BLOCK All commun
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inter PERIPHERAL CONTROL BLOCK 5.3
Page 107 and 108:
CHAPTER 6 TIMER / COUNTER UNIT The
Page 109 and 110:
TIMER/COUNTER UNIT TIMER 0 and TIME
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TIMER/COUNTER UNIT TIMER 1 TIMER 2
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inter TIMER/COUNTER UNIT YES NO YES
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TIMER/COUNTER UNIT 6.2 TIMER EVENTS
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TIMER/COUNTER UNIT When the timer i
Page 119 and 120:
TIMER/COUNTER UNIT the write, the E
Page 121 and 122:
TIMER/COUNTER UNIT bump_minute: mov
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TIMER/COUNTER UNIT set_count code x
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CHAPTER 7 CHIP SELECT/READY LOGIC U
Page 129 and 130:
CHIP SELECT/READY LOGIC UNIT The Ch
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CHIP SELECT/READY LOGIC UNIT CHIP S
Page 133 and 134:
CHIP SELECT/READY LOGIC UNIT Case 1
Page 135 and 136:
CHIP SELECT/READY LOGIC UNIT EXAMPL
Page 137 and 138:
CHIP SELECT/READY LOGIC UNIT READY
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inter CHIP SELECT/READY LOGIC UNIT
Page 141 and 142:
CHIP SELECT/READY LOGIC UNIT 7.4 AP
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CHIP SELECT/READY LOGIC UNIT Exampl
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CHIP SELECT/READY LOGIC UNIT The fi
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inter CHIP SELECT/READY LOGIC UNIT
Page 149:
intJ CHIP SELECT/READY LOGIC UNIT m
Page 153:
CHAPTER 8 SERIAL COMMUNICATIONS UNI
Page 156 and 157:
SERIAL COMMUNICATIONS UNIT BAUD RAT
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S&RIAl1.COMMUNICATIONS·UNIT SERIAL
Page 160 and 161:
SERIAL COMMUNICATIONS UNIT 8.1.1.1
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
SERIAL COMMUNICATIONS UNIT Initiall
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SERIAL COMMUNICATIONS UNIT Received
Page 170 and 171:
SERIAL COMMUNICATIONS UNIT REN Bit:
Page 172 and 173:
SERIAL COMMUNICATIONS UNIT The foll
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SERIAL COMMUNICATIONS UNIT CLKOUT T
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SERIAL COMMUNICATIONS UNIT CTS SAMP
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SERIAL COMMUNICATIONS UNIT At the i
Page 180 and 181:
SERIAL COMMUNICATIONS UNIT Example
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Page 184 and 185:
Page 187 and 188:
CHAPTER 9 INTERRUPTS 80C186EB famil
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intJ INTERRUPTS interrupted by high
Page 191 and 192:
INTERRUPTS Interrupt on Overflow·
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INTERRUPTS 9.3.1 INTERRUPT LATENCY
Page 195 and 196:
INTERRUPTS interrupt service routin
Page 197 and 198:
INTERRUPTS 9.4 INTERRUPT CONTROL UN
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INTERRUPTS 9.4.2 INTERRUPT UNIT PRO
Page 201 and 202:
INTERRUPTS INTERRUPT CONTROL REGIST
Page 203 and 204:
INTERRUPTS 9.4.2.4 THE REQUEST REGI
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inter INTERRUPTS 9.4.2.6 THE PRIORI
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INTERRUPTS POLL AND POLL STATUS REG
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INTERRUPTS INTERRUPT STATUS REGISTE
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INTERRUPTS When the integrated Inte
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INTERRUPTS 9.4.4.3 INTERRUPT RESPON
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INTERRUPTS YES PRESENT INTERRUPT RE
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Refresh Control Unit 10
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intJ REFRESH CONTROL UNIT 10.1 REFR
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inter REF.RESH CONTROL UNIT REFRESH
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inl:el® REFRESH CONTROL UNIT REFRE
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REFRESH CONTROL UNIT TI T1 TI T1 T1
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Input/Output Port Unit 11
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INPUT/OUTPUT PORT UNIT F·BUS GCS7
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INPUT/OUTPUT PORT UNIT PORT 1 DIREC
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inter INPUT/OUTPUTPORT UNIT PORT 2
Page 238 and 239:
INPUT/OUTPUT PORT UNIT FROM INTEGRA
Page 240 and 241:
inter INPUT/OUTPUT PORT UNIT READ P
Page 242 and 243:
INPUT/OUTPUT PORT UNIT PORT DIRECTI
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INPUTJOUTPUTPORT UNIT 11.4 PROGRAMM
Page 247 and 248:
CHAPTER 12 POWER MANAGEMENT UNIT Th
Page 249 and 250:
POWER MANAGEMENT UNIT 12.1 FUNCTION
Page 251 and 252:
l .. "11 Ti Ti cO r:: CiJ I CLKOUT
Page 253 and 254:
POWER MANAGEMENT UNIT 12.1.1.3 EXIT
Page 255 and 256:
( ::!! cc c iii ... ~ i:» m ~. d:
Page 257 and 258:
POWER MANAGEMENT UNIT PDTMR PIN r--
Page 259 and 260:
O~: _______________________________
Page 261:
POWER MANAGEMENT UNIT Example 1. ho
Page 265 and 266:
CHAPTER 13 HARDWARE PROVISIONS FOR
Page 267 and 268:
HARDWARE PROVISIONS FOR FLOATING PO
Page 269 and 270:
Page 271 and 272:
Page 273:
ONCE Mode 14
Page 277:
Differences Between the 80C 186 Fam
Page 280 and 281:
APPENDIX A A.4 HOLD/HLDA VS. REQUES
Page 282 and 283:
APPENDIX A INTERRUPTED STRING MOVE
Page 285 and 286:
APPENDIX B SUMMARY OF DIFFERENCES B
Page 287 and 288:
APPENDIX B B.1.2 SEMICONDUCTOR TECH
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APPENDIXB B.4INTERRUPT CONTROLLER T
Page 291:
Differences Between 80C186EB and 80
Page 295:
Synchronization Appendix 0
Page 298 and 299:
APPENDIX 0 Thus, the output of this
Page 301 and 302:
APPENDIXE Appendix E. Instruction S
Page 303 and 304:
APPENDIX E Appendix E. Instruction
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APPENDIXE Appendix E. Instruction S
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Instruction Summary 2 AppendixF
Page 309 and 310:
APPENDIX F 1ST BYTE HEX Appendix F.
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APPENDIXF 1ST BYTE HEX BINARY Appen
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APPENDIXF Appendix F. Machine Instr
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIXG LO HI 0 1 2 3 0 ADD ADD A
Page 325 and 326:
APPENDIXH MODAL PIN STATES The tenn
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APPENDIX H Name Modal State Type De
Page 329:
APPENDIXH Name Modal State Type Des
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inter ALABAMA ~~I ~:llord Dr .. #2
Page 335 and 336:
intel~ DOMESTIC DISTRIBUTORS (Contd
Page 337 and 338:
INTERNATIONAL SALES OFFICES AUSTRAL
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UNITED STATES Intel Corporation 306
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