80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

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OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSOR CORE ARCHITECTURE If arepeatpreftx has been coded, thenregisterCX (the count register) is decremented by one after each repetition of the string instruction. The CX register must be initialized to the number of repetitions desired before the string instruction is executed. If the CX register is 0, the string instruction is not executed and control goes to the following instruction. 2.2.1.5 PROGRAM TRANSFER INSTRUCTIONS The sequence in which instructions are executed in the 80C 186 Modular Core family is determined by the contents of the CS and IPregisters. The CS register contains the base address of the current code segment. The IP register points to the memory locations from which the next instruction is to be fetched. In most operating conditions, the next instruction to be executed will have already been fetched and is waiting in the CPU instruction queue. The program transfer instructions operate on the instruction pointer and on the CS register; changing the content of these causes normal sequential operation to be altered. When a program transfer occurs, the queue no longer contains the correct instruction. When the BIUobtains the next instruction from memory using the new IP andCS values, it passes the instruction directly to the EU and begins reftlling the queue from the new location. Four groups of program transfers are available with the 80C186 Core family processors. See Table 2.9. These are unconditional transfers, conditional transfers, iteration control instructions, and interrupt crelated instructions. The unconditional transfer instructions may transfer control to a target instruction within the current code segment (intrasegment transfer) or to a different code segment (intersegment transfer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment transfer FAR. The transfer is made unconditionally any time the instruction is executed. The conditional transfer instructions are jumps that mayor may not transfer control depending on the state of the CPU flags at the time the instruction is executed. These 18 instructions (see Table 2.10) each test a different combination of flags for a condition. If the condition is logically TRUE then control is transferred to the target specified in the instruction. If the condition is FALSE then control passes to the instruction that follows the conditional jump. <strong>Al</strong>l conditional jumps are SHORT, that is, the target must be in the current code segment and within -128 to + 127 bytes of the ftrst byte of the next instruction. For example, JMP OOH causes a jump to the fIrst byte of the next instruction. Since jumps are made by adding the relative displacement of the target to the instruction pointer, all conditional jutnps are self-relative and are appropriate for position-independent routines. 2-20
OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSOR CORE ARCHITECTURE MNEMONIC Table 2.10. Interpretation of Conditional Transfers CONDITION TESTED "JUMP IF .•• " J<strong>Al</strong>JNBE JAElJNB JB/JNAE JBElJNA JC JE/JZ JG/JNLE JGElJNL JUJNGE JLE/JNG JNC JNE/JNZ JNO JNP/JPO JNS JO JP/JPE JS (CFor ZF)=O CF=O CF=1 (CForZF)=1 CF=1 ZF=1 ((SF xor OF) or ZF) = 0 (SF xor OF)=O (SF xor OF)=1 ((SF xor OF) or ZF)=1 CF=O ZF=O OF=O PF=O SF=O OF=1 PF=1 SF=1 above/not below nor equal above or equal/not below below/not above nor equal below or equal/not above carry equal/zero greater/not less nor equal greater or equal/not less less/not greater nor equal less or equal/not greater not carry not equal/not zero not overflow not parity/parity odd not sign overflow parity/parity equal sign Note: "above" and "below" refer to the relationship of two unsigned values; "greater" and "less" refer to the relationship of two signed values. The iteration control instructions can be used to regulate the repetition of software loops. These instructions use the CX register as a counter. Like the conditiorial transfers, the iteration control instructions are self-relative and may only transfer to targets that are within -128 to +127 bytes of themselves, i.e., they are SHORT transfers. The interrupt instructions allow interrupt service routines to be activated by programs as well as by external hardware devices. The effect of software interrupts is similar to hardware-initiated interrupts. However, the processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in software or with an NMI (Non-Maskable Interrupt). 2.2.1.6 PROCESSOR CONTROL INSTRUCTIONS The processor control instructions (see Table 2.11) allow programs to control various CPU functions. One group of instructions updates flags, and another group is used primarily for synchronizing the microprocessor to external events. A final instruction causes the CPU to do nothing. Except for the flag operations, none of the processor control instructions affects the flags. 2-21
Page 2 and 3: LITERATURE To order Intel Literatur
Page 4 and 5: INTERNATIONAL LITERATURE ORDER FORM
Page 6 and 7: inter Intel Corporation makes no wa
Page 9 and 10: Table of Contents CHAPTER 1 INTRODU
Page 11 and 12: Table of Contents (continued) 8.1.2
Page 13: Table of Contents (continued) APPEN
Page 17 and 18: CHAPTER 1 INTRODUCTION The 80C 186E
Page 19 and 20: INTRODUCTION Some customers may not
Page 21: INTRODUCTION 80C186EB: This refers
Page 25 and 26: CHAPTER 2 OVERVIEW OF THE 80C186 FA
Page 27 and 28: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 33 and 34: inter OVERVIEW OF THE 80C186 FAMILY
Page 43: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 57: Bus Interface Unit 3
Page 60 and 61: BUS INTERFACE UNIT '--lm I T. I~ I
Page 62 and 63: BUS INTERFACE UNIT 3.2 PHYSICAL ADD
Page 64 and 65: BUS INTERFACE UNIT Non-pipelinedEA
Page 66 and 67: BUS INTERFACE UNIT Any 80C 188 Core
Page 68 and 69: BUS INTERFACE UNIT LATCH ALE ~ READ
Page 70 and 71: BUS INTERFACE UNIT 3.4.3.1 TEST INP
Page 72 and 73: BUS INTERFACE UNIT CPU·DERIVED SIG
Page 74 and 75: BUS INTERFACE UNIT CLOCK OUT READY
Page 76 and 77: BUS INTERFACE UNIT 80C186 MODULAR C
Page 78 and 79: BUS INTERFACE UNIT 3.7.3 WAIT STATE
Page 80 and 81: BUS INTERFACE UNIT 1II0V mov out mo
Page 82 and 83: BUS INTERFACE UNIT 3.8.2 HOLD/HLDA
Page 84 and 85: BUS INTERFACE UNIT T,OR Tw T, CLOCK
Page 86 and 87: BUS INTERFACE UNIT A special mechan
Page 89 and 90: CHAPTER 4 CLOCK GENERATOR The clock
Page 91 and 92: CLOCK GENERATOR The RC tank circuit
Page 93 and 94: CLOCK GENERATOR ClKIN 1 1 1 1 Vee 1
Page 95:
CLOCK GENERATOR ClKIN RESIN RESYNC
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CHAPTERS PERIPHERAL CONTROL BLOCK A
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PERIPHERAL CONTROL BLOCK All commun
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inter PERIPHERAL CONTROL BLOCK 5.3
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CHAPTER 6 TIMER / COUNTER UNIT The
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TIMER/COUNTER UNIT TIMER 0 and TIME
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TIMER/COUNTER UNIT TIMER 1 TIMER 2
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inter TIMER/COUNTER UNIT YES NO YES
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TIMER/COUNTER UNIT 6.2 TIMER EVENTS
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TIMER/COUNTER UNIT When the timer i
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TIMER/COUNTER UNIT the write, the E
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TIMER/COUNTER UNIT bump_minute: mov
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TIMER/COUNTER UNIT set_count code x
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CHAPTER 7 CHIP SELECT/READY LOGIC U
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CHIP SELECT/READY LOGIC UNIT The Ch
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CHIP SELECT/READY LOGIC UNIT CHIP S
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CHIP SELECT/READY LOGIC UNIT Case 1
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CHIP SELECT/READY LOGIC UNIT EXAMPL
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CHIP SELECT/READY LOGIC UNIT READY
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inter CHIP SELECT/READY LOGIC UNIT
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CHIP SELECT/READY LOGIC UNIT 7.4 AP
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CHIP SELECT/READY LOGIC UNIT Exampl
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CHIP SELECT/READY LOGIC UNIT The fi
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inter CHIP SELECT/READY LOGIC UNIT
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intJ CHIP SELECT/READY LOGIC UNIT m
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CHAPTER 8 SERIAL COMMUNICATIONS UNI
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SERIAL COMMUNICATIONS UNIT BAUD RAT
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S&RIAl1.COMMUNICATIONS·UNIT SERIAL
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SERIAL COMMUNICATIONS UNIT 8.1.1.1
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Page 164 and 165:
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SERIAL COMMUNICATIONS UNIT Initiall
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SERIAL COMMUNICATIONS UNIT Received
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SERIAL COMMUNICATIONS UNIT REN Bit:
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SERIAL COMMUNICATIONS UNIT The foll
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SERIAL COMMUNICATIONS UNIT CLKOUT T
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SERIAL COMMUNICATIONS UNIT CTS SAMP
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SERIAL COMMUNICATIONS UNIT At the i
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SERIAL COMMUNICATIONS UNIT Example
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CHAPTER 9 INTERRUPTS 80C186EB famil
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intJ INTERRUPTS interrupted by high
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INTERRUPTS Interrupt on Overflow·
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INTERRUPTS 9.3.1 INTERRUPT LATENCY
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INTERRUPTS interrupt service routin
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INTERRUPTS 9.4 INTERRUPT CONTROL UN
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INTERRUPTS 9.4.2 INTERRUPT UNIT PRO
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INTERRUPTS INTERRUPT CONTROL REGIST
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INTERRUPTS 9.4.2.4 THE REQUEST REGI
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inter INTERRUPTS 9.4.2.6 THE PRIORI
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INTERRUPTS POLL AND POLL STATUS REG
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INTERRUPTS INTERRUPT STATUS REGISTE
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INTERRUPTS When the integrated Inte
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INTERRUPTS 9.4.4.3 INTERRUPT RESPON
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INTERRUPTS YES PRESENT INTERRUPT RE
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Refresh Control Unit 10
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intJ REFRESH CONTROL UNIT 10.1 REFR
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inter REF.RESH CONTROL UNIT REFRESH
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inl:el® REFRESH CONTROL UNIT REFRE
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REFRESH CONTROL UNIT TI T1 TI T1 T1
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Input/Output Port Unit 11
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INPUT/OUTPUT PORT UNIT F·BUS GCS7
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INPUT/OUTPUT PORT UNIT PORT 1 DIREC
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inter INPUT/OUTPUTPORT UNIT PORT 2
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INPUT/OUTPUT PORT UNIT FROM INTEGRA
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inter INPUT/OUTPUT PORT UNIT READ P
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INPUT/OUTPUT PORT UNIT PORT DIRECTI
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INPUTJOUTPUTPORT UNIT 11.4 PROGRAMM
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CHAPTER 12 POWER MANAGEMENT UNIT Th
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POWER MANAGEMENT UNIT 12.1 FUNCTION
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l .. "11 Ti Ti cO r:: CiJ I CLKOUT
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POWER MANAGEMENT UNIT 12.1.1.3 EXIT
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( ::!! cc c iii ... ~ i:» m ~. d:
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POWER MANAGEMENT UNIT PDTMR PIN r--
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O~: _______________________________
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POWER MANAGEMENT UNIT Example 1. ho
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CHAPTER 13 HARDWARE PROVISIONS FOR
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HARDWARE PROVISIONS FOR FLOATING PO
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Page 271 and 272:
Page 273:
ONCE Mode 14
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Differences Between the 80C 186 Fam
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APPENDIX A A.4 HOLD/HLDA VS. REQUES
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APPENDIX A INTERRUPTED STRING MOVE
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APPENDIX B SUMMARY OF DIFFERENCES B
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APPENDIX B B.1.2 SEMICONDUCTOR TECH
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APPENDIXB B.4INTERRUPT CONTROLLER T
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Differences Between 80C186EB and 80
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Synchronization Appendix 0
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APPENDIX 0 Thus, the output of this
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APPENDIXE Appendix E. Instruction S
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APPENDIX E Appendix E. Instruction
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APPENDIXE Appendix E. Instruction S
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Instruction Summary 2 AppendixF
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APPENDIX F 1ST BYTE HEX Appendix F.
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APPENDIXF 1ST BYTE HEX BINARY Appen
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APPENDIXF Appendix F. Machine Instr
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIXG LO HI 0 1 2 3 0 ADD ADD A
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APPENDIXH MODAL PIN STATES The tenn
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APPENDIX H Name Modal State Type De
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APPENDIXH Name Modal State Type Des
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inter ALABAMA ~~I ~:llord Dr .. #2
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intel~ DOMESTIC DISTRIBUTORS (Contd
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INTERNATIONAL SALES OFFICES AUSTRAL
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UNITED STATES Intel Corporation 306
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