80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

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OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSORCOREARCHITECTORE SINGLE INDEX DOUBLE INDEX ENCODED IN THE INSTRUCTION EXPLICIT { IN THE INSTRUCTION ASSUMED UNLESS OVERRIDDEN BY PREFIX BIU 270288-001-14 Figure 2.12. Memory Address Computation The displacement element is an 8-bit or 16-bit number that is contained in the instruction. The displacement generally is derived from the position of the operand name (a variable or label) in the program. The programmer can also modify this value or explicitly specify the displacement. A programmer may specify that either the BX or BP register is to serve as a base register.whose content is to be used in the EA computation. Similarly, either the SI or DI register may be specified as the index register. The displacement value is a constant. The contents of the base and index registers may change during execution. This allows one instruction to access different memory locations as determined by the current values in the base or base and index registers. Effective address calculations with the BP register are made using the SS register, by default, although either the DS or the ES register may be specified instead. 2-24
OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSOR CORE ARCHITECTURE Direct addressing is the simplest memory addressing mode (see Figure 2.13). No registers are involved and the EA is taken directly from the displacement of the instruction. The programmer typically uses direct addressing to access scaler variables. r-----,------.------.-----..., 1,--_oP_C_O_D_E ---I1_M_O_D_R_/M_.L-I __ D_18_P_LA-+C.E _M~~ __ J I EA I 270288-001-15 Figure 2.13. Direct Addressing With register indirect addressing, the effective address of a memory operand may be taken directly from one of the base or index registers (see Figure 2.14). One instruction can operate on many different memory locations ifthe value in the base or index register is updated appropriately. Any 16- bit general register may be used for register indirect addressing with the JMP or CALL instructions. BX OR BP OR--+-_'" 81 OR DI 270288-001-16 Figure 2.14. Register Indirect Addressing 2-25
Page 2 and 3: LITERATURE To order Intel Literatur
Page 4 and 5: INTERNATIONAL LITERATURE ORDER FORM
Page 6 and 7: inter Intel Corporation makes no wa
Page 9 and 10: Table of Contents CHAPTER 1 INTRODU
Page 11 and 12: Table of Contents (continued) 8.1.2
Page 13: Table of Contents (continued) APPEN
Page 17 and 18: CHAPTER 1 INTRODUCTION The 80C 186E
Page 19 and 20: INTRODUCTION Some customers may not
Page 21: INTRODUCTION 80C186EB: This refers
Page 25 and 26: CHAPTER 2 OVERVIEW OF THE 80C186 FA
Page 27 and 28: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 33 and 34: inter OVERVIEW OF THE 80C186 FAMILY
Page 47: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 57: Bus Interface Unit 3
Page 60 and 61: BUS INTERFACE UNIT '--lm I T. I~ I
Page 62 and 63: BUS INTERFACE UNIT 3.2 PHYSICAL ADD
Page 64 and 65: BUS INTERFACE UNIT Non-pipelinedEA
Page 66 and 67: BUS INTERFACE UNIT Any 80C 188 Core
Page 68 and 69: BUS INTERFACE UNIT LATCH ALE ~ READ
Page 70 and 71: BUS INTERFACE UNIT 3.4.3.1 TEST INP
Page 72 and 73: BUS INTERFACE UNIT CPU·DERIVED SIG
Page 74 and 75: BUS INTERFACE UNIT CLOCK OUT READY
Page 76 and 77: BUS INTERFACE UNIT 80C186 MODULAR C
Page 78 and 79: BUS INTERFACE UNIT 3.7.3 WAIT STATE
Page 80 and 81: BUS INTERFACE UNIT 1II0V mov out mo
Page 82 and 83: BUS INTERFACE UNIT 3.8.2 HOLD/HLDA
Page 84 and 85: BUS INTERFACE UNIT T,OR Tw T, CLOCK
Page 86 and 87: BUS INTERFACE UNIT A special mechan
Page 89 and 90: CHAPTER 4 CLOCK GENERATOR The clock
Page 91 and 92: CLOCK GENERATOR The RC tank circuit
Page 93 and 94: CLOCK GENERATOR ClKIN 1 1 1 1 Vee 1
Page 95: CLOCK GENERATOR ClKIN RESIN RESYNC
Page 99 and 100:
CHAPTERS PERIPHERAL CONTROL BLOCK A
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PERIPHERAL CONTROL BLOCK All commun
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inter PERIPHERAL CONTROL BLOCK 5.3
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CHAPTER 6 TIMER / COUNTER UNIT The
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TIMER/COUNTER UNIT TIMER 0 and TIME
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TIMER/COUNTER UNIT TIMER 1 TIMER 2
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inter TIMER/COUNTER UNIT YES NO YES
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TIMER/COUNTER UNIT 6.2 TIMER EVENTS
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TIMER/COUNTER UNIT When the timer i
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TIMER/COUNTER UNIT the write, the E
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TIMER/COUNTER UNIT bump_minute: mov
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TIMER/COUNTER UNIT set_count code x
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CHAPTER 7 CHIP SELECT/READY LOGIC U
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CHIP SELECT/READY LOGIC UNIT The Ch
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CHIP SELECT/READY LOGIC UNIT CHIP S
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CHIP SELECT/READY LOGIC UNIT Case 1
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CHIP SELECT/READY LOGIC UNIT EXAMPL
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CHIP SELECT/READY LOGIC UNIT READY
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inter CHIP SELECT/READY LOGIC UNIT
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CHIP SELECT/READY LOGIC UNIT 7.4 AP
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CHIP SELECT/READY LOGIC UNIT Exampl
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CHIP SELECT/READY LOGIC UNIT The fi
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inter CHIP SELECT/READY LOGIC UNIT
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intJ CHIP SELECT/READY LOGIC UNIT m
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CHAPTER 8 SERIAL COMMUNICATIONS UNI
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SERIAL COMMUNICATIONS UNIT BAUD RAT
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S&RIAl1.COMMUNICATIONS·UNIT SERIAL
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SERIAL COMMUNICATIONS UNIT 8.1.1.1
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Page 164 and 165:
Page 166 and 167:
SERIAL COMMUNICATIONS UNIT Initiall
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SERIAL COMMUNICATIONS UNIT Received
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SERIAL COMMUNICATIONS UNIT REN Bit:
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SERIAL COMMUNICATIONS UNIT The foll
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SERIAL COMMUNICATIONS UNIT CLKOUT T
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SERIAL COMMUNICATIONS UNIT CTS SAMP
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SERIAL COMMUNICATIONS UNIT At the i
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SERIAL COMMUNICATIONS UNIT Example
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Page 184 and 185:
Page 187 and 188:
CHAPTER 9 INTERRUPTS 80C186EB famil
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intJ INTERRUPTS interrupted by high
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INTERRUPTS Interrupt on Overflow·
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INTERRUPTS 9.3.1 INTERRUPT LATENCY
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INTERRUPTS interrupt service routin
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INTERRUPTS 9.4 INTERRUPT CONTROL UN
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INTERRUPTS 9.4.2 INTERRUPT UNIT PRO
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INTERRUPTS INTERRUPT CONTROL REGIST
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INTERRUPTS 9.4.2.4 THE REQUEST REGI
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inter INTERRUPTS 9.4.2.6 THE PRIORI
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INTERRUPTS POLL AND POLL STATUS REG
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INTERRUPTS INTERRUPT STATUS REGISTE
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INTERRUPTS When the integrated Inte
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INTERRUPTS 9.4.4.3 INTERRUPT RESPON
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INTERRUPTS YES PRESENT INTERRUPT RE
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Refresh Control Unit 10
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intJ REFRESH CONTROL UNIT 10.1 REFR
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inter REF.RESH CONTROL UNIT REFRESH
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inl:el® REFRESH CONTROL UNIT REFRE
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REFRESH CONTROL UNIT TI T1 TI T1 T1
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Input/Output Port Unit 11
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INPUT/OUTPUT PORT UNIT F·BUS GCS7
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INPUT/OUTPUT PORT UNIT PORT 1 DIREC
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inter INPUT/OUTPUTPORT UNIT PORT 2
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INPUT/OUTPUT PORT UNIT FROM INTEGRA
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inter INPUT/OUTPUT PORT UNIT READ P
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INPUT/OUTPUT PORT UNIT PORT DIRECTI
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INPUTJOUTPUTPORT UNIT 11.4 PROGRAMM
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CHAPTER 12 POWER MANAGEMENT UNIT Th
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POWER MANAGEMENT UNIT 12.1 FUNCTION
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l .. "11 Ti Ti cO r:: CiJ I CLKOUT
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POWER MANAGEMENT UNIT 12.1.1.3 EXIT
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( ::!! cc c iii ... ~ i:» m ~. d:
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POWER MANAGEMENT UNIT PDTMR PIN r--
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O~: _______________________________
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POWER MANAGEMENT UNIT Example 1. ho
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CHAPTER 13 HARDWARE PROVISIONS FOR
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HARDWARE PROVISIONS FOR FLOATING PO
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Page 271 and 272:
Page 273:
ONCE Mode 14
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Differences Between the 80C 186 Fam
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APPENDIX A A.4 HOLD/HLDA VS. REQUES
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APPENDIX A INTERRUPTED STRING MOVE
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APPENDIX B SUMMARY OF DIFFERENCES B
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APPENDIX B B.1.2 SEMICONDUCTOR TECH
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APPENDIXB B.4INTERRUPT CONTROLLER T
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Differences Between 80C186EB and 80
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Synchronization Appendix 0
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APPENDIX 0 Thus, the output of this
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APPENDIXE Appendix E. Instruction S
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APPENDIX E Appendix E. Instruction
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APPENDIXE Appendix E. Instruction S
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Instruction Summary 2 AppendixF
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APPENDIX F 1ST BYTE HEX Appendix F.
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APPENDIXF 1ST BYTE HEX BINARY Appen
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APPENDIXF Appendix F. Machine Instr
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIXG LO HI 0 1 2 3 0 ADD ADD A
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APPENDIXH MODAL PIN STATES The tenn
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APPENDIX H Name Modal State Type De
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APPENDIXH Name Modal State Type Des
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inter ALABAMA ~~I ~:llord Dr .. #2
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intel~ DOMESTIC DISTRIBUTORS (Contd
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INTERNATIONAL SALES OFFICES AUSTRAL
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UNITED STATES Intel Corporation 306
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