80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

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OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSOR CORE ARCHITECTURE hardware products. On the 80C186 Core, these addresses are used as I/O ports for the 80C187 numerics processor extension. The peripheral control block (see Section 5.0) may reside in memory or I/O space. <strong>Al</strong>l unused locations in the peripheral control block are also reserved. 2.2 SOFTWARE OVERVIEW An80C 186 Modular Core family members execute exactly the same instructions. This instruction set includes all the 8086/8088 instructions plus several useful additions and enhancements. The following sections provide a description of the instructions by category and a detailed discussion of the various operand addressing modes. Software for 80C186 Core family systems does not need to be written in assembly language. The processor provides direct hardware support for programs written in the many high-level languages available. Most high-level languages store variables in memory; the symmetrical instruction set supports direct operation on memory operands, including operands on the stack. The hardware addressing modes provide efficient, straightforward implementations of based variables, arrays, arrays of structures and other high-level language data constructs. A powerful set of memory-tomemory string operations is available for efficient character data manipulation. Finally, routines with critical performance requirements that cannot be met with high-level languages may be written in assembly language and linked with high-level code. 2.2.1 INSTRUCTION SET Instructions in the 80C 186 Modular Core family treat different types of operands uniformly. Nearly every instruction can operate on either byte or word data. Register, memory and immediate operands may be specified interchangeably in most instructions. The exception to this is that immediate values serve as source and not destination operands. In particular, memory variables may be added to, subtracted from, shifted, compared, and so on, in place, without moving them in and out of registers. This saves instructions, registers, and execution time in assembly language programs. In high-level languages, where most variables are memory-based, compilers can produce faster and shorter object programs. The 80C186 Core family instruction set can be viewed as existing on two levels. One is the assembly level and the other is the machine level. To the assembly language programmer, the 80C186 Core family appears to have a repertoire of about 100 instructions. One MOV (data move) instruction, for example, transfers a byte of a word from a register of a memory location or an immediate value to either a register or a memory location. The 80C 186 Modular Core family CPU s, however, recognize 28 different machine versions of the MOV instruction. The two levels of instruction set address two different requirements: efficiency and simplicity. The approximately 300 forms of machine-level instructions make very efficient use of storage. For 2-14
OVERVIEW OF THE 80C186 FAMILY MODULAR MICROPROCESSOR CORE ARCHITECTURE example, the machine instruction that increments a memory operand is three or four bytes long because the address of the operand must be encoded in the instruction. To increment a register, however, does not require as much information, so the instruction can be shorter. The 80C 186 Core family has eight different machine-level instructions that increment a different 16-bit register. Each of these instructions is only one byte long. The assembly level instructions simplify the programmer's view of the instruction set. The programmer writes one form of an INC (increment) instruction and the assembler examines the operand to determine which machine level instruction to generate. The following paragraphs provide a functional description of the assembly-level instructions. 2.2.1.1 DATA TRANSFER INSTRUCTIONS The instruction set contains 14 data transfer instructions. These instructions move single bytes and words betwc.!n memory and registers, and also move single bytes and words between the AL or AX registers and I/O ports. Table 2.3 lists the four types of data transfer instructions and their functions. 2-15
Page 2 and 3: LITERATURE To order Intel Literatur
Page 4 and 5: INTERNATIONAL LITERATURE ORDER FORM
Page 6 and 7: inter Intel Corporation makes no wa
Page 9 and 10: Table of Contents CHAPTER 1 INTRODU
Page 11 and 12: Table of Contents (continued) 8.1.2
Page 13: Table of Contents (continued) APPEN
Page 17 and 18: CHAPTER 1 INTRODUCTION The 80C 186E
Page 19 and 20: INTRODUCTION Some customers may not
Page 21: INTRODUCTION 80C186EB: This refers
Page 25 and 26: CHAPTER 2 OVERVIEW OF THE 80C186 FA
Page 27 and 28: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 33 and 34: inter OVERVIEW OF THE 80C186 FAMILY
Page 37: OVERVIEW OF THE 80C186 FAMILY MODUL
Page 57: Bus Interface Unit 3
Page 60 and 61: BUS INTERFACE UNIT '--lm I T. I~ I
Page 62 and 63: BUS INTERFACE UNIT 3.2 PHYSICAL ADD
Page 64 and 65: BUS INTERFACE UNIT Non-pipelinedEA
Page 66 and 67: BUS INTERFACE UNIT Any 80C 188 Core
Page 68 and 69: BUS INTERFACE UNIT LATCH ALE ~ READ
Page 70 and 71: BUS INTERFACE UNIT 3.4.3.1 TEST INP
Page 72 and 73: BUS INTERFACE UNIT CPU·DERIVED SIG
Page 74 and 75: BUS INTERFACE UNIT CLOCK OUT READY
Page 76 and 77: BUS INTERFACE UNIT 80C186 MODULAR C
Page 78 and 79: BUS INTERFACE UNIT 3.7.3 WAIT STATE
Page 80 and 81: BUS INTERFACE UNIT 1II0V mov out mo
Page 82 and 83: BUS INTERFACE UNIT 3.8.2 HOLD/HLDA
Page 84 and 85: BUS INTERFACE UNIT T,OR Tw T, CLOCK
Page 86 and 87: BUS INTERFACE UNIT A special mechan
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CHAPTER 4 CLOCK GENERATOR The clock
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CLOCK GENERATOR The RC tank circuit
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CLOCK GENERATOR ClKIN 1 1 1 1 Vee 1
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CLOCK GENERATOR ClKIN RESIN RESYNC
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CHAPTERS PERIPHERAL CONTROL BLOCK A
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PERIPHERAL CONTROL BLOCK All commun
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inter PERIPHERAL CONTROL BLOCK 5.3
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CHAPTER 6 TIMER / COUNTER UNIT The
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TIMER/COUNTER UNIT TIMER 0 and TIME
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TIMER/COUNTER UNIT TIMER 1 TIMER 2
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inter TIMER/COUNTER UNIT YES NO YES
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TIMER/COUNTER UNIT 6.2 TIMER EVENTS
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TIMER/COUNTER UNIT When the timer i
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TIMER/COUNTER UNIT the write, the E
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TIMER/COUNTER UNIT bump_minute: mov
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TIMER/COUNTER UNIT set_count code x
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CHAPTER 7 CHIP SELECT/READY LOGIC U
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CHIP SELECT/READY LOGIC UNIT The Ch
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CHIP SELECT/READY LOGIC UNIT CHIP S
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CHIP SELECT/READY LOGIC UNIT Case 1
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CHIP SELECT/READY LOGIC UNIT EXAMPL
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CHIP SELECT/READY LOGIC UNIT READY
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inter CHIP SELECT/READY LOGIC UNIT
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CHIP SELECT/READY LOGIC UNIT 7.4 AP
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CHIP SELECT/READY LOGIC UNIT Exampl
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CHIP SELECT/READY LOGIC UNIT The fi
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inter CHIP SELECT/READY LOGIC UNIT
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intJ CHIP SELECT/READY LOGIC UNIT m
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CHAPTER 8 SERIAL COMMUNICATIONS UNI
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SERIAL COMMUNICATIONS UNIT BAUD RAT
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S&RIAl1.COMMUNICATIONS·UNIT SERIAL
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SERIAL COMMUNICATIONS UNIT 8.1.1.1
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SERIAL COMMUNICATIONS UNIT Initiall
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SERIAL COMMUNICATIONS UNIT Received
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SERIAL COMMUNICATIONS UNIT REN Bit:
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SERIAL COMMUNICATIONS UNIT The foll
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SERIAL COMMUNICATIONS UNIT CLKOUT T
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SERIAL COMMUNICATIONS UNIT CTS SAMP
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SERIAL COMMUNICATIONS UNIT At the i
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SERIAL COMMUNICATIONS UNIT Example
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CHAPTER 9 INTERRUPTS 80C186EB famil
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intJ INTERRUPTS interrupted by high
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INTERRUPTS Interrupt on Overflow·
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INTERRUPTS 9.3.1 INTERRUPT LATENCY
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INTERRUPTS interrupt service routin
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INTERRUPTS 9.4 INTERRUPT CONTROL UN
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INTERRUPTS 9.4.2 INTERRUPT UNIT PRO
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INTERRUPTS INTERRUPT CONTROL REGIST
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INTERRUPTS 9.4.2.4 THE REQUEST REGI
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inter INTERRUPTS 9.4.2.6 THE PRIORI
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INTERRUPTS POLL AND POLL STATUS REG
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INTERRUPTS INTERRUPT STATUS REGISTE
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INTERRUPTS When the integrated Inte
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INTERRUPTS 9.4.4.3 INTERRUPT RESPON
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INTERRUPTS YES PRESENT INTERRUPT RE
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Refresh Control Unit 10
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intJ REFRESH CONTROL UNIT 10.1 REFR
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inter REF.RESH CONTROL UNIT REFRESH
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inl:el® REFRESH CONTROL UNIT REFRE
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REFRESH CONTROL UNIT TI T1 TI T1 T1
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Input/Output Port Unit 11
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INPUT/OUTPUT PORT UNIT F·BUS GCS7
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INPUT/OUTPUT PORT UNIT PORT 1 DIREC
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inter INPUT/OUTPUTPORT UNIT PORT 2
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INPUT/OUTPUT PORT UNIT FROM INTEGRA
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inter INPUT/OUTPUT PORT UNIT READ P
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INPUT/OUTPUT PORT UNIT PORT DIRECTI
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INPUTJOUTPUTPORT UNIT 11.4 PROGRAMM
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CHAPTER 12 POWER MANAGEMENT UNIT Th
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POWER MANAGEMENT UNIT 12.1 FUNCTION
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l .. "11 Ti Ti cO r:: CiJ I CLKOUT
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POWER MANAGEMENT UNIT 12.1.1.3 EXIT
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( ::!! cc c iii ... ~ i:» m ~. d:
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POWER MANAGEMENT UNIT PDTMR PIN r--
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O~: _______________________________
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POWER MANAGEMENT UNIT Example 1. ho
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CHAPTER 13 HARDWARE PROVISIONS FOR
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HARDWARE PROVISIONS FOR FLOATING PO
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ONCE Mode 14
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Differences Between the 80C 186 Fam
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APPENDIX A A.4 HOLD/HLDA VS. REQUES
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APPENDIX A INTERRUPTED STRING MOVE
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APPENDIX B SUMMARY OF DIFFERENCES B
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APPENDIX B B.1.2 SEMICONDUCTOR TECH
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APPENDIXB B.4INTERRUPT CONTROLLER T
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Differences Between 80C186EB and 80
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Synchronization Appendix 0
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APPENDIX 0 Thus, the output of this
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APPENDIXE Appendix E. Instruction S
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APPENDIX E Appendix E. Instruction
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APPENDIXE Appendix E. Instruction S
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Instruction Summary 2 AppendixF
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APPENDIX F 1ST BYTE HEX Appendix F.
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APPENDIXF 1ST BYTE HEX BINARY Appen
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APPENDIXF Appendix F. Machine Instr
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIXG LO HI 0 1 2 3 0 ADD ADD A
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APPENDIXH MODAL PIN STATES The tenn
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APPENDIX H Name Modal State Type De
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APPENDIXH Name Modal State Type Des
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inter ALABAMA ~~I ~:llord Dr .. #2
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intel~ DOMESTIC DISTRIBUTORS (Contd
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INTERNATIONAL SALES OFFICES AUSTRAL
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UNITED STATES Intel Corporation 306
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