80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

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INTERRUPTS $mod1llb name This routine configures the interrupt controller to provide two cascaded interrupt inputs (through an external 1l259A internal controller on pins INTO and INT2/INTAO) and two direct interrupt inputs (on pins INT1 and INT3). The default priority levels are used. Because of this, the priority level programmed into the control register is set to 111, the level all interrupts assu,me at reset. , IOCON equ OFF11lH IMASK equ OFFOIlH code set int code segment assume CS: code proc near push DX push AX mov mov out mov mov out pop pop ret endp ends end AX,010D111B DX,IOCON DX,AX AX,D10D1101B DX,IMASK DX,AX AX DX ; public 'code' ; Cascade Mode ; interrupt unmasked ; now unmask the other external ; interrupts Figure 9.18. Example <strong>80C186EB</strong> Family Interrupt Initialization for Master Mode 9.5 INTERRUPT CONTROLLER FLOW CHARTS Figure 9.19 shows an interrupt request generation flow chart and Figure 9.20 shows an interrupt acknowledge sequence flow chart. Each interrupt source processed by an <strong>80C186EB</strong> family integrated Interrupt Controller follows each flow chart independently. 9-28
INTERRUPTS YES PRESENT INTERRUPT REQUEST TO EXTERNAL CONTROLLER 270288-001-111 Figure 9.19. Interrupt Request Sequencing 9-29
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LITERATURE To order Intel Literatur
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INTERNATIONAL LITERATURE ORDER FORM
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inter Intel Corporation makes no wa
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Table of Contents CHAPTER 1 INTRODU
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Table of Contents (continued) 8.1.2
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Table of Contents (continued) APPEN
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CHAPTER 1 INTRODUCTION The 80C 186E
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INTRODUCTION Some customers may not
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INTRODUCTION 80C186EB: This refers
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CHAPTER 2 OVERVIEW OF THE 80C186 FA
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OVERVIEW OF THE 80C186 FAMILY MODUL
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inter OVERVIEW OF THE 80C186 FAMILY
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Bus Interface Unit 3
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BUS INTERFACE UNIT '--lm I T. I~ I
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BUS INTERFACE UNIT 3.2 PHYSICAL ADD
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BUS INTERFACE UNIT Non-pipelinedEA
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BUS INTERFACE UNIT Any 80C 188 Core
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BUS INTERFACE UNIT LATCH ALE ~ READ
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BUS INTERFACE UNIT 3.4.3.1 TEST INP
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BUS INTERFACE UNIT CPU·DERIVED SIG
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BUS INTERFACE UNIT CLOCK OUT READY
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BUS INTERFACE UNIT 80C186 MODULAR C
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BUS INTERFACE UNIT 3.7.3 WAIT STATE
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BUS INTERFACE UNIT 1II0V mov out mo
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BUS INTERFACE UNIT 3.8.2 HOLD/HLDA
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BUS INTERFACE UNIT T,OR Tw T, CLOCK
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BUS INTERFACE UNIT A special mechan
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CHAPTER 4 CLOCK GENERATOR The clock
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CLOCK GENERATOR The RC tank circuit
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CLOCK GENERATOR ClKIN 1 1 1 1 Vee 1
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CLOCK GENERATOR ClKIN RESIN RESYNC
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CHAPTERS PERIPHERAL CONTROL BLOCK A
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PERIPHERAL CONTROL BLOCK All commun
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inter PERIPHERAL CONTROL BLOCK 5.3
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CHAPTER 6 TIMER / COUNTER UNIT The
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TIMER/COUNTER UNIT TIMER 0 and TIME
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TIMER/COUNTER UNIT TIMER 1 TIMER 2
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inter TIMER/COUNTER UNIT YES NO YES
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TIMER/COUNTER UNIT 6.2 TIMER EVENTS
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TIMER/COUNTER UNIT When the timer i
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TIMER/COUNTER UNIT the write, the E
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TIMER/COUNTER UNIT bump_minute: mov
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TIMER/COUNTER UNIT set_count code x
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CHAPTER 7 CHIP SELECT/READY LOGIC U
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CHIP SELECT/READY LOGIC UNIT The Ch
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CHIP SELECT/READY LOGIC UNIT CHIP S
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CHIP SELECT/READY LOGIC UNIT Case 1
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CHIP SELECT/READY LOGIC UNIT EXAMPL
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CHIP SELECT/READY LOGIC UNIT READY
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inter CHIP SELECT/READY LOGIC UNIT
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CHIP SELECT/READY LOGIC UNIT 7.4 AP
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CHIP SELECT/READY LOGIC UNIT Exampl
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CHIP SELECT/READY LOGIC UNIT The fi
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inter CHIP SELECT/READY LOGIC UNIT
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intJ CHIP SELECT/READY LOGIC UNIT m
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CHAPTER 8 SERIAL COMMUNICATIONS UNI
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SERIAL COMMUNICATIONS UNIT BAUD RAT
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S&RIAl1.COMMUNICATIONS·UNIT SERIAL
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SERIAL COMMUNICATIONS UNIT 8.1.1.1
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SERIAL COMMUNICATIONS UNIT 8.1.1.2
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Page 166 and 167: SERIAL COMMUNICATIONS UNIT Initiall
Page 168 and 169: SERIAL COMMUNICATIONS UNIT Received
Page 170 and 171: SERIAL COMMUNICATIONS UNIT REN Bit:
Page 172 and 173: SERIAL COMMUNICATIONS UNIT The foll
Page 174 and 175: SERIAL COMMUNICATIONS UNIT CLKOUT T
Page 176 and 177: SERIAL COMMUNICATIONS UNIT CTS SAMP
Page 178 and 179: SERIAL COMMUNICATIONS UNIT At the i
Page 180 and 181: SERIAL COMMUNICATIONS UNIT Example
Page 187 and 188: CHAPTER 9 INTERRUPTS 80C186EB famil
Page 189 and 190: intJ INTERRUPTS interrupted by high
Page 191 and 192: INTERRUPTS Interrupt on Overflow·
Page 193 and 194: INTERRUPTS 9.3.1 INTERRUPT LATENCY
Page 195 and 196: INTERRUPTS interrupt service routin
Page 197 and 198: INTERRUPTS 9.4 INTERRUPT CONTROL UN
Page 199 and 200: INTERRUPTS 9.4.2 INTERRUPT UNIT PRO
Page 201 and 202: INTERRUPTS INTERRUPT CONTROL REGIST
Page 203 and 204: INTERRUPTS 9.4.2.4 THE REQUEST REGI
Page 205 and 206: inter INTERRUPTS 9.4.2.6 THE PRIORI
Page 207 and 208: INTERRUPTS POLL AND POLL STATUS REG
Page 209 and 210: INTERRUPTS INTERRUPT STATUS REGISTE
Page 211 and 212: INTERRUPTS When the integrated Inte
Page 213: INTERRUPTS 9.4.4.3 INTERRUPT RESPON
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Page 220 and 221: intJ REFRESH CONTROL UNIT 10.1 REFR
Page 222 and 223: inter REF.RESH CONTROL UNIT REFRESH
Page 224 and 225: inl:el® REFRESH CONTROL UNIT REFRE
Page 226 and 227: REFRESH CONTROL UNIT TI T1 TI T1 T1
Page 229: Input/Output Port Unit 11
Page 232 and 233: INPUT/OUTPUT PORT UNIT F·BUS GCS7
Page 234 and 235: INPUT/OUTPUT PORT UNIT PORT 1 DIREC
Page 236 and 237: inter INPUT/OUTPUTPORT UNIT PORT 2
Page 238 and 239: INPUT/OUTPUT PORT UNIT FROM INTEGRA
Page 240 and 241: inter INPUT/OUTPUT PORT UNIT READ P
Page 242 and 243: INPUT/OUTPUT PORT UNIT PORT DIRECTI
Page 244 and 245: INPUTJOUTPUTPORT UNIT 11.4 PROGRAMM
Page 247 and 248: CHAPTER 12 POWER MANAGEMENT UNIT Th
Page 249 and 250: POWER MANAGEMENT UNIT 12.1 FUNCTION
Page 251 and 252: l .. "11 Ti Ti cO r:: CiJ I CLKOUT
Page 253 and 254: POWER MANAGEMENT UNIT 12.1.1.3 EXIT
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Page 257 and 258: POWER MANAGEMENT UNIT PDTMR PIN r--
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Page 261: POWER MANAGEMENT UNIT Example 1. ho
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CHAPTER 13 HARDWARE PROVISIONS FOR
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HARDWARE PROVISIONS FOR FLOATING PO
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ONCE Mode 14
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Differences Between the 80C 186 Fam
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APPENDIX A A.4 HOLD/HLDA VS. REQUES
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APPENDIX A INTERRUPTED STRING MOVE
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APPENDIX B SUMMARY OF DIFFERENCES B
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APPENDIX B B.1.2 SEMICONDUCTOR TECH
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APPENDIXB B.4INTERRUPT CONTROLLER T
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Differences Between 80C186EB and 80
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Synchronization Appendix 0
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APPENDIX 0 Thus, the output of this
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APPENDIXE Appendix E. Instruction S
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APPENDIX E Appendix E. Instruction
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APPENDIXE Appendix E. Instruction S
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Instruction Summary 2 AppendixF
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APPENDIX F 1ST BYTE HEX Appendix F.
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APPENDIXF 1ST BYTE HEX BINARY Appen
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APPENDIXF Appendix F. Machine Instr
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIX F 1ST BYTE HEX BINARY Appe
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APPENDIXG LO HI 0 1 2 3 0 ADD ADD A
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APPENDIXH MODAL PIN STATES The tenn
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APPENDIX H Name Modal State Type De
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APPENDIXH Name Modal State Type Des
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inter ALABAMA ~~I ~:llord Dr .. #2
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intel~ DOMESTIC DISTRIBUTORS (Contd
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INTERNATIONAL SALES OFFICES AUSTRAL
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UNITED STATES Intel Corporation 306
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