80C186EB 80C188EB Users Manual 1990 - Al Kossow's Bitsavers

inter
OVERVIEW OF THE 80C186 FAMILY MODULAR
MICROPROCESSOR CORE ARCHITECTURE
FFFFFH
DATA: DS: B ~--
j
CODE: CS: E 1---,
D
STACK: SS: H \--, I
EXTRA: ES:
h II
I I
I I
IL
I L_
G
: [j
OH
270288-001-09
Figure 2.7. Currently Addressable Segments
The segmented memory structure of the 80Cl86 Modular Core family is a hardware provision to
encourage modular programming. Every program will use segmentation differently. Smaller applications
tend to initialize the segment registers and then simply forget them. Larger applications give
careful consideration to segment definition and use.
2.1.8 LOGICAL ADDRESSES
It is useful to think of every memory location as having two kinds of addresses, physical and logical.
A physical address is a 20-bit value that identifies each unique byte location in the memory space.
Physical addresses range from OH to FFFFFH. All exchanges between the CPU and memory components
use a physical address.
Programs deal with logical, rather than physical addresses. Program code can be developed without
prior knowledge of where the code is to be located in memory; in larger applications, dynamic
management of memory resources is a necessity. A logical address consists of a segment base value
and an offset value. For any given memory location, the segment base value locates the first byte of
the segment and the offset value is the distance, in bytes, of the target location from the beginning of
the segment. Segment base and offset values are unsigned 16-bit quantities. Many different logical
addresses can map to the same physical location. In the example (see Figure 2.8), physical memory
location 2C3H is contained in two different overlapping segments, one beginning at 2BOH and the
other at 2COH.
2-9