DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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Table 5-1. Controls and Indicators Control or Indicator Function Register Display Register Select Switches Status Display RESET Switch STEP Switch RU N Switch SYSTEM RESET Switch REPEA T SwHch In-line display of 16 (or 18) bits in selected operational reg ister. Reg ister bi ts are numbered from rig ht to left wi th the sign bit appearing on the far left side of the display. Lights are grouped in an octal arrangement. Selection of the register to be displayed is accomplished by the register select switches. Five alternate-action switches used to select one of five registers for display. Only one register may be selected at a time. Selection of two or more registers at the same time disables the selection logic and the display becomes blank. Four indicators are provided to indicate the status of the machine. OVFL indicator lights when the overflow flipflop is set. STEP indicator lights when the computer is in the step mode and the Micro-EXEC facility is not being used. RUN indicator lights when the computer is in the run mode. ALARM indicator lights when a thermal overload condition occurs. The RESET switch causes the selected register to be cleared. This switch is disabled when the computer is in the run mode. The STEP switch is a momentary-contact switch that causes the instruction in the instruction register to be executed if the computer is in the step mode. If the computer is in the run mode, pressing the STEP switch causes the computer to halt at the completion of the instruction being executed. The RU N switch causes the program to run at the location specifi ed by the program counter after first execu ti ng the instruction in the instruction register. The SYSTEM RESET switch is a system-clear control that forces the computer to the halt mode and initializes control flipflops in the processor. In addition, all peripheral devices are initialized by SYSTEM RESET. This control is normally used as an initialize control, but is useful to halt I/O operations. Toggle switch that permits manual repeat of an instruction in instruction register. Pressing STEP switch executes instruction and advances program counter; however, contents of the instruction register are left unchanged. Switch on the control console is activated only when the STEP light is on (operation halted). 5-3
Table 5-1. (Continued) Control or Indicator Function SE NSE Switches 1, 2, 3 POWER On/Off Toggle switches that permit manual program control whenever sense-switch- jump, jump-and-mark, or execute instructions (JSS 1, JSS2, JSS3, JS 1M, JS2M, JS3M, XS 1, XS2, XS3) are performed. The indicated jump and execute operations are performed only if the corresponding SENSE switch is ON. Alternate-action switch/indicator that turns power supplies on and off. I ndi ca tor/swi tch is i Ilumi na ted when power is on; indicator is off when power is off. To display the contents of any memory cell in the A, B, or X register; set the appropriate load-type instruction (LDA, LDB, LDX) with the proper memory address in the instruction register; then press the STEP switch to load the selected word into the register. To manually execute a program stored in memory, set the starting address of the program in the program counter. When the STEP switch is pressed, the instruction contained in the instruction register is executed, and the instruction of the selected address is transferred to the instruction register. Repeated operation of the STEP switch will then step through the program one instruction at a time. All operations such as multi-level indirect addressing will be performed for each instruction as the STEP switch is operated. Note that I/O instructions involving an asynchronous device that transfers data in a block (such as a magnetic tape unit or teletype) generally ca nnot be opera ted in the step mode. 5.2.3 Instruction Repeat I n the step mode, the instruction register contains the next instruction to be executed when STEP is pressed. The program counter contains the location of the next instruction to be transferred to the instruction register after the current instruction is execu ted. In some cases, it is desirable to manually execute an instruction several times. When the REPEAT switch is on, instruction register loading (when STEP is pressed) is inhibited even though the instruction counter is advanced each time. This mode is 5-4
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DATA 620/i SYSTEM REFERENCE MANUAL
Page 3 and 4:
VDM-3000 Revision A March 1968
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Page SECTION 5 CONTROL CONSOLE OPER
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The unique design of the DA TA 620/
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Table 1-1. (Continued) Specifi cati
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Table 1-1. (Continued) Specifi cati
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Detailed design and maintenance inf
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SET R., SET U'" J POI 26801A R REGI
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A register. This full-length regist
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made available on an external cable
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17 16 15 14 13 12 11 10 9 8 7 6 5 4
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n 17 16 15 14 13 12 11 10 9 8 7 6 5
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620/i -01 Memory /Periphera I Contr
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un ique memory destination address
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Table G-1 (d), appendix G, summariz
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P0131802A BRING INSTRUCTION (W-+U)
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Relative: Yes Indexing: Yes Indirec
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POl31804A BRING OPERAND ('N~U) BRIN
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I ncrement Memory and Replace Timin
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The contents of the A and B registe
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ANA AND Memory and A Timing: 2 cycl
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The overflow indicator (OF) is set.
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Indexing: No Indirect Addressing: N
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LLRL Long Logical Rotate Left Timin
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I ASLB I Arithmetic Shift B Left Ti
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
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The contents of the A (B, X) regist
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Indexing: No Indirect Addressing: N
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A¢FB Add Overflow to B Register Ti
Page 59 and 60: P0131807A r------, 1 BRING I : INST
Page 61 and 62: POJ3J808A BRING INSTRUCTION (W-+U)
Page 63 and 64: ~ Jump if A Register Zero Timing: 2
Page 65 and 66: ~ Jump if Sense Switch 3 Set Timing
Page 67 and 68: Indexing: No Indirect Addressing: Y
Page 69 and 70: JBZM Jump and Mark if B Register Ze
Page 71 and 72: Execute instru'ction group. For the
Page 73 and 74: X¢F Execute if Overflow Set Timing
Page 75 and 76: §] Execute it' B Regi ster Timing:
Page 77 and 78: Extended-addressing instruction gro
Page 79 and 80: STAE Store A Reg i ster Extended Ti
Page 81 and 82: ADDE Add Memory to A Timing: 3 cycl
Page 83 and 84: If (A,B) ~1 --;::x- (divisor> divid
Page 85 and 86: ANAE AND Memory and A Timing: 3 cyc
Page 87 and 88: LDXI Load X Reg i ste r Immediate T
Page 89 and 90: I ADDI I Add Immediate Timing: 2 cy
Page 91 and 92: (divisor> dividend, taken as a bina
Page 93 and 94: ANAl AND Immediate Timing: 2 cycles
Page 95 and 96: P0131811A A~ I L-BUS 1 r-J---, r-J-
Page 97 and 98: Table 4-1. I/O-Cable Control Line S
Page 99 and 100: P0131812A BRING INSTRUCTION (W-'U)
Page 101 and 102: ~ Clear and Input to B Register Tim
Page 103 and 104: ~ I o P0131813A BRING INSTRUCTION r
Page 105 and 106: . A trap timing sequence is initiat
Page 107 and 108: 4.4.2 Program Interrupt (optional)
Page 109: P0131815A DATA-.:aO/i Fig. 5-1 Cont
Page 113 and 114: APPENDICES
Page 115 and 116: DATA 620/i Number System Binary num
Page 117 and 118: The negative result is in error. Th
Page 119 and 120: ~ Standard DATA 620/i Subroutines I
Page 121 and 122: Appendix C Table of Powers of Two
Page 123 and 124: Appendix D Octal-Decimal Integer Co
Page 125 and 126: Octal-Decimal Integer Conversion Ta
Page 127 and 128: Octal-Decimal Integer Conversion Ta
Page 129 and 130: Octal-Decimal Fraction Conversion T
Page 131 and 132: Octal-DecImal Fraction Conversion T
Page 133 and 134: Appendix F DATA 620/i Instructions
Page 135 and 136: WDS/ Time Indirect I Mnemonic Octal
Page 137 and 138: Mnemonic Octal Description WDS/ Tim
Page 139 and 140: Appendix G DATA 620/i Instructions
Page 141 and 142: Table G-1 (c) Logical Instruction G
Page 143 and 144: Table G-3(b) Instruction Format Us
Page 145 and 146: Table G-5 Jump Instruction Group Ta
Page 147 and 148: Table G-7 Execute Instruction Group
Page 149 and 150: Table G-11 Input/Output Instruction
Page 151 and 152: Appendix H DA TA 620/i Reserved Ins
Page 153 and 154: Table H-2 BIC Reserved Instruction
Page 155 and 156: Table H-3(b) Model B Teletype Instr
Page 157 and 158: Table H-5 Gated-Input-Channel Reser
Page 159 and 160: Table H-7 Gated-Output-Channel Rese
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Table H-10 Magnetic Tape Unit Reser
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Appendix I DATA 620/i Standard BCD
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DATA 620/i Standard BCD Codes (cont
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Teletype Character Codes (continued
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DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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