DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

Timing logic generates the basic 4.4-MHz system clock.
From this clock, timing logic derives the timing pulses which
control the sequence of all operations in the computer.
The shift control contains the shift counter and logic to
control operations performed by the shift, multiply, and
divide instructions.
2.1.2 Airthmetic/Logic Section
This section consists of two elements; the R register and the
ari thmeti c un it.
The R register receives operands from memory and holds them
during instruction execution. The operand may be either data
or address words. Th i s reg i ster permits transfers be tween
memory and I/O bus during the execution of extended-cycle
instructions.
The arithmetic unit contains gating required for all arithmetic,
logic, and shifting operations performed by the
computer. Indexed and relative address modifications are
performed in this section without increased instruction
execution time.
The arithmetic unit also controls the gating of words from
the operational registers and the I/O bus onto the C bus
where they are distributed to the operational registers or
to memory registers. This facility is used to implement
many of the microinstructions of the computer.
2.1.3 Operational Registers
The basic DATA 620/i computer contains nine registers.
The operational registers consist of the A, B, X, and P
registers. The A, B, and X registers are directly accessible
to the programmer. The P register is indirectly accessible
through use of the jump-class instructions which modify the
program seque nce. The operati ona I reg is ters are descri bed
in the following paragraphs.
2-3