DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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~ Exclusive-OR Memory Timing: 3 cycles and A Extended (optiona I) n n+l 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 r-r- I I 00 13 X 1---1-- I I I Operand Address t2 L - l8-bit option An exclusive-OR operation is performed between the contents of the A register and the contents of the memory location as addressed by the operand address in location n + 1. The resu It is placed in the A register. If the same bit position of the memory location and the A register contains a zero, or if both bit positions contains a one, the result is zero. The truth table is shown below, where n = bit position: A(n) Condition Effective Memory Location (n) Result A{n) 0 0 0 1 1 0 1 1 0 1 1 0 Indexing: Yes Indirect Addressing: Yes Register <strong>Al</strong>tered: A 3-57
ANAE AND Memory and A Timing: 3 cycles Extended (opti ona I) n n+1 17 16 15 14 13 12 11 10 9 8 7 6 5 432 1 0 r-r- I I 00 6 15 X ~-+ti I l I l8-bit - option I Operand Address The logi cal-AND operation is performed between the contents of the A register and the contents of the memory location as addressed by the operand address in location n + 1. The resu It is placed in the A register. If the same bit position of both the memory location and the A register contains a one the result is a one. The truth table is shown below, where n = bit position: A(n) Condition Effective Memory Location (n) Result A(n) 0 0 0 1 1 0 1 1 0 0 0 1 Indexing: Yes Indirect Addressing: Yes Register <strong>Al</strong>tered: A 3.3.2 Double-Word Non-Addressing Instructions The double-word non-addressing instructions consist of the immediate instruction group. The operand for the immediate instruction is contained in the second word of the double-word instruction. Address modification is not permitted for this group of instructions. The immediate instruction group codes are summarized in table G-10, appendix G. 3-58
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DATA 620/i SYSTEM REFERENCE MANUAL
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VDM-3000 Revision A March 1968
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Page SECTION 5 CONTROL CONSOLE OPER
Page 7 and 8:
The unique design of the DA TA 620/
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Table 1-1. (Continued) Specifi cati
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Table 1-1. (Continued) Specifi cati
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Detailed design and maintenance inf
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SET R., SET U'" J POI 26801A R REGI
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A register. This full-length regist
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made available on an external cable
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17 16 15 14 13 12 11 10 9 8 7 6 5 4
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n 17 16 15 14 13 12 11 10 9 8 7 6 5
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620/i -01 Memory /Periphera I Contr
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un ique memory destination address
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Table G-1 (d), appendix G, summariz
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P0131802A BRING INSTRUCTION (W-+U)
Page 33 and 34: Relative: Yes Indexing: Yes Indirec
Page 35 and 36: POl31804A BRING OPERAND ('N~U) BRIN
Page 37 and 38: I ncrement Memory and Replace Timin
Page 39 and 40: The contents of the A and B registe
Page 41 and 42: ANA AND Memory and A Timing: 2 cycl
Page 43 and 44: The overflow indicator (OF) is set.
Page 45 and 46: Indexing: No Indirect Addressing: N
Page 47 and 48: LLRL Long Logical Rotate Left Timin
Page 49 and 50: I ASLB I Arithmetic Shift B Left Ti
Page 51 and 52: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
Page 53 and 54: The contents of the A (B, X) regist
Page 55 and 56: Indexing: No Indirect Addressing: N
Page 57 and 58: A¢FB Add Overflow to B Register Ti
Page 59 and 60: P0131807A r------, 1 BRING I : INST
Page 61 and 62: POJ3J808A BRING INSTRUCTION (W-+U)
Page 63 and 64: ~ Jump if A Register Zero Timing: 2
Page 65 and 66: ~ Jump if Sense Switch 3 Set Timing
Page 67 and 68: Indexing: No Indirect Addressing: Y
Page 69 and 70: JBZM Jump and Mark if B Register Ze
Page 71 and 72: Execute instru'ction group. For the
Page 73 and 74: X¢F Execute if Overflow Set Timing
Page 75 and 76: §] Execute it' B Regi ster Timing:
Page 77 and 78: Extended-addressing instruction gro
Page 79 and 80: STAE Store A Reg i ster Extended Ti
Page 81 and 82: ADDE Add Memory to A Timing: 3 cycl
Page 83: If (A,B) ~1 --;::x- (divisor> divid
Page 87 and 88: LDXI Load X Reg i ste r Immediate T
Page 89 and 90: I ADDI I Add Immediate Timing: 2 cy
Page 91 and 92: (divisor> dividend, taken as a bina
Page 93 and 94: ANAl AND Immediate Timing: 2 cycles
Page 95 and 96: P0131811A A~ I L-BUS 1 r-J---, r-J-
Page 97 and 98: Table 4-1. I/O-Cable Control Line S
Page 99 and 100: P0131812A BRING INSTRUCTION (W-'U)
Page 101 and 102: ~ Clear and Input to B Register Tim
Page 103 and 104: ~ I o P0131813A BRING INSTRUCTION r
Page 105 and 106: . A trap timing sequence is initiat
Page 107 and 108: 4.4.2 Program Interrupt (optional)
Page 109 and 110: P0131815A DATA-.:aO/i Fig. 5-1 Cont
Page 111 and 112: Table 5-1. (Continued) Control or I
Page 113 and 114: APPENDICES
Page 115 and 116: DATA 620/i Number System Binary num
Page 117 and 118: The negative result is in error. Th
Page 119 and 120: ~ Standard DATA 620/i Subroutines I
Page 121 and 122: Appendix C Table of Powers of Two
Page 123 and 124: Appendix D Octal-Decimal Integer Co
Page 125 and 126: Octal-Decimal Integer Conversion Ta
Page 127 and 128: Octal-Decimal Integer Conversion Ta
Page 129 and 130: Octal-Decimal Fraction Conversion T
Page 131 and 132: Octal-DecImal Fraction Conversion T
Page 133 and 134: Appendix F DATA 620/i Instructions
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WDS/ Time Indirect I Mnemonic Octal
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Mnemonic Octal Description WDS/ Tim
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Appendix G DATA 620/i Instructions
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Table G-1 (c) Logical Instruction G
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Table G-3(b) Instruction Format Us
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Table G-5 Jump Instruction Group Ta
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Table G-7 Execute Instruction Group
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Table G-11 Input/Output Instruction
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Appendix H DA TA 620/i Reserved Ins
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Table H-2 BIC Reserved Instruction
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Table H-3(b) Model B Teletype Instr
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Table H-5 Gated-Input-Channel Reser
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Table H-7 Gated-Output-Channel Rese
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Table H-10 Magnetic Tape Unit Reser
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Appendix I DATA 620/i Standard BCD
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DATA 620/i Standard BCD Codes (cont
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Teletype Character Codes (continued
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DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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