DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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Table G-1 Single-Word Addressed Instructions Table G-1 (a) Load/Store Instruction Group Op Code Octal Mnemonic Instruction I Timing (Cycles) 01 02 03 05 06 07 LDA LDB LDX STA STB STX Load A Reg ister Load B Register Load X Register Store A Reg ister Store B Register Store X Register 2 2 2 2 2 2 Table G-1 (b) Arithmetic Instruction Group Op Code Octal Mnemonic Instruction Timing (Cycles) 04 12 14 16 17 INR Increment and Replace ADD Add Memory to A SUB Subtract Memory from A MUL(*) Multiply l6-bit l8-bit DIV(*) Divide l6-bi t l8-bit 3 2 2 10 11 10-14 11-15 *Optional Instructions G-l
Table G-1 (c) Logical Instruction Group Op Code Octal Mnemonic Instruction Timing (Cycles) 11 ~RA 13 ERA 15 ANA Inc lusive OR, Memory and A Exc I usive OR, Memory and A AND Memory and A 2 2 2 Table G-1 (d) Addressing Modes for Single Word Addressed Instructions M Field 1 1 10 9 Addressing Mode Operation a x X Direct Combine bits 9, 10 with a field (0-8) to form effective address (0000 - 2047). 1 0 a Relative Add a fiel d (bits 0-8) to contents of P to form effective address (Mod 2 15 ). 1 0 1 Index Add a field (bits 0-8) to contents (X Register) of X to form effective address (Mod 2 15 ). 1 1 a Index Add a field (bits 0-8) to contents (B Register) of B to form effective address (Mod 2 15 ). 1 1 1 Indirect a field (bits 0-8) specifies location of an address word. G-2
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DATA 620/i SYSTEM REFERENCE MANUAL
Page 3 and 4:
VDM-3000 Revision A March 1968
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Page SECTION 5 CONTROL CONSOLE OPER
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The unique design of the DA TA 620/
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Table 1-1. (Continued) Specifi cati
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Table 1-1. (Continued) Specifi cati
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Detailed design and maintenance inf
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SET R., SET U'" J POI 26801A R REGI
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A register. This full-length regist
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made available on an external cable
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17 16 15 14 13 12 11 10 9 8 7 6 5 4
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n 17 16 15 14 13 12 11 10 9 8 7 6 5
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620/i -01 Memory /Periphera I Contr
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un ique memory destination address
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Table G-1 (d), appendix G, summariz
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P0131802A BRING INSTRUCTION (W-+U)
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Relative: Yes Indexing: Yes Indirec
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POl31804A BRING OPERAND ('N~U) BRIN
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I ncrement Memory and Replace Timin
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The contents of the A and B registe
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ANA AND Memory and A Timing: 2 cycl
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The overflow indicator (OF) is set.
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Indexing: No Indirect Addressing: N
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LLRL Long Logical Rotate Left Timin
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I ASLB I Arithmetic Shift B Left Ti
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
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The contents of the A (B, X) regist
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Indexing: No Indirect Addressing: N
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A¢FB Add Overflow to B Register Ti
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P0131807A r------, 1 BRING I : INST
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POJ3J808A BRING INSTRUCTION (W-+U)
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~ Jump if A Register Zero Timing: 2
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~ Jump if Sense Switch 3 Set Timing
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Indexing: No Indirect Addressing: Y
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JBZM Jump and Mark if B Register Ze
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Execute instru'ction group. For the
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X¢F Execute if Overflow Set Timing
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§] Execute it' B Regi ster Timing:
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Extended-addressing instruction gro
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STAE Store A Reg i ster Extended Ti
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ADDE Add Memory to A Timing: 3 cycl
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If (A,B) ~1 --;::x- (divisor> divid
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ANAE AND Memory and A Timing: 3 cyc
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LDXI Load X Reg i ste r Immediate T
Page 89 and 90: I ADDI I Add Immediate Timing: 2 cy
Page 91 and 92: (divisor> dividend, taken as a bina
Page 93 and 94: ANAl AND Immediate Timing: 2 cycles
Page 95 and 96: P0131811A A~ I L-BUS 1 r-J---, r-J-
Page 97 and 98: Table 4-1. I/O-Cable Control Line S
Page 99 and 100: P0131812A BRING INSTRUCTION (W-'U)
Page 101 and 102: ~ Clear and Input to B Register Tim
Page 103 and 104: ~ I o P0131813A BRING INSTRUCTION r
Page 105 and 106: . A trap timing sequence is initiat
Page 107 and 108: 4.4.2 Program Interrupt (optional)
Page 109 and 110: P0131815A DATA-.:aO/i Fig. 5-1 Cont
Page 111 and 112: Table 5-1. (Continued) Control or I
Page 113 and 114: APPENDICES
Page 115 and 116: DATA 620/i Number System Binary num
Page 117 and 118: The negative result is in error. Th
Page 119 and 120: ~ Standard DATA 620/i Subroutines I
Page 121 and 122: Appendix C Table of Powers of Two
Page 123 and 124: Appendix D Octal-Decimal Integer Co
Page 125 and 126: Octal-Decimal Integer Conversion Ta
Page 127 and 128: Octal-Decimal Integer Conversion Ta
Page 129 and 130: Octal-Decimal Fraction Conversion T
Page 131 and 132: Octal-DecImal Fraction Conversion T
Page 133 and 134: Appendix F DATA 620/i Instructions
Page 135 and 136: WDS/ Time Indirect I Mnemonic Octal
Page 137 and 138: Mnemonic Octal Description WDS/ Tim
Page 139: Appendix G DATA 620/i Instructions
Page 143 and 144: Table G-3(b) Instruction Format Us
Page 145 and 146: Table G-5 Jump Instruction Group Ta
Page 147 and 148: Table G-7 Execute Instruction Group
Page 149 and 150: Table G-11 Input/Output Instruction
Page 151 and 152: Appendix H DA TA 620/i Reserved Ins
Page 153 and 154: Table H-2 BIC Reserved Instruction
Page 155 and 156: Table H-3(b) Model B Teletype Instr
Page 157 and 158: Table H-5 Gated-Input-Channel Reser
Page 159 and 160: Table H-7 Gated-Output-Channel Rese
Page 161 and 162: Table H-10 Magnetic Tape Unit Reser
Page 163 and 164: Appendix I DATA 620/i Standard BCD
Page 165 and 166: DATA 620/i Standard BCD Codes (cont
Page 167: Teletype Character Codes (continued
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DATA 620/i SYSTEM REFERENCE MANUAL . - Al Kossow's Bitsavers

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