AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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B76 B75 A86 A85 A84 B74 B73 B72 B71 B70 A83 A82 A81 A80 A79 B69 A78 B68 B67 B66 A77 A76 A75 B65 A74 B64 B63 A73 B62 A72 A71 B61 B60 A70 A69 B59 A68 DVDD VDD33_SVR LX LED_LINK1000n_3 LED_LINK100n_3 LED_LINK10n_3 VDD25_IO LED_LINK1000n_2 LED_LINK100n_2 LED_LINK10n_2 LED_LINK1000n_1 LED_LINK100n_1 LED_LINK10n_1 LED_LINK1000n_0 LED_LINK100n_0 LED_LINK10n_0 INTN SIP SIN AVDD SOP SON TESTMODE TXD3_0 TXD2_0 TXD1_0 TXD0_0 GTXCLK_0/TXCLK_0 FILCAP1_15_0 TXEN/TXCTR_0 DVDD FILCAP0_15_0 RXD3_0 RXD2_0 VDD15_REG_0 RXD1_0 RXD0_0 DVDD FILCAP0 CH0_TRXP0 CH0_TRXN0 AVDD CH0_TRXP1 CH0_TRXN1 VDD33 CH0_TRXP2 CH0_TRXN2 AVDD CH0_TRXP3 CH0_TRXN3 VDD25_REG VREF VDD33 RBIAS0 AVDD25 XTLI AVDDCO_0 XTLO AVDD FILCAP2 CH1_TRXP0 CH1_TRXN0 AVDD CH1_TRXP1 CH1_TRXN1 VDD33 CH1_TRXP2 CH1_TRXN2 AVDD CH1_TRXP3 CH1_TRXN3 FILCAP3 DVDD FILCAP4 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 B8 A10 B9 A11 B10 A12 B11 A13 B12 A14 B13 A15 B14 A16 B15 A17 B16 A18 B17 A19 B18 A20 B19 B 1 A 3 B 19 A 20 A 86 B 76 B 20 A 25 AR8327 TOP VIEW GND (Exposed Ground PAD) AR8327 TOP VIEW A 68 B 59 B 38 A 42 B 56 A 65 B 39 A 47 Figure 1-1. 148 Pin DRQFN Package Pinout (Part 1) 14 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 14 • June 2011 COMPANY CONFIDENTIAL
B 1 A 3 B 19 A 20 A 86 B 76 B 20 A 25 AR8327 TOP VIEW AR8327 TOP VIEW GND (Exposed Ground PAD) A 68 B 59 B 38 A 42 B39 A65 A64 B56 A63 B55 A62 B54 A61 B53 A60 B52 A59 B51 A58 B50 A57 B49 A56 B48 A55 B47 A54 B46 A53 B45 A52 B44 A51 B43 A50 B42 A49 B41 A48 B40 A47 B39 RXCLK_0 RXDV_0/RXCTR_0 DVDD VDD25_IO UART_RXD/MDC UART_TXD/MDIO DVDD FILCAP0_15_1 TXD3_1 TXD2_1 TXD1_1 TXD0_1 GTXCLK_1/TXCLK_1 TXEN/TXCTR_1 DVDD RXD3_1 RXD2_1 VDD15_REG_1 RXD1_1 RXD0_1 RXCLK_1 RXDV_1/RXCTR_1 VDD25_IO DVDD SPI_CLK SPI_CS SPI_DO SPI_DI RESET_L LED_LINK1000n_4 LED_LINK100n_4 LED_LINK10n_4 VDD25_IO CH4_TRXN3 CH4_TRXP3 AVDD CH4_TRXN2 CH2_TRXP0 CH2_TRXN0 AVDD CH2_TRXP1 CH2_TRXN1 VDD33 CH2_TRXP2 CH2_TRXN2 AVDD CH2_TRXP3 CH2_TRXN3 FILCAP5 CH3_TRXP0 CH3_TRXN0 AVDD CH3_TRXP1 CH3_TRXN1 VDD33 AVDD AVDDVCO_1 RBIAS1 VREF FILCAP6 VDD33 CH3_TRXP2 CH3_TRXN2 AVDD CH3_TRXP3 CH3_TRXN3 FILCAP7 CH4_TRXP0 CH4_TRXN0 AVDD CH4_TRXP1 CH4_TRXN1 VDD33 CH4_TRXP2 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 A35 B31 A36 B32 A37 B33 A38 B34 A39 B35 A40 B36 A41 B37 A42 B38 B 56 A 65 B 39 A 47 Figure 1-2. 148 Pin DRQFN Package Pinout (Part 2) Atheros Communications, Inc. Switch • 15 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13: 1. Pin Descriptions This section co
Page 17 and 18: Table 1-1. Signal to Pin Relationsh
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25 and 26: Table 2-1. Atheros Header Type 5'h1
Page 27 and 28: duplex flow control mode is not set
Page 29 and 30: Table 2-6. Action Definition 41 CTA
Page 31 and 32: Table 2-9. IPv4 Pattern 15 [7:6] RE
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37 and 38: 2.9 LED Control There are totally 6
Page 39 and 40: Mode is checking if the ingress VID
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43 and 44: Table 2-29. Application Cases 1 and
Page 45 and 46: Table 2-30. MIB Counters (continued
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66:
Table 3-9. Global Interrupt Registe
Page 67 and 68:
Table 3-11. Global Interrupt Mask R
Page 69 and 70:
Table 3-14 summarizes the MIB Funct
Page 71 and 72:
Table 3-17 summarizes the BIST_CTRL
Page 73 and 74:
Table 3-21 summerizes LED_CTRL1 Reg
Page 75 and 76:
SFT&HW RST Table 3-26 summarizes th
Page 77 and 78:
Table 3-28. Port 1 Status Register
Page 79 and 80:
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Page 83 and 84:
Table 3-35. PORT 0 Header Control R
Page 85 and 86:
3.2.36 PORT4_HEADER_CTRL Address 0x
Page 87 and 88:
Table 3-42 summarizes the SGMII_CTR
Page 89 and 90:
3.3 EEE CTRL REGISTER SUMMARY (Addr
Page 91 and 92:
Table 3-48. PORT 2 EEE Variable Reg
Page 93 and 94:
Table 3-54. PORT 4 EEE Variable Reg
Page 95 and 96:
3.4 PARSER REGISTER SUMMARY(Address
Page 97 and 98:
Bit R/W Inital Value Mnemonic Descr
Page 99 and 100:
Table 3-64. Frame Ack Control Regis
Page 101 and 102:
Page 103 and 104:
3.4.9 WIN_RULE_CTRL3 Address 0x0224
Page 105 and 106:
Table 3-72. Window Rule Control Reg
Page 107 and 108:
Table 3-76. Window Rule Control Reg
Page 109 and 110:
3.5 ACL REGISTER (Address Range: 0x
Page 111 and 112:
Table 3-86. ACL Function Register 4
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
SFT&HW RST Table 3-95 summarizes th
Page 119 and 120:
3.5.17 PORT4_VLAN_CTRL1 Address 0x0
Page 121 and 122:
Page 123 and 124:
Table 3-103 summarizes the IPv6 Pri
Page 125 and 126:
3.6.1 ATU_DATA0 Address 0x0600 SFT&
Page 127 and 128:
Table 3-110. ATU_FUNC_REG Register
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Page 161 and 162:
SFT&HW RST Table 3-140 summarizes t
Page 163 and 164:
Table 3-142. Port 5 Lookup Control
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Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Table 3-148. Global Trunk Control R
Page 175 and 176:
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Table 3-151. Parser Register Summar
Page 179 and 180:
Table 3-151. Parser Register Summar
Page 181 and 182:
Table 3-153, “QM Control Register
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Table 3-159. Port 3 WRR Control Reg
Page 189 and 190:
Table 3-161. Port 5 WRR Control Reg
Page 191 and 192:
Table 3-163. Port 0 Rate Limit Cont
Page 193 and 194:
Table 3-166, “Port 0 Rate Limit C
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Page 203 and 204:
3.7.21 PORT1_EG_RATE_CTRL0 Address
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Page 213 and 214:
Inital Bit R/W Value Mnemonic Descr
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Page 251 and 252:
Table 3-226. Port 1 Flow Control Th
Page 253 and 254:
Bit R/W 15:8 R/O 0 RESERVED Inital
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Table 3-239. ACL_2 Rate Control Reg
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Page 267 and 268:
Page 269 and 270:
Table 3-248, “ACL_6 Rate Control
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Table 3-257. ACL_11 Rate Control Re
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
SFT&HW RST Table 3-267, “ACL_16 R
Page 283 and 284:
Table 3-270. ACL_17 Rate Limit Cont
Page 285 and 286:
Table 3-273. ACL_19 Rate Limit Cont
Page 287 and 288:
Page 289 and 290:
3.7.129 ACL_RATE_CTRL1_22 Address 0
Page 291 and 292:
3.7.132 ACL_RATE_CTRL0_24 Address 0
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Table 3-296, “ACL_30 Rate Limit C
Page 301 and 302:
Page 303 and 304:
Table 3-301. Port 0 Ingress Rate Li
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
SFT&HW RST Table 3-308, “Port 3 I
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Table 3-317, “Port 6 Ingress Rate
Page 319 and 320:
Page 321 and 322:
3.8 PKT EDIT REGISTER(Address Range
Page 323 and 324:
Table 3-324. Port 0 Queue Remap Reg
Page 325 and 326:
Page 327 and 328:
Table 3-331, “Port 6 Queue Remap
Page 329 and 330:
3.8.14 Router Default VID Register
Page 331 and 332:
Page 333 and 334:
Page 335 and 336:
Table 3-348. WCMP Next Hop Table 1
Page 337 and 338:
Table 3-353. HNAT Control Register
Page 339 and 340:
3.9.18 NAPT_Used_Account Address 0x
Page 341 and 342:
Page 343 and 344:
3.10 PHY Control Registers Table 3-
Page 345 and 346:
Table 3-366. Control Register Bit S
Page 347 and 348:
Bit Symbol Type Description 8 Exten
Page 349 and 350:
Bit Symbol Type Description 14 Ack
Page 351 and 352:
Bit Symbol Type Description 14 Ack
Page 353 and 354:
Table 3-373, “Next Page Transmit
Page 355 and 356:
Bit Symbol Type Description 11 Mast
Page 357 and 358:
Table 3-377. MMD Access Control Reg
Page 359 and 360:
Bit Symbol Type Description 2 SQE T
Page 361 and 362:
Bit Symbol Type Description 14 Spee
Page 363 and 364:
Bit Symbol Type Description 8 False
Page 365 and 366:
Table 3-385. Status Register Bit Sy
Page 367 and 368:
Table 3-389. Debug Port 2 (R/W Port
Page 369 and 370:
Table 3-391. Debug Register — Sys
Page 371 and 372:
3.10.28 Debug Register—Hib Contro
Page 373 and 374:
Bit Symbol Type Description 5 RES M
Page 375 and 376:
Table 3-397. PCS Control1 Bit Symbo
Page 377 and 378:
3.13 MMD7 — Auto-negotiation Regi
Page 379 and 380:
Device Address = 7 Table 3-403 summ
Page 381 and 382:
Table 3-409. EEE Advertisement Bit
Page 383 and 384:
4. Electrical Characteristics 4.1 A
Page 385 and 386:
4.4.12 Power-on-Reset Timing Figure
Page 387 and 388:
4.5.3 GMII Timing Figure 4-4 shows
Page 389 and 390:
4.5.5 SPI Timing Figure 4-6 shows t
Page 391 and 392:
5. Package Dimensions The AR8327 is
Page 393 and 394:
6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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