AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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Table 2-22. LED Rule Default Value (continued) 13 FULL_LIGHT_EN 1’b0 1’b0 1’b0 12 HALF_LIGHT_EN 1’b0 1’b0 1’b0 11 POWER_ON_LIGHT_EN 1’b1 1’b1 1’b1 10 LINK_1000M_LIGHT_EN 1’b1 1’b0 1’b0 9 LINK_100M_LIGHT_EN 1’b0 1’b1 1’b0 8 LINK_10M_LIGHT_EN 1’b0 1’b0 1’b1 7 COL_BLINK_EN 1’b0 1’b0 1’b0 6 Reserved 1’b0 1’b0 1’b0 5 RX_BLINK_EN 1’b1 1’b1 1’b1 4 TX_BLINK_EN 1’b1 1’b1 1’b1 3 Reserved 1’b0 1’b0 1’b0 2 LINKUP_OVER_EN 1’b1 1’b1 1’b1 1:0 LED_BLINK_RFREQ 1’b01: 4Hz 1’b01: 4Hz 1’b01: 4Hz 2.10 VLANs The AR8327 switch supports many VLAN options including IEEE 802.1Q and port-based VLANs. The AR8327 supports 4096 IEEE 802.1Q VLAN groups and 4K VLAN table entries, and the AR8327 device checks VLAN port membership from the VLAN ID, extracted from the tag header of the frame. Table 2-18 shows the AR8327-supported 802.1Q modes. The port-based VLAN is enabled according to the user-defined PORT VID value. The AR8327 supports optional discards of tagged, untagged frames, and priority tagged frames. The AR8327 also supports untagging of the VLAN ID for packets going out on untagged ports on a per-port basis. The AR8327 also support double Tagging frame which is S-Tag and C-Tag. The AR8327 can lookup the 4K VLAN table by S-Tag or C-Tag depending on the configuration mode. There are also 64 entry in VLAN translation table supporting the VLAN operation. 2.10.1 Port-Based VLAN The AR8327 switch supports port-based VLAN functionality used for non-management frames when 802.1Q is disabled on the ingress port. When FORCE_PORT_VLAN_EN is enabled, non-management frames conform to port-based configurations even if 802.1Q is enabled on the ingress port. Each ingress port contains a register that restricts the output (or egress) ports to which it can to send frames. This port-based VLAN register has a field called PORT_VID_MEM that contains the port based setting. If bit 0 of a port's PORT_VID_MEM is set to a one, the port is allowed to send frames to Port 0, bit [2] for Port 2, and so on. At reset, the PORT_VID_MEM for each port is set to a value of all 1s, except for each port's own bit, which clears to zero. Note that the CPU port is port 0. 2.10.2 802.1Q VLANs The AR8327 supports a maximum of 4096 entries in the VLAN table. The device supports 4096 VLAN ID range from 0 to 4095. The AR8327 supports both shared and independent VLAN learning (SVL and IVL). This means that forwarding decisions are based on the frame's destination MAC address, which should be unique among all VLANs. 2.10.3 VLAN Security The AR8327 will check the ingress packets base on the VLAN operation mode and decide forward or drop the packets. There are two sets of configuration. One is the Ingress VLAN Mode. Another is 802.1Q Mode. The Ingress VLAN Mode is checking the ingress frame is tagging or not. The 802.1Q 38 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 38 • June 2011 COMPANY CONFIDENTIAL
Mode is checking if the ingress VID is valid and if the ingress port is belong to the member. The following tables show the detail. Table 2-23. VLAN Security ING_VLAN_MODE Frame with Tag Frame with Priority Tagging Frame without Tag 2’b00 Forward Forward Forward 2’b01 Forward Drop Drop 2’b10 Drop Forward Forward 2’b11 Forward Forward Forward Table 2-24. VLAN Security 802.1Q VID miss VLAN member violation No violation Secure Drop Drop Forward Use VLAN Table Result Check Drop Forward Use VLAN Table Result Fallback Disable Forward Use VLAN Table Result Forward Use VLAN Table Result Forward Use Port-based VLAN Forward Use VLAN Table Result Forward Use VLAN Table Result 2.10.4 Port Isolation When FORCE_PORT_VLAN_EN is enabled on the ingress port, except for VLAN member check, nonmanagement frames will conform to port-based VLAN member check. 2.10.5 Leaky VLAN The AR8327 support leaky VLAN to enable specific frames to be forwarded across VLAN boundary. Totally four types of frames can be leaked across VLAN boundary: Unicast, Multicast and ARP, among which Unicast and Multicast leaky are port or MAC address based and ARP is port based. 2.10.6 VLAN Translation The AR8327 supports VLAN translation function. The AR8327 will lookup the VLAN translation table when packets arrive at the ingress port and packets transmit at the egress port. 2.10.7 VLAN Translation Table The VLAN translation table allows user to modify the C-VID and/or S-VID. The table is shown below. Table 2-25. VLAN Translation Table Bit Name Description 11:0 O_VID Original VID 23:12 S_VID Service VID 35:24 C_VID Custom VID Atheros Communications, Inc. Switch • 39 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13 and 14: 1. Pin Descriptions This section co
Page 15 and 16: B 1 A 3 B 19 A 20 A 86 B 76 B 20 A
Page 17 and 18: Table 1-1. Signal to Pin Relationsh
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25 and 26: Table 2-1. Atheros Header Type 5'h1
Page 27 and 28: duplex flow control mode is not set
Page 29 and 30: Table 2-6. Action Definition 41 CTA
Page 31 and 32: Table 2-9. IPv4 Pattern 15 [7:6] RE
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37: 2.9 LED Control There are totally 6
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43 and 44: Table 2-29. Application Cases 1 and
Page 45 and 46: Table 2-30. MIB Counters (continued
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66: Table 3-9. Global Interrupt Registe
Page 67 and 68: Table 3-11. Global Interrupt Mask R
Page 69 and 70: Table 3-14 summarizes the MIB Funct
Page 71 and 72: Table 3-17 summarizes the BIST_CTRL
Page 73 and 74: Table 3-21 summerizes LED_CTRL1 Reg
Page 75 and 76: SFT&HW RST Table 3-26 summarizes th
Page 77 and 78: Table 3-28. Port 1 Status Register
Page 83 and 84: Table 3-35. PORT 0 Header Control R
Page 85 and 86: 3.2.36 PORT4_HEADER_CTRL Address 0x
Page 87 and 88: Table 3-42 summarizes the SGMII_CTR
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3.3 EEE CTRL REGISTER SUMMARY (Addr
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Table 3-48. PORT 2 EEE Variable Reg
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Table 3-54. PORT 4 EEE Variable Reg
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3.4 PARSER REGISTER SUMMARY(Address
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Bit R/W Inital Value Mnemonic Descr
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Table 3-64. Frame Ack Control Regis
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3.4.9 WIN_RULE_CTRL3 Address 0x0224
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Table 3-72. Window Rule Control Reg
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Table 3-76. Window Rule Control Reg
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3.5 ACL REGISTER (Address Range: 0x
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Table 3-86. ACL Function Register 4
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SFT&HW RST Table 3-95 summarizes th
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3.5.17 PORT4_VLAN_CTRL1 Address 0x0
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Table 3-103 summarizes the IPv6 Pri
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3.6.1 ATU_DATA0 Address 0x0600 SFT&
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Table 3-110. ATU_FUNC_REG Register
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SFT&HW RST Table 3-140 summarizes t
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Table 3-142. Port 5 Lookup Control
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Table 3-148. Global Trunk Control R
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Table 3-151. Parser Register Summar
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Table 3-151. Parser Register Summar
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Table 3-153, “QM Control Register
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Table 3-159. Port 3 WRR Control Reg
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Table 3-161. Port 5 WRR Control Reg
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Table 3-163. Port 0 Rate Limit Cont
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Table 3-166, “Port 0 Rate Limit C
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3.7.21 PORT1_EG_RATE_CTRL0 Address
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Inital Bit R/W Value Mnemonic Descr
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Table 3-226. Port 1 Flow Control Th
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Bit R/W 15:8 R/O 0 RESERVED Inital
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Table 3-239. ACL_2 Rate Control Reg
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Table 3-248, “ACL_6 Rate Control
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Table 3-257. ACL_11 Rate Control Re
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SFT&HW RST Table 3-267, “ACL_16 R
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Table 3-270. ACL_17 Rate Limit Cont
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Table 3-273. ACL_19 Rate Limit Cont
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3.7.129 ACL_RATE_CTRL1_22 Address 0
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3.7.132 ACL_RATE_CTRL0_24 Address 0
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Table 3-296, “ACL_30 Rate Limit C
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Table 3-301. Port 0 Ingress Rate Li
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SFT&HW RST Table 3-308, “Port 3 I
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Table 3-317, “Port 6 Ingress Rate
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3.8 PKT EDIT REGISTER(Address Range
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Table 3-324. Port 0 Queue Remap Reg
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Table 3-331, “Port 6 Queue Remap
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3.8.14 Router Default VID Register
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Table 3-348. WCMP Next Hop Table 1
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Table 3-353. HNAT Control Register
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3.9.18 NAPT_Used_Account Address 0x
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3.10 PHY Control Registers Table 3-
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Table 3-366. Control Register Bit S
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Bit Symbol Type Description 8 Exten
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Bit Symbol Type Description 14 Ack
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Bit Symbol Type Description 14 Ack
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Table 3-373, “Next Page Transmit
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Bit Symbol Type Description 11 Mast
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Table 3-377. MMD Access Control Reg
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Bit Symbol Type Description 2 SQE T
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Bit Symbol Type Description 14 Spee
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Bit Symbol Type Description 8 False
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Table 3-385. Status Register Bit Sy
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Table 3-389. Debug Port 2 (R/W Port
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Table 3-391. Debug Register — Sys
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3.10.28 Debug Register—Hib Contro
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Bit Symbol Type Description 5 RES M
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Table 3-397. PCS Control1 Bit Symbo
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3.13 MMD7 — Auto-negotiation Regi
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Device Address = 7 Table 3-403 summ
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Table 3-409. EEE Advertisement Bit
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4. Electrical Characteristics 4.1 A
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4.4.12 Power-on-Reset Timing Figure
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4.5.3 GMII Timing Figure 4-4 shows
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4.5.5 SPI Timing Figure 4-6 shows t
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5. Package Dimensions The AR8327 is
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6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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