AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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Table 1-1. Signal to Pin Relationships and Descriptions Symbol Pin Type Description Media Connection CH0_TRXN0 A4 IA, OA Media-dependent interface, MDI[3:0]: Transmitter output CH0_TRXP0 B2 positive/negative CH0_TRXN1 B4 IA, OA Connect derectly to Transformer without any pull-down CH0_TRXP1 A5 terminators, such as resistors or capacitors, required. CH0_TRXN2 A7 IA, OA CH0_TRXP2 B5 CH0_TRXN3 B7 IA, OA CH0_TRXP3 A8 CH1_TRXN0 B13 IA, OA Media-dependent interface, MDI[3:0]: Transmitter output CH1_TRXP0 A14 positive/negative CH1_TRXN1 A16 IA, OA Connect derectly to Transformer without any pull-down CH1_TRXP1 B14 terminators, such as resistors or capacitors, required. CH1_TRXN2 B16 IA, OA CH1_TRXP2 A17 CH1_TRXN3 A19 IA, OA CH1_TRXP3 B17 CH2_TRXN0 A25 IA, OA Media-dependent interface, MDI[3:0]: Transmitter output CH2_TRXP0 B20 positive/negative CH2_TRXN1 B22 IA, OA Connect derectly to Transformer without any pull-down CH2_TRXP1 A26 terminators, such as resistors or capacitors, required. CH2_TRXN2 A28 IA, OA CH2_TRXP2 B23 CH2_TRXN3 B25 IA, OA CH2_TRXP3 A29 CH3_TRXN0 A31 IA, OA Media-dependent interface, MDI[3:0]: Transmitter output CH3_TRXP0 B26 positive/negative CH3_TRXN1 B28 IA, OA Connect derectly to XFMR without any pull-down terminators, CH3_TRXP1 A32 such as resistors or capacitors, required. CH3_TRXN2 A37 IA, OA CH3_TRXP2 B32 CH3_TRXN3 B34 IA, OA CH3_TRXP3 A38 16 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 16 • June 2011 COMPANY CONFIDENTIAL
Table 1-1. Signal to Pin Relationships and Descriptions (continued) Symbol Pin Type Description CH4_TRXN0 A40 IA, OA Media-dependent interface, MDI[3:0]: Transmitter output CH4_TRXP0 B35 positive/negative CH4_TRXN1 B37 IA, OA Connect directly to XFMR without any pull-down terminators, CH4_TRXP1 A41 such as resistors or capacitors, required. CH4_TRXN2 B39 IA, OA CH4_TRXP2 B38 CH4_TRXN3 A48 IA, OA CH4_TRXP3 B40 MAC 0/CPU port GMII/RGMII interface GTXCLK_0/TXCLK_0 A73 I/O, PU RGMII transmit clock, 125 MHz/25 MHz, or configurable. This is the reference clock input for RGMII mode, PHY type interface, or MII mode MAC type interface. It also supports 50MHz clock input (Turbo-MII) when operating in MII mode, MAC type interface. RXCLK_0 A65 I/O, PD RGMII receive clock. This is output clock from MAC0 when AR8327 operates a PHY type interface. It can be 125MHz/ 25MHz/2.5MHz —depending upon the operating speed. RXD0_0 A68 I/O, PD RGMII/MII — receive data or configuration; recommend RXD1_0 A69 I/O, PD adding a 22 damping resistor. these are output signals from MAC0. The RXD[3:0]_0 are used as data input when operating RXD2_0 A70 I/O, PD at RGMII or MII mode. The reference clock for these output signals will be: RXD3_0 B60 I/O, PD RXCLK_0 (pin A65): RGMII/MII PHY type interface and GMII-MAC type interface. RXDV_0/RXCTR_0 A64 I/O, PD RGMII/MII received data; valid. This is output signal for MAC0. TXEN/TXCTR_0 A72 I, PD RGMII/MII transmit enable, this is input signal for the MAC0. TXD0_0 B63 I, PD RGMII/MII transmit data, these are input signals for MAC0. TXD1_0 A74 I, PD All the data bits TXD[7:0]_0 are used in GMII mode. The TXD[3:0]_0 are used as data input when operating on RGMII TXD2_0 B64 I, PD or MII mode. The reference clock for these input signals will be: TXD3_0 A75 I, PD 1. GTXCLK_0 (pin A73): RGMII/MII mode 2. GTXCLK_0 (pin B51): GMII mode MAC 6/PHY 4 RGMII/MII GTXCLK_1/TXCLK_1 B51 I/O, PD RGMII transmit clock, 125 MHz/25 MHz, or configuration. This is the reference clock input for RGMII mode PHY type interface or MII mode MAC type interface. RXCLK_1 B47 I/O, PD RGMII receive clock. This is output clock from PHY 4 when the AR8327 operates a PHY type interface. It can be 125MHz/ 25MHz/2.5MHz depending on the operating speed. Atheros Communications, Inc. Switch • 17 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13 and 14: 1. Pin Descriptions This section co
Page 15: B 1 A 3 B 19 A 20 A 86 B 76 B 20 A
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25 and 26: Table 2-1. Atheros Header Type 5'h1
Page 27 and 28: duplex flow control mode is not set
Page 29 and 30: Table 2-6. Action Definition 41 CTA
Page 31 and 32: Table 2-9. IPv4 Pattern 15 [7:6] RE
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37 and 38: 2.9 LED Control There are totally 6
Page 39 and 40: Mode is checking if the ingress VID
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43 and 44: Table 2-29. Application Cases 1 and
Page 45 and 46: Table 2-30. MIB Counters (continued
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66: Table 3-9. Global Interrupt Registe
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Table 3-11. Global Interrupt Mask R
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Table 3-14 summarizes the MIB Funct
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Table 3-17 summarizes the BIST_CTRL
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Table 3-21 summerizes LED_CTRL1 Reg
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SFT&HW RST Table 3-26 summarizes th
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Table 3-28. Port 1 Status Register
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Table 3-35. PORT 0 Header Control R
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3.2.36 PORT4_HEADER_CTRL Address 0x
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Table 3-42 summarizes the SGMII_CTR
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3.3 EEE CTRL REGISTER SUMMARY (Addr
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Table 3-48. PORT 2 EEE Variable Reg
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Table 3-54. PORT 4 EEE Variable Reg
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3.4 PARSER REGISTER SUMMARY(Address
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Bit R/W Inital Value Mnemonic Descr
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Table 3-64. Frame Ack Control Regis
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3.4.9 WIN_RULE_CTRL3 Address 0x0224
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Table 3-72. Window Rule Control Reg
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Table 3-76. Window Rule Control Reg
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3.5 ACL REGISTER (Address Range: 0x
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Table 3-86. ACL Function Register 4
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SFT&HW RST Table 3-95 summarizes th
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3.5.17 PORT4_VLAN_CTRL1 Address 0x0
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Table 3-103 summarizes the IPv6 Pri
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3.6.1 ATU_DATA0 Address 0x0600 SFT&
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Table 3-110. ATU_FUNC_REG Register
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SFT&HW RST Table 3-140 summarizes t
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Table 3-142. Port 5 Lookup Control
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Table 3-148. Global Trunk Control R
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Table 3-151. Parser Register Summar
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Table 3-151. Parser Register Summar
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Table 3-153, “QM Control Register
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Table 3-159. Port 3 WRR Control Reg
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Table 3-161. Port 5 WRR Control Reg
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Table 3-163. Port 0 Rate Limit Cont
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Table 3-166, “Port 0 Rate Limit C
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3.7.21 PORT1_EG_RATE_CTRL0 Address
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Inital Bit R/W Value Mnemonic Descr
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Table 3-226. Port 1 Flow Control Th
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Bit R/W 15:8 R/O 0 RESERVED Inital
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Table 3-239. ACL_2 Rate Control Reg
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Table 3-248, “ACL_6 Rate Control
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Table 3-257. ACL_11 Rate Control Re
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SFT&HW RST Table 3-267, “ACL_16 R
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Table 3-270. ACL_17 Rate Limit Cont
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Table 3-273. ACL_19 Rate Limit Cont
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3.7.129 ACL_RATE_CTRL1_22 Address 0
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3.7.132 ACL_RATE_CTRL0_24 Address 0
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Table 3-296, “ACL_30 Rate Limit C
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Table 3-301. Port 0 Ingress Rate Li
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SFT&HW RST Table 3-308, “Port 3 I
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Table 3-317, “Port 6 Ingress Rate
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3.8 PKT EDIT REGISTER(Address Range
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Table 3-324. Port 0 Queue Remap Reg
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Table 3-331, “Port 6 Queue Remap
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3.8.14 Router Default VID Register
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Table 3-348. WCMP Next Hop Table 1
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Table 3-353. HNAT Control Register
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3.9.18 NAPT_Used_Account Address 0x
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3.10 PHY Control Registers Table 3-
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Table 3-366. Control Register Bit S
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Bit Symbol Type Description 8 Exten
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Bit Symbol Type Description 14 Ack
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Bit Symbol Type Description 14 Ack
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Table 3-373, “Next Page Transmit
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Bit Symbol Type Description 11 Mast
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Table 3-377. MMD Access Control Reg
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Bit Symbol Type Description 2 SQE T
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Bit Symbol Type Description 14 Spee
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Bit Symbol Type Description 8 False
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Table 3-385. Status Register Bit Sy
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Table 3-389. Debug Port 2 (R/W Port
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Table 3-391. Debug Register — Sys
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3.10.28 Debug Register—Hib Contro
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Bit Symbol Type Description 5 RES M
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Table 3-397. PCS Control1 Bit Symbo
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3.13 MMD7 — Auto-negotiation Regi
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Device Address = 7 Table 3-403 summ
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Table 3-409. EEE Advertisement Bit
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4. Electrical Characteristics 4.1 A
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4.4.12 Power-on-Reset Timing Figure
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4.5.3 GMII Timing Figure 4-4 shows
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4.5.5 SPI Timing Figure 4-6 shows t
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5. Package Dimensions The AR8327 is
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6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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