AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

2.18.4 Automatic Address Learning
Up to 2048 MAC address/port number mappings can be stored in the address table. A three-way hash
algorithm allows a maximum of three different addresses with the same hash key to be stored
simultaneously. The AR8327 searches for the SA of an incoming packet in the address table. If the SA is
not found, the address is hashed and stored in the first empty bin found at the hashed location. If both
address bins are full, each entry’s age time is examined to select the least recently used bin. If the SA is
found, the aging value of the corresponding entry is reset to 0. If the DA is PAUSE, the AR8327
automatically disables the learning process.
2.18.5 Automatic Address Aging
Address aging supports network topology changes such as an end station disconnecting from the
network or an address moving from one port to another. An address is removed (aged-out) from the
address database after a specified amount of time since the last time it appeared in an incoming frame
source address. The AR8327 has a default aging time of 5 minutes, but can be set in 7-second
increments to a maximum of 10,000 minutes.
2.18.6 Broadcast/Multicast Storm Control
If broadcast/multicast storm control is enabled, all broadcast/multicast packets beyond the default
threshold of 10 ms (for 100 Mb operations) and 100 ms (for 10 Mb operations) are discarded. Atheros
Header Configuration
The Atheros header is a two-byte header that the CPU uses to configure the AR8327 switch.
2.18.7 ARL Table
The address database is stored in the embedded SRAM and has a size of 2048 entries with a default
aging time of about 300 seconds or 5 minutes.
Support:
n Search one address in the table
n Use get next read out whole table
n Loading and purging an entry in the ARL table
n Flush entries: all Entries, all Non-static Entries, one port's all Entries, one port's all Non-static
Entries
All registers and counters can be accessed (read and written) through the UART/MDIO interface and
CPU port frames. Interrupts may be asserted upon access completion.
Table 2-32.
Bit Name Description
83:72 VID The VID group indicates which the MAC address belongs to
71 RESERVED
70 COPY_TO_CPU 1’b1: A packet received with this address should be copied to the CPU port
69 REDIRECT_TO_CPU 1’b1: Indicates that a packet received with this address should be redirected to
the CPU port. If no CPU is connected to the switch, this frame should be
discarded.
68 LEAKY_EN 1’b1: Use Leaky VLAN enable for this MAC address. This bit can be used for
Unicast and Multicast frame control by ARL_uni_leaky_en and
ARL_multi_leaky_en
67:64 STATUS 4’h0: Indicates entry is empty
4’h1 ~ 7: indicates entry is dynamic and valid
4’h8 ~ 4’hE: Reserved for future use
4’F: Indicates entry is static and won’t be aged out or changed by the hardware
48 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc.
48 • June 2011 COMPANY CONFIDENTIAL