AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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Table 2-8. MAC Pattern Mask 13:12 VLAN [15:13] PRIORITY MASK [12] CFI MASK [11:0] VID MASK/VID HIGH 15:14 TYPE MASK 16 [7:6] RULE VALID 2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end [5] FRAME WITH TAG MASK 1'b1: consider FRAME_WITH_TAG 1'b0: ignore FRAME_WITH_TAG [4] FRAME_WITH_TAG 1'b1: tagged frame 1'b0: untagged frame [3] VID MASK 1'b1:mask;1'b0:range [2:0] RULE TYPE These three bits must be 3'b001 to indicate the MAC rule. 2.7.4 IPv4 Pattern The action will be taken when the IPv4 Rule is matched. Table 2-9. IPv4 Pattern Byte Name Description 3:0 DIP Destination IP address 7:4 SIP Source IP address 8 IP PROTOCOL IP protocol 9 DSCP DSCP field 11:10 TCP/UDP DESTINATION PORT/ TCP/UDP DESTINATION PORT LOW 13:12 TCP/UDP SOURCE PORT/ TCP/UDP SOURCE PORT LOW OR ICMP TYPE CODE 14 [7] RESERVED [6] DHCPv4 [5] RIPv1 [4]SPORT_FIELD_TYPE [3:0] RESERVED TCP/UDP destination port number or low bound port number. See mask byte 14 bit 1. TCP/UDP source port number or low bound port number. See mask byte 14 bit 0. 1: ICMP TYPE/CODE 0: TCP/UDP SPORT 30 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 30 • June 2011 COMPANY CONFIDENTIAL
Table 2-9. IPv4 Pattern 15 [7:6] RESERVED [5:0] TCP FLAGS 16 [7] RULE RESULT INVERSE EN [6:0] SOURCE PORT Table 2-10. IPv4 Mask Byte Name Description 3:0 DIP MASK 7:4 SIP MASK 8 IP PROTOCOL MASK 9 DSCP MASK 11:10 TCP/UDP DESTINATION PORT MASK/ TCP/UDP DESTINATION PORT HIGH 13:12 TCP/UDP SOURCE PORT MASK/ TCP/UDP SOURCE PORT HIGH OR ICMP TYPE CODE MASK 14 [7] RESERVED [6] DHCPV4 MASK [5] RIPv1 MASK [4:2] RESERVED [1] TCP/UDP DESTINATION MASK [0] TCP/UDP SOURCE MASK This can be mask or high definition. See byte 14, bit 1. This can be mask or high definition. See byte 14, bit 0. Indicates the definition of bytes 11 and 10. 1'b1: mask; 1'b0: range Indicates the definition of bytes 13 and 12. 1'b1: mask; 1'b0: range 15 [7:6] RESERVED [5:0] TCP FLAGS MASK 16 [7:6] RULE VALID 2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end [5:3] RESERVED [2:0] RULE TYPE These three bits must be 3'b010 to indicate the IPv4 rule. Atheros Communications, Inc. Switch • 31 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13 and 14: 1. Pin Descriptions This section co
Page 15 and 16: B 1 A 3 B 19 A 20 A 86 B 76 B 20 A
Page 17 and 18: Table 1-1. Signal to Pin Relationsh
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25 and 26: Table 2-1. Atheros Header Type 5'h1
Page 27 and 28: duplex flow control mode is not set
Page 29: Table 2-6. Action Definition 41 CTA
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37 and 38: 2.9 LED Control There are totally 6
Page 39 and 40: Mode is checking if the ingress VID
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43 and 44: Table 2-29. Application Cases 1 and
Page 45 and 46: Table 2-30. MIB Counters (continued
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66: Table 3-9. Global Interrupt Registe
Page 67 and 68: Table 3-11. Global Interrupt Mask R
Page 69 and 70: Table 3-14 summarizes the MIB Funct
Page 71 and 72: Table 3-17 summarizes the BIST_CTRL
Page 73 and 74: Table 3-21 summerizes LED_CTRL1 Reg
Page 75 and 76: SFT&HW RST Table 3-26 summarizes th
Page 77 and 78: Table 3-28. Port 1 Status Register
Page 79 and 80: Table 3-30. Port 3 Status Register
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Table 3-32. Port 5 Status Register
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Table 3-35. PORT 0 Header Control R
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3.2.36 PORT4_HEADER_CTRL Address 0x
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Table 3-42 summarizes the SGMII_CTR
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3.3 EEE CTRL REGISTER SUMMARY (Addr
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Table 3-48. PORT 2 EEE Variable Reg
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Table 3-54. PORT 4 EEE Variable Reg
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3.4 PARSER REGISTER SUMMARY(Address
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Bit R/W Inital Value Mnemonic Descr
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Table 3-64. Frame Ack Control Regis
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3.4.9 WIN_RULE_CTRL3 Address 0x0224
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Table 3-72. Window Rule Control Reg
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Table 3-76. Window Rule Control Reg
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3.5 ACL REGISTER (Address Range: 0x
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Table 3-86. ACL Function Register 4
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SFT&HW RST Table 3-95 summarizes th
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3.5.17 PORT4_VLAN_CTRL1 Address 0x0
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Table 3-103 summarizes the IPv6 Pri
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3.6.1 ATU_DATA0 Address 0x0600 SFT&
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Table 3-110. ATU_FUNC_REG Register
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SFT&HW RST Table 3-140 summarizes t
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Table 3-142. Port 5 Lookup Control
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Table 3-148. Global Trunk Control R
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Table 3-151. Parser Register Summar
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Table 3-151. Parser Register Summar
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Table 3-153, “QM Control Register
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Table 3-159. Port 3 WRR Control Reg
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Table 3-161. Port 5 WRR Control Reg
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Table 3-163. Port 0 Rate Limit Cont
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Table 3-166, “Port 0 Rate Limit C
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3.7.21 PORT1_EG_RATE_CTRL0 Address
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Inital Bit R/W Value Mnemonic Descr
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Table 3-226. Port 1 Flow Control Th
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Bit R/W 15:8 R/O 0 RESERVED Inital
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Table 3-239. ACL_2 Rate Control Reg
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Table 3-248, “ACL_6 Rate Control
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Table 3-257. ACL_11 Rate Control Re
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SFT&HW RST Table 3-267, “ACL_16 R
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Table 3-270. ACL_17 Rate Limit Cont
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Table 3-273. ACL_19 Rate Limit Cont
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3.7.129 ACL_RATE_CTRL1_22 Address 0
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3.7.132 ACL_RATE_CTRL0_24 Address 0
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Table 3-296, “ACL_30 Rate Limit C
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Table 3-301. Port 0 Ingress Rate Li
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SFT&HW RST Table 3-308, “Port 3 I
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Table 3-317, “Port 6 Ingress Rate
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3.8 PKT EDIT REGISTER(Address Range
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Table 3-324. Port 0 Queue Remap Reg
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Table 3-331, “Port 6 Queue Remap
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3.8.14 Router Default VID Register
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Table 3-348. WCMP Next Hop Table 1
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Table 3-353. HNAT Control Register
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3.9.18 NAPT_Used_Account Address 0x
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3.10 PHY Control Registers Table 3-
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Table 3-366. Control Register Bit S
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Bit Symbol Type Description 8 Exten
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Bit Symbol Type Description 14 Ack
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Bit Symbol Type Description 14 Ack
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Table 3-373, “Next Page Transmit
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Bit Symbol Type Description 11 Mast
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Table 3-377. MMD Access Control Reg
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Bit Symbol Type Description 2 SQE T
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Bit Symbol Type Description 14 Spee
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Bit Symbol Type Description 8 False
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Table 3-385. Status Register Bit Sy
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Table 3-389. Debug Port 2 (R/W Port
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Table 3-391. Debug Register — Sys
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3.10.28 Debug Register—Hib Contro
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Bit Symbol Type Description 5 RES M
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Table 3-397. PCS Control1 Bit Symbo
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3.13 MMD7 — Auto-negotiation Regi
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Device Address = 7 Table 3-403 summ
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Table 3-409. EEE Advertisement Bit
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4. Electrical Characteristics 4.1 A
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4.4.12 Power-on-Reset Timing Figure
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4.5.3 GMII Timing Figure 4-4 shows
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4.5.5 SPI Timing Figure 4-6 shows t
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5. Package Dimensions The AR8327 is
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6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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