AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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2.4 Header for Read/Write Register. The AR8327 supports the read/write register through the Atheros Header. The figure is the frame format of the read/write register command. 8 byte 4 byte 2 byte 4 byte 2.6.2 Half-Duplex Flow Control Half-duplex flow control regulates the remote station to avoid dropping packets in network congestion. Back pressure is supported for half-duplex operations. When the free buffer space is almost empty, the AR8327 device transmits a jam pattern on the port and forces a collision. If the half- command data header data padding crc Data: 0~16byte Table 2-4. Command Format for Read/Write Register using Atheros Header Bit Name Description 18:0 ADDR The starting register address for the read/write command. The address must be boundary of word address. 23:20 LENGTH The data length for read/write register. Maximum 16 bytes. 28 CMD 1'b0: write 1'b1: read 31:29 CHECK_CODE Must be 3'b101. otherwise the command would be ignored. 63:32 SEQ_NUM The Sequence number can be checked by CPU. 2.5 Media Access Controllers (MAC) The AR8327 integrates seven independent GB Ethernet MACs that perform all functions in the IEEE 802.3 specifications, for example, frame formatting, frame stripping, CRC checking, CSMA/CD, collision handling, and back-pressure flow control. Each MAC supports 10 Mbps, 100 Mbps, or 1000 Mbps operation in either full-duplex or half-duplex mode 2.6 Port Status Configuration The AR8327 supports flexible port status configuration on a group or per-port basis. Each port has status registers that provide information about the port interface. The first port (port 0) MAC behaves as a PHY to allow a direct connection to an external MAC (e.g. a management CPU or a MAC inside a router). In this mode, the AR8327 drives interface clocks from a CLK pin at the desired frequency. Only full-duplex modes are supported and need to match the mode of the link partner's MAC. The second RGMII interface supports a PHY interface as a WAN port. 2.6.1 Full-Duplex Flow Control The AR8327 device supports IEEE 802.3x full-duplex flow control, force-mode full-duplex flow control, and half-duplex backpressure. If the link partner supports auto-negotiation, the 802.3x full-duplex flow control is auto-negotiated between the remote node and the AR8327. If the full-duplex flow control is enabled, when the free buffer space is almost empty, the AR8327 sends out an IEEE 802.3x compliant PAUSE to stop the remote device from sending more frames. 26 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 26 • June 2011 COMPANY CONFIDENTIAL
duplex flow control mode is not set, the incoming packet is dropped if there is no buffer space available. 2.6.3 Inter-Packet Gap (IPG) The IPG is the idle time between any to successive packets from the same port. The typical IPG is 9.6 µs for 10 Mbps Ethernet and 960 ns for 100 Mbps Ethernet. 2.6.4 Illegal Frames The AR8327 discards all illegal frames such as CRC error, oversized packets (length greater than maximum length), and runt packets (length less than 64 bytes). 2.7 ACL The AR8327 supports up to 96 ACL rule table entries. Each rule can support filtering or re-direction of the incoming packets based on the following field in the packet. n Source MAC address n Destination MAC address n VID n EtherType n Source IP address n Destination IP address n Protocol n Source TCP/UDP port number n Destination TCP/UDP port number n Physical Port number When the incoming packets match an entry in the rules table, the following action can be taken defined in the result field. n Change VID field n Drop the packet n change VID n change priority The AR8327/AR8327N can bind up to 4 rules to support 16*4 bytes keys and support up to 2 matches per packet to support different functions such as ACL+Qos, ACL+routing, etc. 2.7.1 ACL Rule The ACL rule is constructed from a packet patters, pattern mask and action. The pattern can be defined as MAC layer or Layer 3 (IPv4 or IPv6) or user defined window. The ACL pattern types supported by the AR8327 are listed in Table 2-5. Table 2-5. PatternTypes Value Description 1 MAC Pattern 2 IPV4 Pattern 3 IPV6 Pattern 1 4 IPV6 Pattern 2 5 IPV6 Pattern 3 6 WINDOW Pattern Atheros Communications, Inc. Switch • 27 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13 and 14: 1. Pin Descriptions This section co
Page 15 and 16: B 1 A 3 B 19 A 20 A 86 B 76 B 20 A
Page 17 and 18: Table 1-1. Signal to Pin Relationsh
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25: Table 2-1. Atheros Header Type 5'h1
Page 29 and 30: Table 2-6. Action Definition 41 CTA
Page 31 and 32: Table 2-9. IPv4 Pattern 15 [7:6] RE
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37 and 38: 2.9 LED Control There are totally 6
Page 39 and 40: Mode is checking if the ingress VID
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43 and 44: Table 2-29. Application Cases 1 and
Page 45 and 46: Table 2-30. MIB Counters (continued
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66: Table 3-9. Global Interrupt Registe
Page 67 and 68: Table 3-11. Global Interrupt Mask R
Page 69 and 70: Table 3-14 summarizes the MIB Funct
Page 71 and 72: Table 3-17 summarizes the BIST_CTRL
Page 73 and 74: Table 3-21 summerizes LED_CTRL1 Reg
Page 75 and 76: SFT&HW RST Table 3-26 summarizes th
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Table 3-28. Port 1 Status Register
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Table 3-35. PORT 0 Header Control R
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3.2.36 PORT4_HEADER_CTRL Address 0x
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Table 3-42 summarizes the SGMII_CTR
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3.3 EEE CTRL REGISTER SUMMARY (Addr
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Table 3-48. PORT 2 EEE Variable Reg
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Table 3-54. PORT 4 EEE Variable Reg
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3.4 PARSER REGISTER SUMMARY(Address
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Bit R/W Inital Value Mnemonic Descr
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Table 3-64. Frame Ack Control Regis
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3.4.9 WIN_RULE_CTRL3 Address 0x0224
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Table 3-72. Window Rule Control Reg
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Table 3-76. Window Rule Control Reg
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3.5 ACL REGISTER (Address Range: 0x
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Table 3-86. ACL Function Register 4
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SFT&HW RST Table 3-95 summarizes th
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3.5.17 PORT4_VLAN_CTRL1 Address 0x0
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Table 3-103 summarizes the IPv6 Pri
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3.6.1 ATU_DATA0 Address 0x0600 SFT&
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Table 3-110. ATU_FUNC_REG Register
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SFT&HW RST Table 3-140 summarizes t
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Table 3-142. Port 5 Lookup Control
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Table 3-148. Global Trunk Control R
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Table 3-151. Parser Register Summar
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Table 3-151. Parser Register Summar
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Table 3-153, “QM Control Register
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Table 3-159. Port 3 WRR Control Reg
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Table 3-161. Port 5 WRR Control Reg
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Table 3-163. Port 0 Rate Limit Cont
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Table 3-166, “Port 0 Rate Limit C
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3.7.21 PORT1_EG_RATE_CTRL0 Address
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Inital Bit R/W Value Mnemonic Descr
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Table 3-226. Port 1 Flow Control Th
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Bit R/W 15:8 R/O 0 RESERVED Inital
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Table 3-239. ACL_2 Rate Control Reg
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Table 3-248, “ACL_6 Rate Control
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Table 3-257. ACL_11 Rate Control Re
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SFT&HW RST Table 3-267, “ACL_16 R
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Table 3-270. ACL_17 Rate Limit Cont
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Table 3-273. ACL_19 Rate Limit Cont
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3.7.129 ACL_RATE_CTRL1_22 Address 0
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3.7.132 ACL_RATE_CTRL0_24 Address 0
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Table 3-296, “ACL_30 Rate Limit C
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Table 3-301. Port 0 Ingress Rate Li
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SFT&HW RST Table 3-308, “Port 3 I
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Table 3-317, “Port 6 Ingress Rate
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3.8 PKT EDIT REGISTER(Address Range
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Table 3-324. Port 0 Queue Remap Reg
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Table 3-331, “Port 6 Queue Remap
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3.8.14 Router Default VID Register
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Table 3-348. WCMP Next Hop Table 1
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Table 3-353. HNAT Control Register
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3.9.18 NAPT_Used_Account Address 0x
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3.10 PHY Control Registers Table 3-
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Table 3-366. Control Register Bit S
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Bit Symbol Type Description 8 Exten
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Bit Symbol Type Description 14 Ack
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Bit Symbol Type Description 14 Ack
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Table 3-373, “Next Page Transmit
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Bit Symbol Type Description 11 Mast
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Table 3-377. MMD Access Control Reg
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Bit Symbol Type Description 2 SQE T
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Bit Symbol Type Description 14 Spee
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Bit Symbol Type Description 8 False
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Table 3-385. Status Register Bit Sy
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Table 3-389. Debug Port 2 (R/W Port
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Table 3-391. Debug Register — Sys
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3.10.28 Debug Register—Hib Contro
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Bit Symbol Type Description 5 RES M
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Table 3-397. PCS Control1 Bit Symbo
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3.13 MMD7 — Auto-negotiation Regi
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Device Address = 7 Table 3-403 summ
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Table 3-409. EEE Advertisement Bit
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4. Electrical Characteristics 4.1 A
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4.4.12 Power-on-Reset Timing Figure
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4.5.3 GMII Timing Figure 4-4 shows
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4.5.5 SPI Timing Figure 4-6 shows t
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5. Package Dimensions The AR8327 is
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6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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