AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

Table 2-20. Enhanced MAC Pattern Mask
14:13 TYPE MASK
15 Reserved
16 [7:6] RULE VALID 2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end
[5] FRAME WITH CTAG
MASK
[4]
FRAME_WITH_CTAG
1'b1: consider FRAME_WITH_CTAG
1'b0: ignore FRAME_WITH_CTAG
1'b1: frame with CTAG
1'b0: frame without CTAG
[3] CVID MASK 1'b1:mask;1'b0:range
[2:0] RULE TYPE These three bits must be 3'b111 to indicate the Enhanced MAC Rule.
2.8 Register Access
The MDIO interface allows users to access the Switch internal registers and MII registers. The figure
shown below is the format to access MII registers in the embedded PHY. The PHY address is from
0x00 up to 0x04. The Op code “10” indicates the read command and “01” is the write command.
The Switch internal registers are 32-bits wide, but the MDIO access is only 16-bits wide. So it needs 2
times access to complete the internal registers access. Moreover the address spacing is more than 10
bits supported by MDIO, So it needs to write the upper address bits to internal registers, like page
mode access method. For example, the register address bit 18 to 9 are treated as page address and will
be written out first as High_addr[9:0], refer the Table 1 below. Then the register could be accessed via
Tables 2, where Low_addr[7:1] is the address bit [8:2] of register and Low_add[0] is 0 for Data[15:0] or
Low_addr[0] is 1 for Data[31:16].
1. First, write high-address command.
Where High_Addr[9:0] is address[18:9] for register, as follows:
2. Second, read/write 32 bit register data
command.
Table 2: where Low_Addr[7:1] is address [8:2] of register and Low_Addr[0] is 0 for Data[15:0], 1 for
Data[31:16]
TA
start Op 2'b10 Low_addr[7:0]
[1:0]
Data[15:0]
36 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc.
36 • June 2011 COMPANY CONFIDENTIAL