AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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Table 2-30. MIB Counters (continued) Counter Width Offset Description Rx1024Byte 32bit 0x2C The number of frames received whose length is between 512 and 1023 bytes, including those with errors Rx1518Byte 32bit 0x30 The number of frames received whose length is between 1024 and 1518 bytes, including those with errors RxMaxByte 32bit 0x34 The number of frames received whose length is between 1519 and maxlength, including those with errors (Jumbo) RxTooLong 32bit 0x38 The number of frames received whose length exceeds maxlength including those with FCS errors RxGoodByte 64bit 0x3C:0x40 Total data octets received in a frame with a valid FCS. All frame sizes are included. RXBadByte 64bit 0x44:0x48 Total data octets received in frame with and invalid FCS. All frame sizes are included. Pause frame is included with a valid FCS RxOverFlow 32bit 0x4C Total valid frames received that are discarded due to lack of buffer space Filtered 32bit 0x50 Port disabled and unknown VID TxBroad 32bit 0x54 Total good frames transmitted with a broadcast Destination address TxPause 32bit 0x58 Total good PAUSE frames transmitted TxMulti 32bit 0x5C Total good frames transmitted with a multicast Destination address TxUnderRun 32bit 0x60 Total valid frames discarded that were not transmitted due to transmit FIFO buffer underflow Tx64Byte 32bit 0x64 Total frames transmitted with a length of exactly 64 bytes, including errors Tx128Byte 32bit 0x68 Total frames transmitted with a length between 65 and 127 bytes, including those with errors Tx256Byte 32bit 0x6C Total frames truncated with a length between 128 and 255 bytes, including those with errors Tx512Byte 32bit 0x70 Total frames truncated with a length between 256 and 511 bytes, including those with errors Tx1024Byte 32bit 0x74 Total frames truncated with a length between 512 and 1023 bytes, including those with errors Tx1518Byte 32bit 0x78 Total frames transmitted with length between 1024 and 1518, including those with errors (Jumbo) TxMaxByte 32bit 0x7C Total frames transmitted with length between 1519 and Maxlength, including those with errors (Jumbo) TxOverSize 32bit 0x80 Total frames over Maxlength but transmitted truncated with bad FCS TxByte 64bit 0x84:0x88 Total data octets transmitted from counted, including those with a bad FCS TxCollision 32bit 0x8C Total collisions experienced by a port during packet transmission TxAbortCol 32bit 0x90 Total number of frames not transmitted because the frame experienced 16 transmission attempts and was discarded TxMultiCol 32bit 0x94 Total number of successfully transmitted frames that experienced more than one collision 44 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 44 • June 2011 COMPANY CONFIDENTIAL
Table 2-30. MIB Counters (continued) Counter Width Offset Description TxSingleCol 32bit 0x98 Total number of successfully transmitted frames that experienced exactly one collision TxExcDefer 32bit 0x9C The number of frames that deferred for an excessive period of time TxDefer 32bit 0xA0 Total frames whose transmission was delayed on its first attempt because the medium way was busy TXLateCol 32bit 0xA4 Total number of times a collision is detected later than 512 bit-times into the transmission of a frame 2.13 Quality of Service (QoS) The AR8327 supports six queues (MAC0, MAC5, and MAC6) or four queues (MAC1 ~ MAC4). This egress queue schedule mechanism can be configured to one of the following modes: Table 2-31. Mode Description Strict Priority (SP) Any packets residing in the higher priority queues transmit first. Lower priority packets transmit once these queues are emptied. Weighted Fair Queuing Each queue is assigned a weight that determines how many packets are sent from each priority queue. Mix Mode The highest one or two priority queues use SP and other queues conform to WRR The AR8327 recognizes the QoS information of ingress frames and map to different egress priority levels. The AR8327 determines the priority of the frames based on DA, TOS/TC, VLAN, and port. Each has an enable bit that can be applied. When more than one type of priority is selected, the order in which the frame priority should be applied can be determined. Priority enable bits and select order bits are set on a by port basis at the port’s base address. Priority Determined DA TOS/TC VLAN Description Set DA_PRI_EN bit [18] to 1’b1 and add the address to the ARL table-set priority_over_en to 1’b1. ARL priority bits [59:58] can be used as DA priority. Set IP_PRI_EN bit [16] to 1’b1, and set the IP priority mapping register (0x60–0x6C). Set VLAN_PRI_EN (bit [17]) to 1’b1, and set the TAG priority mapping register (0x70). When more than one priority enable bit is set to 1’b1. (DA_PRI_SEL, IP_PRI_SEL, VLAN_PRI_SEL) can determine the order in which the frame priority should be applied. If *_PRI_SEL is set to 2’b0, frame priority is determined by that first. Otherwise, priority is determined by which *_PRI_SEL is set to 2’b01, then 2’b10, 2’b11, etc. Atheros Communications, Inc. Switch • 45 AR8327/AR8327N Seven-port Gigabit Ethernet
Page 1 and 2: AR8327/AR8327N Seven-port Gigabit E
Page 3 and 4: Table of Contents General Descripti
Page 5 and 6: 3.5.17 PORT4_VLAN_CTRL1 ...........
Page 7 and 8: 3.7.121 ACL_RATE_CTRL0_18 .........
Page 9 and 10: 6 Ordering Information ............
Page 11 and 12: Revision History Table 0-1. AR8161-
Page 13 and 14: 1. Pin Descriptions This section co
Page 15 and 16: B 1 A 3 B 19 A 20 A 86 B 76 B 20 A
Page 17 and 18: Table 1-1. Signal to Pin Relationsh
Page 19 and 20: Table 1-1. Signal to Pin Relationsh
Page 21 and 22: Table 1-2. Interface Summary for MA
Page 23 and 24: 2. Functional Description The AR832
Page 25 and 26: Table 2-1. Atheros Header Type 5'h1
Page 27 and 28: duplex flow control mode is not set
Page 29 and 30: Table 2-6. Action Definition 41 CTA
Page 31 and 32: Table 2-9. IPv4 Pattern 15 [7:6] RE
Page 33 and 34: Table 2-13. IPv6 Pattern — Patter
Page 35 and 36: 2.7.7 Enhanced MAC Pattern Table 2-
Page 37 and 38: 2.9 LED Control There are totally 6
Page 39 and 40: Mode is checking if the ingress VID
Page 41 and 42: 2.10.9 VLAN Table The AR8327 suppor
Page 43: Table 2-29. Application Cases 1 and
Page 47 and 48: 2.17.3 Forwarding Unknown The AR832
Page 49 and 50: Table 2-32. Bit Name Description 63
Page 51 and 52: Table 2-34. Basic NAT Table 73:72 A
Page 53 and 54: 2.19.4 ARP ENTRY The HNAT module su
Page 55 and 56: 2.21 Memory Map Table 2-38. Memory
Page 57 and 58: 3. Register Descriptions Table 3-1
Page 59 and 60: 3.2.1 MASK_CTRL Address: 0x0000 HW
Page 61 and 62: Table 3-6 summarizes the PORT5 PAD
Page 63 and 64: Table 3-7. PORT6 PAD MODE CTRL Regi
Page 65 and 66: Table 3-9. Global Interrupt Registe
Page 67 and 68: Table 3-11. Global Interrupt Mask R
Page 69 and 70: Table 3-14 summarizes the MIB Funct
Page 71 and 72: Table 3-17 summarizes the BIST_CTRL
Page 73 and 74: Table 3-21 summerizes LED_CTRL1 Reg
Page 75 and 76: SFT&HW RST Table 3-26 summarizes th
Page 77 and 78: Table 3-28. Port 1 Status Register
Page 83 and 84: Table 3-35. PORT 0 Header Control R
Page 85 and 86: 3.2.36 PORT4_HEADER_CTRL Address 0x
Page 87 and 88: Table 3-42 summarizes the SGMII_CTR
Page 89 and 90: 3.3 EEE CTRL REGISTER SUMMARY (Addr
Page 91 and 92: Table 3-48. PORT 2 EEE Variable Reg
Page 93 and 94: Table 3-54. PORT 4 EEE Variable Reg
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3.4 PARSER REGISTER SUMMARY(Address
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Bit R/W Inital Value Mnemonic Descr
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Table 3-64. Frame Ack Control Regis
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3.4.9 WIN_RULE_CTRL3 Address 0x0224
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Table 3-72. Window Rule Control Reg
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Table 3-76. Window Rule Control Reg
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3.5 ACL REGISTER (Address Range: 0x
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Table 3-86. ACL Function Register 4
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SFT&HW RST Table 3-95 summarizes th
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3.5.17 PORT4_VLAN_CTRL1 Address 0x0
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Table 3-103 summarizes the IPv6 Pri
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3.6.1 ATU_DATA0 Address 0x0600 SFT&
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Table 3-110. ATU_FUNC_REG Register
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SFT&HW RST Table 3-140 summarizes t
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Table 3-142. Port 5 Lookup Control
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Table 3-148. Global Trunk Control R
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Table 3-151. Parser Register Summar
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Table 3-151. Parser Register Summar
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Table 3-153, “QM Control Register
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Table 3-159. Port 3 WRR Control Reg
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Table 3-161. Port 5 WRR Control Reg
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Table 3-163. Port 0 Rate Limit Cont
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Table 3-166, “Port 0 Rate Limit C
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3.7.21 PORT1_EG_RATE_CTRL0 Address
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Inital Bit R/W Value Mnemonic Descr
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Table 3-226. Port 1 Flow Control Th
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Bit R/W 15:8 R/O 0 RESERVED Inital
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Table 3-239. ACL_2 Rate Control Reg
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Table 3-248, “ACL_6 Rate Control
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Table 3-257. ACL_11 Rate Control Re
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SFT&HW RST Table 3-267, “ACL_16 R
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Table 3-270. ACL_17 Rate Limit Cont
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Table 3-273. ACL_19 Rate Limit Cont
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3.7.129 ACL_RATE_CTRL1_22 Address 0
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3.7.132 ACL_RATE_CTRL0_24 Address 0
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Table 3-296, “ACL_30 Rate Limit C
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Table 3-301. Port 0 Ingress Rate Li
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SFT&HW RST Table 3-308, “Port 3 I
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Table 3-317, “Port 6 Ingress Rate
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3.8 PKT EDIT REGISTER(Address Range
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Table 3-324. Port 0 Queue Remap Reg
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Table 3-331, “Port 6 Queue Remap
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3.8.14 Router Default VID Register
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Table 3-348. WCMP Next Hop Table 1
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Table 3-353. HNAT Control Register
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3.9.18 NAPT_Used_Account Address 0x
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3.10 PHY Control Registers Table 3-
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Table 3-366. Control Register Bit S
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Bit Symbol Type Description 8 Exten
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Bit Symbol Type Description 14 Ack
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Bit Symbol Type Description 14 Ack
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Table 3-373, “Next Page Transmit
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Bit Symbol Type Description 11 Mast
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Table 3-377. MMD Access Control Reg
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Bit Symbol Type Description 2 SQE T
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Bit Symbol Type Description 14 Spee
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Bit Symbol Type Description 8 False
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Table 3-385. Status Register Bit Sy
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Table 3-389. Debug Port 2 (R/W Port
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Table 3-391. Debug Register — Sys
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3.10.28 Debug Register—Hib Contro
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Bit Symbol Type Description 5 RES M
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Table 3-397. PCS Control1 Bit Symbo
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3.13 MMD7 — Auto-negotiation Regi
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Device Address = 7 Table 3-403 summ
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Table 3-409. EEE Advertisement Bit
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4. Electrical Characteristics 4.1 A
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4.4.12 Power-on-Reset Timing Figure
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4.5.3 GMII Timing Figure 4-4 shows
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4.5.5 SPI Timing Figure 4-6 shows t
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5. Package Dimensions The AR8327 is
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6. Ordering Information The orderin
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AR8327/AR8327N Seven-port Gigabit Ethernet Switch - La Fibre

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