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Layout for matching: Use of dummies• DummiesUse dummy devices to provide the same contour conditions. Ground dummies (do not let them float) Dummies can be full (shorted) devices, or part of them Beware of their parasitics!Layout for matching: Use of dummies• Reference cellUse multiple basic transistors instead of different sizes Same W, same orientation,
Design of large area components• MOS TransistorsMultiple gates to minimizeserial resistanceMultiple contacts to minimizeserial resistance No big contacts!!!“stacked” structures Lower parasitic capacitances Lower areaAnalogue applications Avoid minimum sizeAutomatically generated layoutsAMS, 0.35 microns, 10/0.35Design of large area components• ResistancesBended structuresDummy structures45 degrees (avoid nonlaminar current flow)Contacts Current in the samedirection Multiple contactsPiezoresistive effectResistor: 5K, 275x3 sq microns.Example of “good” and “bad” layout
Page 3 and 4: Layouts• Digital logic: automatic
Page 5 and 6: Designing a layout: CAD Tools• La
Page 7 and 8: Lithography• Example: which is th
Page 9 and 10: Lithography• 436 nm: used down to
Page 11 and 12: Differences between layout and Circ
Page 13 and 14: Differences between layout and Circ
Page 15 and 16: Corrections performed by the foundr
Page 17 and 18: Example of design rules for POLY 1
Page 19 and 20: Layout for matching• Devices with
Page 21: Layout for matching: Common centroi
Page 25 and 26: Layout Strategies for circuit relia
Page 27 and 28: Layout for reliability: Latch-up•
Page 29 and 30: Layout for reliability: CMP2µ 2µ5
Page 31 and 32: Layout for reliability: CMPProposal
Page 33 and 34: Layout for reliability: Antenna•
Page 35: References• The art of Analog Lay

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