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Layout Strategies for circuit reliability (III)• CMP Chemical MechanicalPolishing or ChemicalMechanical Planarization Removal any irregulartopography Surface within the depthof field of aphotolithography system.Layout for reliability: CMP• Example: MOSIS 0.25(TSMC)• Design rules:Minimum % coverage ofMetal layersPolysilicon layersCapacitor Layers
Layout for reliability: CMP2µ 2µ5µDummy patterns are distributedover the chip as uniformly aspossible in order to reach therequired coverage for eachmaterial (Metal 1, 2, 3, 4, 5, Poly 1and CTM (capacitor top metal) )All Metal Fill pattern(staked M1, M2, M3, M4 )Poly 1 Fill pattern asmetalLayout for reliability: CMP1. Orientation of dummy pattern should be perpendicular toprevious layer2. Top layer should have larger dummy patternExample: 4-metal technologyPattern for M1Pattern for M2 Pattern for M3 Pattern for M4 (top)
Page 3 and 4: Layouts• Digital logic: automatic
Page 5 and 6: Designing a layout: CAD Tools• La
Page 7 and 8: Lithography• Example: which is th
Page 9 and 10: Lithography• 436 nm: used down to
Page 11 and 12: Differences between layout and Circ
Page 13 and 14: Differences between layout and Circ
Page 15 and 16: Corrections performed by the foundr
Page 17 and 18: Example of design rules for POLY 1
Page 19 and 20: Layout for matching• Devices with
Page 21 and 22: Layout for matching: Common centroi
Page 23 and 24: Design of large area components•
Page 25 and 26: Layout Strategies for circuit relia
Page 27: Layout for reliability: Latch-up•
Page 31 and 32: Layout for reliability: CMPProposal
Page 33 and 34: Layout for reliability: Antenna•
Page 35: References• The art of Analog Lay

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