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Layout for reliability: CMP• Patterns generated automatically by the foundry• User has masks to define areas that will NOT be filled with patterns(Ex: inductors, capacitors, test strcutures, etc)Example in a 0,18 µm technology:Layout for reliability: CMPExample of Transmission line inM7 with dummy metals below :Open question: How do dummymetal fills affect transmission linesand passives ?“A Bidirectional- and Multi-Drop-Transmission-Line Interconnect…”,IEEE JSSC April 2008
Layout for reliability: CMPProposal: slow-wave transmission lines-Low Q- Small area- Necessary grid fulfills metal coverageBorremans et al., “VCO design for 60 GHz applications usingdifferential shielded inductors in 0.13 µm CMOS”, RFIC’08Layout for reliability: CMP• Slots Act both as stressreleasers and tominimize dishing Slots in metals W>Value (tech. dependent) Possible library ofcomponents Corners Padsdishing
Page 3 and 4: Layouts• Digital logic: automatic
Page 5 and 6: Designing a layout: CAD Tools• La
Page 7 and 8: Lithography• Example: which is th
Page 9 and 10: Lithography• 436 nm: used down to
Page 11 and 12: Differences between layout and Circ
Page 13 and 14: Differences between layout and Circ
Page 15 and 16: Corrections performed by the foundr
Page 17 and 18: Example of design rules for POLY 1
Page 19 and 20: Layout for matching• Devices with
Page 21 and 22: Layout for matching: Common centroi
Page 23 and 24: Design of large area components•
Page 25 and 26: Layout Strategies for circuit relia
Page 27 and 28: Layout for reliability: Latch-up•
Page 29: Layout for reliability: CMP2µ 2µ5
Page 33 and 34: Layout for reliability: Antenna•
Page 35: References• The art of Analog Lay

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