Microcomputer Unit - Index of

-----------------------------------------------------HD6801S0,HD6801S5• AC CHARACTERISTICSBUS TIMING (Vee = 5.0V±5%, Vss '"' OV, Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test ConditionHDS801S0 HDS801S5min typ max min typ maxCycle Time tCYC 1 - 10 0.8 - 10 /J.sAddress Strobe Pulse Width "High" PWASH 200 - - 150 - - nsAddress Strobe Rise Time tASr 5 - 50 5 - 50 nsAddress Strobe Fall Time tASf 5 - 50 5 - 50 nsAddress Strobe Delay Time tASO SO - - 30 - - nsEnable Rise Time ' ter 5 - 50 5 - 50 nsEnable Fall Time tEf 5 - 50 5 - 50 nsEnable Pulse Width "High" Time PW EH 450 - - 340 - - nsEnable Pulse Width "Low" Time PWEL 450 - - 350 - - nsAddress Strobe to Enable.Delay Time tASEO SO - - 30 - - nsAddress Delay Time tAD Fig. 1 - - 250 - - 260 nsAddress Delay Time for Latch (f = 1.0MHz) tAOL Fig. 2 - - 270 - - 260 nsData Set-up Write Time tosw 225 - - 115 - - nsData Set-up Read Time tOSR 80 - - 70 - - nsData Hold Time l Read tHR 10 - - 10 - - nsI Write tHW 20 - - 20 - -Address Set-up Time for Latch tASL 60 - - 50 - - nsAddress Hold Time for Latch tAHL 20 - - 20 - - nsAddress Hold Time tAH 20 - - 20 - - nsPeripheral Read I Non-Multiplexed Bus (tACCN) - - (510) - - (420)nsAccess TimeI Multiplexed Bus (tACCM) - - (600) - - (420)Oscillator stabilization Time tRC Fig. 10 100 - - 100 - - msProcessor Control Set-up Time tpcs Fig. 11 200 - - 200 - - nsUnitPERIPHERAL PORT TIMING (Vee = 5.0V ±S%, Vss = OV. Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitPeripheral Data Setup Time Port 1, 2,3,4 tpDSU Fig. 3 200 - - nsPeripheral Data Hold Time Port 1,2,3,4 tpDH Fig. 3 200 - - nsDelay Time, Enable Positive Transitionto 053 Negative TransitionDelay Time, Enable Positive Transitionto 053 Positive TransitiontOS01 Fig. 5 - - 350 nstOSD2 Fig. 5 - - 350 nsDelay Time, Enable NegativeTransition to Peripheral Data Port 1, 2*,3,4 tpwD Fig. 4 - - 400 nsValidDelay Time, Enable Negative*Transition to Peripheral Port 2**, 4 tCMOS Fig. 4 - - 2.0 lASCMOS Data ValidInput Strobe Pulse Width tpWIS Fig. 6 200 - - nsInput Data Hold Time port 3 tlH Fig. 6 50 - - nsInput Data Set-up Time Port 3 tIS Fig. 6 20 - - ns**'Okn pull up register required for Port 2~HITACHI 43