Microcomputer Unit - Index of

8-BIT SINGLE-CHIPMICROCOMPUTER DATABOOK$HITACHI

When using this manual. the reader should keep the following in mind:1. This manual may, wholly or partially. be subject to change without notice.2. All rights reserved: No one is permitted to reproduce or duplicate. in anyform. the whole or part of this manual without Hitachi's permission.3. Hitachi will not be responsible for any damage to the user that may resultfrom accidents or any other reasons during operation of his unit accordingto this manual.4. This manual neither ensures the enforcement of any industrial propertiesor other rights. nor sanctions the enforcement right thereof.

HD630SYOHD63AOSYOHD63BOSYOijD630SYIHD63AOSYIHD63BOSYIHD630SY2HD63AOSY2HD63BOSY2HD63LOSFIHD63LOSEOHD68POIV07HD68POIV07-1HD68POIMOHD68POIMO-IHD68POSV07HD68POSWOHD63POIMIHD63PAOIMIHD63PBOIMIHD63POSYOHD63PAOSYOHD63PBOSYOHD63701XOMicrocomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 451Microcomputer Unit (CMOS) .................................................... 451Microcomputer Unit (CMOS) .........................•.......................... 451Microcomputer Unit (CMOS) ... . . . . . ............................................ 478Microcomputer Unit (CMOS) .................................................... 478Microcomputer Unit (CMOS) .................................................... 478Microcomputer Unit (CMOS) .................................................... 478Microcomputer Unit (CMOS) .................................................... 478Microcomputer Unit (CMOS) .................................................... 478Microcomputer Unit (CMOS) .................................................... 507Evaluation Chip for HD63LOSFI (CMOS) ............................................ 538Microcomputer Unit (NMOS) .................................................... 540Microcomputer Unit (NMOS) .................................................... 540Microcomputer Unit (NMOS) .................................................... 540Microcomputer Unit (NMOS) .................................................... S40Microcomputer Unit (NMOS) .................................................... 579Microcomputer Unit (NMOS) .................................................... 601Microcomputer Unit (CMOS) .................................................... 630Microcomputer Unit (CMOS) .................................................... 630Microcomputer Unit (CMOS) ..................................................... 630Microcomputer Unit (CMOS) ....................... '.' ........................... 668Microcomputer Unit (CMOS) .................................................... 668Microcomputer Unit (CMOS) ..................................................... 668Microcomputer Unit (CMOS) .................................................... 670• INTRODUCTION OF RELATED DEVICES• 8/16-bit MuIti-chip Microcomputers, ......................................................... 675• 4-bit Single-chip Microcomputer HMCS400 Series ............................ " ..................... 677• 4-bit Single-chip Microcomputer HMCS40 Series ., ...............................•................ 678• LCD Driver Series ......................................... , ..........•.................. 680• IC Memories .......................................................................... 682• Gate Array ..................................................................... ...... 685• LSI for Speech Synthesizer System ................................ , .......................... 687• CODEC/Filter Combo LSI ................................................... '.' ............ 690• HITACHI SALES OFFICE LOCATIONS ..•....•.....•..•....•...•.•..••.•••.••....•...•..•.•.••..•.....•. 692_HITACHI

QUICK REFERENCE GUIDE• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6801 SERIESType No.Bus Timing (MHz)LSISupply Voltage (V)Characteristics Operating Temperature * tC)Package tROM (k byte)MemoryRAM (byte)I/O PortExternalSoftInterruptTimerFunctionsSeria.1TimerSCIExternal Memory ExpansionClock Pulse GeneratorBuilt-in RAM HoldingEPROM on the Package Type**CompatibilityHD6801S0 HD6801VO HD6803HD6801S5 HD6801V5 HD6803·11.011.25 1.0/1.25 1.011.255.0 5.0 5.00-+70 o -+70 0-+70DP·40 DP·40 DP-402 4 -128 128 12829 29 132 2 21 1 13 3 31 1 1• Free running counter 16-bit x 1• Output compare register 16-bit x 1• Input capture register 16-bit x 1Full double step-stop type• Address/data non-multiple mode(256 bytes)• Address/data multiple mode(65k bytes)HD68P01V07HD68P01V07-1MC6801MC680l-lBuilt-in (External clock useable)Yes (64 bytes)HD68P(J1V07HD68P01V07-1-• Address/datamultiple mode(65k bytes)-MC6803MC6803-l• Wide Temperature Range (-40 - +85°C) version is available .•• HD68P01MO useable.t DP; Plastic DIP_HITACHI 7

QUICK REFERENCE GUIDE----------------------------• NMOS 8·BIT SINGLE·CHIP MICROCOMPUTER HD6805 SERIESLSICharacteristicsType No.Clock Frequency (MHz)Supply Voltage (V)Operating Temperature *** ( DC)HD6805S11.05.250-+70HD6805S6*HD6805Ul1.0 1.05.25 5.250-+70 0-+10Package tROM (k byte)MemoryRAM (byte)1/0 Port110 Port Input PortOutput PortNestingExternalInterrupt SoftTimerSerialDP·281.1642020 --6111-DP-28DP·401.8 264 9620 2420 - 32 8- -6 61 11 11 1- -FunctionsTimer• 8-bit timer with 7-bit prescaler• Event counterSCI-- -Clock Pulse Generator• Resistor• CrystalLow·voltage Automatic Reset (LVI)YesYesYesSelf·check ModeExternal Memory ExpansionAvailable-AvailableAvailable- -Other FeaturesEPROM on the Package TypeCompatibility* Preliminary * * Under development* * * Wide Temperature Range (-40 - +8SoC) version is available.t DP; Plastic DIP-MC6805P2- HD68P05V07MC6805P6 -8 _HITACHI

---------------------------- QUICK REFERENCE GUIDEHD6805Vl HD6805T2** HD6805Wl*1.0 1.0 1.05.25 5.25 5.250-+70 0-+70 0-+70DP·40 DP·28 DP·404 2.5 496 64 9624 19 2332 8 19 - 29 6- - -6 6 121 1 21 1 11 1 4- - -• 8·bit timerwith 7·bitprescaler• Event counter·8·bitcomparator- - -• CrystalYes Yes YesAvailable Available Available- - -PLL logicfor RFsynthesizer• 8·bit x4·channelinternalAID converter• 8 bytes ofstandby RAMHD68P05V07 - HD68P05WO*- MC6805T2 -.,.HITACHI 9

QUICK REFERENCE GUIDE-----------------------------• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6301 SERIESLSICharacteristicsHD6301V1HD6301XOType No. HD63A01V1 HD63A01XOHD63B01V1HD63B01XO1.0 (HD6301V1) 1.0 (HD6301XO)Bus Timing (MHz) 1.5 (HD63A01V1) 1.5 (HD63A01XO)2.0 (HD63B01V1) 2.0 (HD63B01XO)Supply Voltage (V) 5.0 5.0Operating Temperature-(oC) 0-+70 0-+70Package t DP-40, FP-54, CG-40 DP-64S, FP-80MemoryROM (k byte) 4 4RAM (byte) 128 1921/0 Port 29 24I/O Port Input Port 29 - 53 8InterruptOutput Port - 21External 2 3Soft 2 2Timer 3 4Functions Serial 1 116-bit x 1 l6-bit x 1(F.ee ".on;n. count .. Xl) ( Free running counter )( 1 )Output compare register x 1 Output compare register x2Timer I nput capture register x 1 Input capture register x18-bit x 1( 8-bit up counter x 1 )Time constant register x 1SCI Asynchronous Asynch ronou s/Synchronou sExternal Memory Expansion 65k bytes 65k bytesOther Features-Error detection-Low power consumptionmodes (sleep and standby)-Error detection-Low power consumptionmodes (sleep and standby)-Slow memory interface-HaltHD63P01M1HD63701 XO**EPROM on the Package Type HD63PA01M1 * (EPROM on-chip)HD63PB01M1 *• Preliminary •• Under development ••• Wide Temperature Range (-40 - +SSoC) version is available.t DP; Plastic DIP, FP; Plastic Flat Package, CG; Glass-sealed Ceramic Leadless Chip Carrier10 eHITACHI

----------------------------- QUICK REFERENCE GUIDEHD6301YO** HD6303R HD6303X HD6303Y**HD63A01YO** HD63A03R HD63A03X HD63A03Y**HD63B01YO** HD63B03R HD63B03X HD63B03Y**1.0 (HD6301YO) 1.0 (HD6303R) 1.0 (H D6303X) 1.0 (HD6303Y)1.5 (HD63A01YO) 1.5 (HD63A03R) 1.5 (HD63A03X) 1.5 (HD63A03Y)2.0 (HD63B01YO) 2.0 (HD63B03R) 2.0 (HD63B03X) 2.0 (H D63B03Y)5.0 5.0 5.0 5.00-+70 0-+70 0-+70 0-+70DP-64S, FP-64 DP-40, FP-54, CG-40 DP-64S, FP-80 DP-64S, FP-6416 - - -256 128 192 25648 13 16 24-----53 - 13 - 24 8 24 -5 - - -3 2 3 32 2 2 24 3 4 41 1 1 116-bit x 1 16-bit x 1 16-bit x 1 16-bit x 1cree .unning counte .. l ) cree .unning coun'" x I ) ( Free running counter xl ) cree .unning counle .. I )Output compare register x 2 Output compare register x 1 - Output compare register x 2 Output compare ~egister x 2Input capture register x 1 Input capture register x 1 Input capture register x 1 Input capture register x 18-bit xl 8-bit x 1 8-bit x 1( 8-bit up counter Xl) ( 8-bit up counter Xl) ( 8-bit up counter Xl)Time constant register x 1 Time constant register x 1 Time constant register x 1Asynchronous/Synchronous Asynchronous Asynchronous/Synchronous Asynchronous/Synchronous65k bytes 65k bytes 65kbytes 65k bytes-Error detection -Error detection -Error detection -Error detection-low power consumption -low power consumption -low power consumption -low power consumptionmodes (sleep and standby) modes (sleep and standby) modes (sleep and standby) modes (sleep and standby)- -Slow memory interface -Slow memory interface -Slow memory interface-Halt -Halt -Halt$ HITACHI 11

QUICK REFERENCE GUIDE·-----------------------------• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6305 SERIESHD6305UO** HD6305VO**Type No. HD63A05UO** HD63A05VO**HD63B05UO** HD63B05VO**1.0 (HD6305UO) 1.0 (HD6305VO)Clock Frequency (MHz) 1.5 (HD63A05UO) 1.5 (HD63A05VO)LSI2.0 (HD63B05UO) 2.0 (HD63B05VO)Characteristics Supply Voltage (V) 5.0 5.0FunctionsOperating Temperature *** (oC) 0-+70 0-+70Package t DP-40 DP·40MemoryROM (k byte) 2 4RAM (byte) 128 192I/O Port 1 31 31I/O Port Input Port 31 - 31 -Output Port - -External 2 2InterruptTimerSCISoft 1 1Timer 2 2Serial 1 1External Memory Expansion - -HD6305XO*HD63A05XO*HD63B05XO*1.0 (HD6305XO)1.5 (HD63A05XO)2.0 (HD63B05XO)5.00-+70DP·64S, FP·6441283255 72121-16Other FeaturesEPROM on the Package TyPe - -Evaluation Ch ip - -HD63P05YO**HD63PA05YO**HD63PB05YO**-• Preliminary •• Under development ••• Wide Temperature Range (-46 - +85 0 C) version is available.t DP; Plastic DIP, FP; Plastic Flat Package12 $ HITACHI

-----------------------------QUICK REFERENCE GUIDEHD630SXl HD630SX2 HD630SYO* HD630SY1* HD630SY2*HD63AOSXl HD63AOSX2 HD63AOSYO* HD63AOSYl * HD63AOSY2* HD63LOSFlHD63BOSXl HD63BOSX2 HD63BOSYO* HD63BOSY1* HD63BOSY2*1.0 (H D630SX 1) 1.0 (HD630SX2) 1.0 (H D630SYO) 1.0 (HD630SY1) 1.0 (H D630SY2)1 .S (H D63AOSX 1 ) 1.S (HD63AOSX2) 1.S (HD63AOSYO) 1.S (H D63AOSY 1 ) 1.S (HD63AOSY2) 0.12'.0 (H D63BOSX 1) 2.0 (HD63BOSX2) 2.0 (HD63BOSYO) 2.0 (HD63BOSY1) 2.0 (HD63BOSY2)S.O S.O S.O S.O S.O 3.00-+70 0-+70 0-+70 0-+70 0-+70 -20 - +7SDP·64S, FP·64 DP·64S, FP·64 DP·64S, FP·64 DP·64S, Fp·64 Dp·64S, Fp·64 DP·64S, FP·804 - 8 8 - 4128 128 2S6 2S6 2S6 9624 24 32 24 24 2031 7 31 7 SS 7 31 7 31 7 20 -- - 16 - - (19)2 2 2 2 2 11 1 1 1 1 12 2 2 2 2 11 1 1 1 1 -• 8·bit x 1 (with 7·bit prescaler)- 8·bit X 1 (with- lS·bit x 1 (combined with SCI) 7·bit prescaler)Synchronous12k bytes 16k bytes - 8 k bytes 16k bytes--- Low power consumption modes - 8·bit AID converter(Wait, stop and standby)-LCD driver(6 x 7 segment)- Low power con·sumption modes(Standby and halt)- -HD63POSYO**HD63PAOSYO** - - -HD63PBOSYO**- - - - -HD63LOSEO~HITACHI 13

QUICK REFERENCE GUIDE.----------------------------• NMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON PACKAGE TYPEType No.LSIl Supply Voltage (V)Characteristics I Operating Temperature*· (0 C)I Package tEquivalent DeviceMountable EPROMHD68P01V07HD6801VOHN482732A·30HD68P01V07·1 * HD68P01MO HD68P01MO·1 *S.O0- +70DC·40PHD6801VS - -HN482732A·30 HN482764·3 HN482764·3HD68POSV07S.OHD68POSWO*S.O0- +70 0-+70DC·40PHD680SU1HD680SVlDC·40PHD680SW1HN482732A·30 HN482732A·30HN482764·3"• Preliminary.. Wide Temperature Range (-40 - +85"C) version is available.t DC; Ceramic DIP (EPROM on the package type)• CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON PACKAGE TYPEType No. HD63P01M1 HD63PA01M1· HD63PB01M1· HD63POSYO·· HD63PAOSYO" HD63PBOSYO··Supply Voltage (V)S.OS.OLSICharacteristics Operating Temperature"· (oC)0- +70 0- +70Equivalent DevicePackage tHD6301V1DC·40PHD63A01V1HD63B01V1DP·64SPHD630SXO HD63AOSXO HD63BOSXOHD6305YO HD63AOSYO HD63BOSYOMountable EPROMHN482732A·30HN482764·3HN27C&4·30HN482732A·30 HN482732A·25 HN482732A·30 HN482732A·30 HN482732A·25HN482764·3 HN482764 HN482764·3 HN482764·3 HN482764HN27C64·30 HN27C&4·25 HN27C&4·30 HN27C64·30 HN27C&4·25• Preliminary•• Under Development••• Wide Temperature Range (-40 - +8SoC) version is available.t DC; Ceramic DIP (EPROM on the package type)14eHITACHI

----------------------------- QUICK REFERENCE GUIDE• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON-CHIP TYPEType No.HD63701XO*Bus Timing (MHz) 1.0LSI Supply Voltage (V) 5.0CharacteristicsOperating Temperature (oC) 0-+70Package tDC-64SMemoryROM (k byte)RAM (byte) 1924 (EPROM)FunctionsI/O Port~24I/O Port Input Port 53 8InterruptOutput Port 21External 3Soft 2Timer 4Serial 116-bit x 1Free running counter x 1Output compare register x 2Timer (Input capture register x 18-bit x 1( 8-bit up counter xl)Time constant register x 1SCIAsynch ronous/Sy nch ronou s)-External Memory ExpansionOther Features65k bytes• Error detection• Low power consumption modes (sleep and standby)• Slow memory interface• HaltEquivalent DeviceHD6301XOReference Page 720• Under developmentt DC; Ceramic DIP (Shrink typel_HITACHI 15

INTRODUCTION OF PACKAGESHitac;hi microcomputer devices are offered in a variety ofpackages, to meet various user requirements.1. Package ClassificationWhen selecting suitable packaging, please refer to thePackage Classifications given in Fig. I for pin insertion, surfacemount, and multi-function types, in plastic and ceramic.Standard OutlinePlastic DIPPin Insertion TypeCeramic DIPShrink OutlineShrink Type Plastic DIPShrink Type Ceramic DIPPackage ClassificationFlat PackageSurface Mounting TypeChip CarrierMulti·function TypeDIP; DUAL IN LINE PACKAGES·DIP; SHRINK DUAL IN LINE PACKAGEPGA: PIN GRID ARRAYFLAT·DIP; FLAT DUAL IN LINE PACKAGEFLAT·QUIP; FLAT QUAD IN LINE PACKAGECC: CHIP CARRIERSOP;SMALL OUTLINE PACKAGEFPP; FLAT PLASTIC PACKAGEPLCC;PLASTIC LEADED CHIP CARRIERLCC ; LEADLESS CHIP CARRIERFig. 1Package Classification according to Material and Printed Circuit Board Mounting Type_HITACHI 17

INTRODUCTION OF PACKAGES------------------------2. Type No. and Package Code Indication by code as follows, and illustrated in the data sheet for eachThe Hitachi Type No. for single-chip microcomputer devices device.is followed by package material and outline specifications, asshown below. The package type used for each device is identifiedWhen ordering, please write the package code next to thetype number.Type No. IndicationHDx X X xP(Note I HDXXfXXXX stands for Type No.of EPROM on the package typemicrocomputer device.Package ClassificationNo Indication : Cerwnic DIPP ; Plastic DIPF ; FPPCG; LCCPeclcage Cod. IndicationDP-64SD ;DIPC;CCF ;FLATPGCAdditional OutlineS; Shrink typeP; EPROM on the package type18_HITACHI

------------------------INTRODUCTION OF PACKAGES3. Package Dimensional OutlineHitachi single-chip microcomputer devices employ the packagesshown in Table I according to PCB mounting method.Table 1 Package ListMounting method'.'Package classificationPackage materialPackage codePin insertion typeStandard outline (DIP)Shrink outline (S-DIP)PlasticPlasticCeramicDp·28DP-40DP-64SDC·64SSurface mounting typeFlat package (FPP)PlasticFp·54Fp·64Fp·80Chip carrier (LCC)Glass sealed ceramicCG·40Multi-function typeEPROM on the package typeCeramicDC-40PDC·64SPPlastic DIP• DP·2814 155:~:Cu2.54ming~-O· -IS" 0.20-0.38(Unit: mm)• DP-40(Unit:mm)~HITACHI19

I Shrink Type Plastic DIP• DP·64SIUnit: mm)I Shrink Type Ceramic DIP• DC·64S1-- .. 11,>. - .. -IUnit:mm)20$ HITACHI

---------------~--·------INTRODUCTION OF PACKAGESLF'atPack~• FP·54~-·~·:121i.e±O.4 ; J..J ( UiiiiihiihiiOh I Jf:f~(Unit:mm)• FP·64• FP-80(Unit:mm)(Unit: mm)_HITACHI 21

INTRODUCTION OF PACKAGES ----------------------I bid' ... Chip Carrier I• CG·4012,19;D~J~IIII 000000000 oiTlH,02 ~ JCO.84, I- ~2.&4 1t"D.51 .;•!D IDDCDDI1DD c,....~c= ;(Unlt:mm)I EPROM 011-....... Type• DC-40Pq "020·0111124-0_'(Unit:mm)22_HITACHI

------------------------INTRODUCTION OF PACKAGES• DC-84SPoIUnit:mml4. Mounting M.thocIPackage lead pins are surface treated with solder coating orplating to facilitate PCB mounting. The lead pins are connectedto the package by eutectic solder. Common connecting methodof leads and precautions are explained as follows:4.1 Mounting Methods of Pin Insertion Type P.ckageInsert lead pins into the PCB through-holes (usually about.,.0.8mm). Soak leads in a wave solder tub.Lead pins held by the through-holes enable handling of thepackage through the sqldering process, and facilitate automatedsoldering. When soldering leads in the wave solder tub, do notget solder on the package.4.2 Mounting Method of lurfllce Mount Type P.ck ..Apply the specified quantity of solder paste to the pattern onany printed board by the screen printing method, to temporarilyfix the package to the board. The solder paste melts when heatedin a renowing furnace, and package leads and the pattern of theprinted board are fixed by the surface tension of the meltedsolder and self alignment.The size of the pattern where leads are attached should be 1.1to 1.3 times the leads' width, depending on paste material orfurnace adjustment.The temperature of the renowing furnace is dependent onpackaging material and type. Fig. 2 lists the adjustment of therenowing furnace for FPP. Pre-heat the furnace to 1500C. Surfacetemperature of the resin should be kept at 235 0 C maximumfor 10 minutes or less.Fig. 2 Reflowing Furnace Adjustmentfor FPPTime-Employ adequate heating or temperature control equipmentto prevent damage to the plastic package epoxy-resin material.When using an infrared heater, avoid long exposure at temperatureshigher than the glass transition point of epoxy-resin (about1500 C), which may cause package damage and loss of reliabilitycharacteristics. Equalize the temperature inside and outside ofpackages by reducing the heat of the upper surface of thepackages.FPP leads may easily bend in shipment or during handling,and impact soldering onto the printed board. Heat the bent leadsagain with a soldering iron to reshape them.Use a rosin flux when soldering. Do not use chloric fluxbecause the chlorine in the flux has a tendency to remain on theleads and reduce reliability. Use alcohol, chlorothene orfreon towash away rosin flux from packages. These solvents should notremain on the packages for an excessive length of time, becausethe package markings may disappear.eHITACHI 23

5. Package MarkingThe Hitachi trademark and product type No. are printed onpackages, as shown in the following examples. Customermarking can be added to single-chip devices upon request.(a)(b).~~~(')B DB8DrnS DB(d)~ D D (e)O~B~fSIMeaning of each mark(a) Hitachi Trademark(b) Lot Code(c) Type No.(d) ,ROM Code(e) Japan Mark24 _HITACHI

QUALITYASSURANCE1. VIEWS ON QUALITY AND RELIABILITYBasic views on quality at Hitachi are to meet theindividual uers' required quality level and maintain ageneral quality level equal to or above that of thegeneral market. The quality required by the user maybe specified by contract. or may be indefinite. In eithercase. efforts are made to assure reliable performancein actual operating circumstances. Quality controlduring the manufacturing process. and quality awarenessfrom design through production lead to productquality and customer satisfaction. Our quality assurancetechnique consists basically of the followingsteps:(1) Build in reliability at the design stage of newproduct development.(2) Build in quality at all steps in the manufacturingprocess.(3) Execute stringent inspection and reliability confirmationof final products.(4) Enhance quality levels through field data feedback.(5) Cooperate with research laboratories for higherquality and reliability.With the views and methods mentioned above.utmost efforts are made to meet users' requirements.2. RELIABILITY DESIGN OFSEMICONDUCTOR DEVICES2.1 Reliability TargetsThe reliability target is an important factor in sales.manufacturing, performance, and price. It is not adequateto set a reliability target based on a single set ofcommon test conditions. The reliability target is setbased on many factors:(1) End use of semiconductor device.(2) End use of equipment in which device is used.(3) Device manufacturing process.(4) End user manufacturing techniques.(5) Quality control and screening test methods.(6) Reliability target of system.2.2 Reliability DesignThe following steps are taken to meet the reliabilitytargets:(1) Design StandardizationAs for design rules, critical items pertaining toquality and reliability are always studied at circuitdesign. device design, layout design. etc. Therefore.as long as standardized processing andmaterials are used the reliability risk is extremelysmall even in the case of new developmentdevices. with the exception of special requirementsimposed by functional needs.(2) Device DesignIt is important for the device design to considertotal balance of process, structure. circuit. andlayout design. especially in the case where newprocesses and/or new materials are employed.Rigorous technical studies are conducted prior todevice development.(3) Reliability Evaluation by Functional TestFunctional Testing is a useful method for designand prOCess reliability evaluation of Ie's and LSIdevices which have complicated functions.The objectives of Functional Test are:• Determining the fundamental failure mode.• Analysis of relation between failure mode andmanufacturing process.• Analysis of failure mechanism.• Establishment of QC points in manufacturingprocess.2.3 Design ReviewDesign Review is an orga nized method to confirm thata design satisfies the performance required andmeets design specifications. In addition, design reviewhelps to insure quality and reliability of the finishedproducts. At Hitachi, design review is performed fromthe planning stage to production for new products.and also for design changes on existing products.Items discussed and considered at design review are:(1) Description of the products based on designdocuments.(2) From the standpoint of each participant. design~ documents are studied. and for points needingclarificatio~. further investigation will be carriedout. \(3) Specify quaiity control and test methods based ondesign documents and drawings.(4) Check process and ability of manufacturing line toachieve design goal.(5) Preparation for production.(6) Planning and execution of sub-programs fordesign changes proposed by individual specialists.$ HITACHI 25

QUALITY ASSURANCE ----------------------for test, experiments, and calculations to confirmthe design changes.(7) Analysis of past failures with similar devices, discussionof methods to prevent them, and planningand execution oftest programs to confirm success.3. QUALITY ASSURANCE SYSTEM3.1 Activity of Quality AssuranceGeneral views of overall quality assurance in Hitachiare as follows:(1) Problems in each individual process should besolved in lhe process. Therefore. at the finishedproduct stage the potential failure factors havebeen removed.(2) Feedback of information is used to insure a satisfactorylevel of ability process.3.2 Quality ApprovalTo insure quality and reliability. quality approval iscarried out at the preproduction stage of devicedesign. as described in section 2. Our views on qualityapproval are:(1) A third party executes approval objectively fromthe standpoint of the customer.(2) Full consideration is given to past failures andinformation from the field.(3) No design change or process change without QAapproval.(4) Parts. materials. and processes are closelymonitored.(5) Control points are established in mass productionafter studying the process abilities and variables.3.3 Quality and Reliability Control .t M •••ProductionQuality control is accomplished through division otfunctions jn manufacturing, quality assurance, andother related departments. The total function flow isshown in Fig. 2. The main points are described below.StepContentsl Target IL Design ReviewSpecificationI.~DesignTrialProductionCharacteristics of Material andMaterials, Parts IIPartsApproval II AppearanceDimensionHeat ResistanceMechanicalElectricalOthersConfirmation ofCharacteristics andReliability of Materialsand PartsIICharacteristics Approval IIElectricalCharacteristicsFunctionVoltageCurrentTemperatureOthersAppearance, DimensionI Confirmation of TargetSpec. Mainly aboutElectrical CharacteristicsIIQuality Approval (1),II Quality Approval (2)Processl~assJReliability TestLife TestThermal StressMoisture ResistanceMechanical StressOthersReliability TestCheck same asQuality Approval (1)Production Figure 1 Flow Chart of Quality Approval,Confirmation of Qualityand Reliability in DesignConfirmation of Quality.and Reliability in MassProduction26 $ HITACHI

--------------------- QUALITY ASSURANCEProcess Quality Control MethodMaterialParts Inspection on Material and Lot Sampling,Parts for SemiconductorConfirmation ofDevicesQuality LevelManufacturing Equipment,Environment, Sub-material,Worker ControlConfirmation ofQuality LevelInner ProcessQuality ControlLot Sampling,Confirmation ofQuality LevelIIIIII---Products100% Inspection onAppearance and ElectricalCharacteristicsSampling Inspection onAppearance and ElectricalCharacteristics--1Testing,InspectionLot SamplingConfirmation of~---- Reliability Test Quality Level, LotSampling~---------------,: Quality Information II Claim :: Field ExperienceI General QualityL _________________ Information~IFeedback ofInformationFigure 2 Flow Chart of Quality Control in Manufacturing ProcesseHITACHI27

QUALITY ASSURANCE---------------------3.3.1 Quality Control of Parts and MaterialsAs semiconductor devices tend towards higher performanceand higher reliability, the importance ofquality control of parts and materials becomes paramount.Items such as crystals, lead frames, fine wirefor wire bonding, packages, and materials needed inmanufacturing processes such as masks and chemicals,are all subject to rigorous inspection and control.Incoming inspection is performed based on the purchasespecification and drawing. The sampling is executedbased mainly on MIL-STD-105D.The other activities of quality assurance are asfollows:(1) Outside vendor technical information meeting.(2) Approval and guidance of outside vendors.(3) Chemical analysis and test.The typical check points of parts and materials areshown in Table 1.Tillie' OuIlity Control Check Paints of Material and Parts(ExamplelMaterial, ImportantParts Control ItemsPoint for CheckAppearance Damage and Contamina·tion on SurfaceWaferDimension FlatnessSheet Resistance ResistaneeDefect Density Defect NumbersCrystal AxisAppearance Defect Numbers, ScratchMaskDimension Dimension LevelResistorationGradation Uniformity of GradationAppearanceFineContamination, Scratch,Wire forBend, TwistWireDimensionPurityBondingPurity LevelElongation Ratio Mechanical StrengthAppearance Contamination, ScratchDimension Dimension LevelProceSSingFrame AccuracyPlatingBondability, SolderabilityMounting Heat ResistanceCharacteristicsAppearance Contamination, ScratchDimension Dimension LevelLeak Resistance AirtightnessPlatingBondability, SolderabilityCeramic Mounting Heat ResistancePackage CharacteristicsElectrieelCharacteristicsMechanical Mechanical StrengthStrengthCompOSition Characteristics ofPlastic MaterialElectricalCharacteristicsPlasticThermalCharacteristicsMoldingMolding PerformancePerformanceMounting Mounting CharacteristicsCharacteristics3.3.2 Inner Procell Quality ControlInner Process Quality Control performs very importantfunctions in quality assurance of semiconductordevices. The manufacturing Inner Process QualityControl is shown in Fig. 3.(1) Quality Control of Semi-final Products and FinalProductsPotential failure factors of semiconductor devicesare removed in the manufacturing process. Toachieve this, check points are set-up in each processand products which have potential failurefactors are not moved to the next process step.Manufacturing lines are rigidly selected and tightinner process quality controls are executed-rigidchecks in each process and each lot, 100% inspectionto remove failure factors caused by manufacturingvariables and high temperature aging andtemperature cycling. Elements of inner processquality control are as follows:• Condition control of equipment and workersenvironment and random sampling of semifinalproducts.• Suggestion system for improvement of work.• Education of workers.• Maintenance and improvement of yield.• Determining quality problems, and implement·ing countermeasures.• Transfer of quality information.(2) Quality Control of Manufacturing Facilities andMeasuring EquipmentManufacturing equipment is improving as higherperformance devices are needed. At Hitachi, theautomation of manufacturing equipment is encouraged.Maintenance Systems maintain operationof high performance equipment. There aredaily inspections which are performed based onrelated specifications. Inspection points are listedin the specification and are checked one by one toprevent any omission. As for adjustment andmaintenance of measuring equipment, specificationsare checked one by one to maintain andimprove quality.(3) Quality Control of Manufacturing Circumstancesand Sub-MaterialsThe quality and reliability of semiconductor devicesare highly affected by the manufacturing process.Therefore, controls of manufacturing circum-28$ HITACHI

QUALITY ASSURANCEstances such as temperature, humidity and dust,and the control of submaterials, like gas, and purewater used in a manufacturing process, are intensivelyexecuted.Dust control is essential to realize higher integrationand higher reliability of devices. At Hitachi,maintenance and improvement of cleanliness atmanufacturing sites is accomplished throughattention to buildings, facilities, air conditioningsystems, delivered materials, clothes, work environment,and periodic inspection of floating dustconcentration.3.3.3 Final Product Inspection and ReliabilityAssurance(1) Final Product InspectionLot inspection is done by the quality assuranceProcess Control Point Purpose of ControlPurchase of Materialwafer~ Wafer Characteristics, Appearance Scratch, Removal of CrystalDefect Wafer, Surface Oxidation Oxidation Assurance of ResistanceInspection on Surface Appearance, Thickness of Pinhole, ScratchOxidationOxide FilmPhoto ResistPhotoResistInspection on Photo Resist Dimension, Appearance Dimension Level PQC Level Check Check of Photo ResistDiffusion Diffusion Diffusion Depth, Sheet Diffusion StatusResistanceInspection on Diffusion Gate Width Control of Basic Parameters PQC Level Check Characteristics of Oxide Film (VTH, etc.) Cleanness of surface,Breakt.!own VoltagePrior Check of VIHBreakdown Voltage CheckEvaporation Evapora- Thickness of Vapor Film, Assurance of Standardtion Scratch, Contamination ThicknessInspection on Evaporation PQC Level CheckWafer Inspection Wafer Thickness, VTH Characteris- Prevention of Crack,ticsQuality Assurance of ScribeInspection on Chip Chip Electrical CharacteristicsElectrical CharacteristicsChip ScribeAppearance of ChipInspection on ChipAppearance PQC Lot JudgementFrameAssembling Assembling Appearance after Chip Quality Check of ChipBondingBondingAppearance after WireQuality Check of WireBondingBonding PQC Level Check Pull Strength, Compression Prevention of Open andWidth, Shear StrengthShortInspection afterAppearance after AssemblingAssembling PQC Lot JudgementSealing Sealing Appearance after Sealing Guarantee of AppearanceOutline, Dimensionand DimenSion PQC Level Check Marking Marking StrengthFinal Electrical Inspection Failure Analysis AnalySis of Failures, Failure Feedback of Analysis Infor-Mode, MechanismmationAppearance InspectionSampling Inspection onProductsReceivingShipmentFigure 3 Example of Inner Process Quality ControleHITACHI 29

QUALITY ASSURANCE ----------------------department for products which were judged goodin 100% test ... the final process in manufacturing.Though 100% yield is expected. samplinginspection is executed to prevent mixture of badproduct by mistake. The inspection is executed notonly to confirm that the products have met theusers' requirements but also to consider potentialCustomerISales Dept.Sales Engineering Dept.quality factors. Lot inspection is executed basedon MIL-STO-1050.(2) Reliability Assurance TestsTo assure the reliability of semiconductor devices.reliability tests and tests on individual manufacturinglots that are required by the user. are periodicallyperformed.Claim(Failures, Information)r------------~---------------------lQual ity Assu ranee Dept.Failure AnalysisManufacturing Dept.LReport1Design Dept.CountermeasureExecution ofCountermeasureQuality Assurance Dept.I---Follow-up and Confirmationof Countermeasure ExecutionReportL-----_______ 4 ____________________ ~Sales Engineering Dept.ReplyCustomerFigure 4 Process Flow Chart of Field Failure30 $ HITACHI

RELIABILITY TEST DATA1. INTRODUCTIONMicrocomputers provide high reliability and quality to meetthe demands of increased functions, enlarging scale, and wideningapplication. Hitachi has improved the quality level ofmicrocomputer products by evaluating reliability, buildingquality into the manufacturing process, strengthening inspectiontechniques, and analyzing field data.The following reliability and quality assurance data forHitachi 8-bit single-chip microcomputers indicates results fromtest and failure analysis.2. PACKAGE AND CHIP STRUCTURE2.1 PackagingProduction output and application of plastic packaging continuesto increase, expanding to automobile measuring and controlsystems, and computer terminal equipment operating undersevere conditions. To meet this demand, Hitachi has significantlyimproved moisture resistance and operational stability in theplastic manufacturing process.Plastic and side-brazed ceramic package structures are shownin Figure 1 and Table I.(11 Plastic DIP(21 Plastic Flat PackageBonding wireBonding wireChipFigure 1 Package StructureTable 1 Package Material and PropertiesItem Plastic DIP Plastic Flat PackagePackage Epoxy EpoxyLead Solder dipping Alloy 42 Solder plating Alloy 42Die bond Au-Si or Ag paste Au-Si or Ag pasteWire bond Thermo compression Thermo compressionWire Au AuCf)HITACHI31

RELIABI LlTY TEST DATA---------------------------2.2 Chip StructureThe HMCS6800 family is produced in NMOS EjD technologyor low power CMOS technology. Si-gate process is usedin both types to achieve high reliability and density. Chip structureand basic circuitry are shown in Figure 2.Si·Gate N-channel E/DSi·Gate CMOSDrain Source Drain Source SiO. SourceFEnFET2FET2N-channelDMOSP-channelEMOSFET2N-channelEMOSN-channelEMOSFigure 2 Chip Structure and Basic Circuit3. QUALITY QUALIFICATION AND EVALUATION3.1 Reliability Test MethodsReliability test methods shown in Table 2 are used to qualify and evaluate new products and processes.Table 2 Reliability Test MethodsTest Items Test Condition M Il·STD·883B Method No.Operating life Test 125°C,10oohr 1005,2High Temp, Storage Tstg max, 1000hr 1008,1Low Temp, StorageTstg min, 1000hrSteady State Humidity65°C 95%RH, 1oo0hrSteady State Humidity Biased85°C 85%RH, 1000hrTemperature CyclingTemperature Cycling-55°C'" 150°C, 10 cycles_20° C '" 125° C: 200 cycles1010,4Thermal Shock O°C'" 100°C, 100 cyclesSoldering Heat260° C, 10 sec1011,32002,22005,1MechanicaJ ShockVibration Fatigue1500G 0.5 msec, 3 times/X, V, Z60Hz 20G, 32hrs/X, V, ZVariable Frequency 2o-2000Hz 200, 4 min/X, V, Z 2007,1Constant Acceleration 200000, 1 min/X, V, Z 2001,2lead Integrity 225gr, 90° 3 times 2004,332 ~HITACHI

--------------------------RELIABI LlTY TEST DATA3.2 ReilabiHty Test R •• ultsReliability Test Results of 8-bit single-chip microcomputer'devices are shown in Table 3 to Table 7.Table 3 Dynamic Life TestDevice Sample Size Component Hour FailureHD6801P 191 191000 0......................................................................... HD6805P 114 114000 0,.....................................................................................................HD6301P 92 92000 0HD63L05FP 40 40000 0HD6305XP 56 56000 0HD68POlHD68P0522222200022000oo(1) 85°C 85%RH Bias TestTable 4 High Temperature. High Humidity Test (Moisture Resistance Test)Device.vcc BiasHD6801P 5.5VHD6805P 5.5VHD6301P 5.5VTotal168 hrs 500 hrs0/22 0/220/22 0/220/176 0/1310/220 0/1751000 hrs0/220/220/1310/175(2) High Temperature High Humidity Storage Life TestDeviceHD6801PHD6805PHD6301PHD6301PHD63L05FPHD63L05FPHD6305XPCondition65°C 95%RH65°C 95%RH65°C 95%RH85°C 95%RH65°C 95%RH85°C 95%RH65°C 95%RH16B hrs500 hrs0/45 0/450/45 0/450/603 0/6030/234 1 */2340/160 0/1600/160 1*/1600/373 0/3731000 hrs0/450/450/6030/2330/1600/1590/373* Aluminium corrosion(3) Pressure Cooker Test(121°C.2atm)DeviceHD6801PHD6805PHD6301PHD6305XPHD63L05FP40hrs0/130/440/1350/830/8060 hrs 100 hrs0/13 0/130/44 0/440/135 0/1350/83 0/830/80 1*/80200 hrs0/130/440/1350/832**/79* Current leakage** Current leakage and aluminium corrosion_HITACHI 33

RELIABILITY TEST DATA --------------------------(4) MIL-STD-883B Moisture Resistance Test(-65°C"'" _10°C, 90%~H or more)DeviceHD6801PHD6805PHD6301PHD63L05FP10 cycles0/500/320/750/2220 cycles 40 cycles0/50 0/500/32 0/320/75 0/75 .0/22 0/22Table 5 Temperature Cycling Test(-55°C - 150°C)Device 10 cycles 100 cycles 200 cyclesHD6801P 0/102 0/102 01102HD6805P 0/442 0/45 0/45HD6301P 0/258 0/258 0/258..............................................................................................................................................................................HD6305XP 0/80 0/80 0/80HD68P01 0/44 0/44 0/44HD68P05 0/68 0/19 0/19Table 6 High Temperature, Low Temperature Storage life TestDevice Temperature 168 hrs 500 hrs 1000 hrs150°C 0/22 0/22 0/22HD6801P-55°C 0/22 0/22 0/22.......................................... ················,·50°C·················· ··················Oi"4·4·············· ············ .. ····Oi44··············· ·················0/44···············H D6805P _ 55° C 0/22 0/22 0/22.......................................... ················1·50°C·················· ··················o"Fii············· ··················Oi22··············· ················0/22···············HD6301P -55°C 0/22 0/22 0/22.......................................... ················150~C·················· ··················0/2"2"············· ··················Oi22··············· ················0·i22···············HD63L05FP -55 C 0/22 0/22 0/22Table 7 Mechanical and Environmental TestTest ItemConditionPlastic DIPFlat Plastic PackageSample Size Failure Sample Size FailureThermal Shock0°C-100°C10 cycles110 0 100 0Soldering Heat 260° C. 10 sec. 164 0 20 0Salt Water Spray35°C, NaCI 5%24 hrs110 0 20 0Solderabil ity230°C, 5 sec.Rosin flux159 0 34 0Drop Test75cm, maple board3 times110 0 20 0Mechanical Shock1500G, 0.5ms3 times/X, V, Z110 0 20 0Vibration Fatigue60 Hz, 20G32hrs/X, V, Z110 0 20 0Vibration Variable Freq.100- 2000Hz20G, 4 times/X, V, Z110 0 20 0Lead Integrity225g,900Bonding 3 times110 0 20 034 $ HITACHI

--------------------------RELIABI LIlY lEST DATA4. PRECAUTIONS4.1 StorageTo prevent deterioration of electrical characteristics, solderability,appearance or structure, Hitachi recommends semiconductordevices be stored as follows:(I) Store in ambient temperatures of 5 to 300 C, with a relativehumidity of 40 to 60%.(2) Store in a clean, dust- and active gas-free environment.(3) Store in conductive containers to prevent static electricity.(4) Store without any physical load.(5) When storing devices for an extended period, store in anunfabricated form, to minimize corrosion of pre-formedlead wires.(6) Unsealed chips should be stored in a cool, dry, dark anddust-free environment. Assembly should be performedwithin 5 days of unpacking. Devices can be stored for up to20 days in dry nitrogen gas with a dew point at -30 0 C or less.(7) Prevent condensation during storage due to rapid temperaturechanges.4.2 TransportationGeneral precautions for electronic components are applicablein transporting semiconductors, units incorporating semi- .conductors, and other similar systems. In addition, Hitachirecommends the following:(I) When transporting semiconductor devices or printed circuitboards, minimize mechanical vibration and shock. Use containersor jigs which will not induce static electricity as aresult of vibration. Use of an electrically conductive containeror aluminum foil is recommended.(2) To prevent device deterioration from clothing-induced staticelectricity, workers should be properly grounded while handlingdevices. Use of a I M ohm resistor is recommended toprevent electric shock.(3) When transporting printed curcuit boards containing semiconductordevices, suitable preventive measures againststatic electricity must be taken. Voltage build-up can beavoided by shorting the card-edge terminals. When a beltconveyor is used, apply some surface treatment to preventbuild-up of electrical charge.(4) Minimize mechanical vibration and shock when transportingsemiconductor devices or printed circuit boards.4.3 Handling for MeasurementAvoid static electricity, noise and voltage surge when measuringor mounting devices. Precaution should be taken againstcurrent leakage through terminals and housings of curve tracers,synchroscopes, pulse generators, and DC power sources.When testing devices, prevent voltage surges from the tester,attached clamping circuit, and any excessive voltage possiblethrough accidental contact.In inspecting a printed circuit board, power should not beapplied if any solder bridges or foreign matter is present.4.4 SolderingSemiconductor devices should not be exposed to hightemperatures for excessive periods. Soldering must be performedconsistent with temperature conditions of 260 0 C for 10 seconds,350 0 C for 3 seconds, and at a distance of I to 1.5mm from the endof the device package.A soldering iron with secondary voltage supplied through agrounded transformer is recommended to protect againstleakage current. Use of alkali or acid flux, which may corrode theleads, is not recommended.4.6 Removing Residual FluxDetergent or ultrasonic removal of residual flux from circuitboards is necessary to ensure system reliability. Selection ofdetergent type and cleaning conditions are important factors.When chloric detergent is used for plastic packaged devices,care must be taken against package corrosion. Extendedcleaning periods and excessive temperature conditions can causethe chip coating to swell due to solvent permeation. Hitachirecommends use of Lotus and Dyfron solvents. Trichloroethylenesolvent is not suitable.The following conditions are advisable for ultrasoniccleaning:• Frequency: 28 to 29 k Hz (to avoid device resonation)• Ultrasonic output: 15W Ii• Keep devices from making direct contact with powergenerator• Cleaning time: Less than 30 seconds.$ HITACHI 35

DESIGN PROCEDURE AND SUPPORT TOOLS FOR8-BIT SINGLE-CHIP MICROCOMPUTERSThe cross assmebler and hardware simulator using varioustypes of computers are prepared by Hitachi as supporting systemsto develop user's programs.User's programs are mask programmed into the ROM anddelivered as the LSI by the company.Fig. I shows the typical program design procedure and TableI shows the system development support tools for the 8-bitsingle-chip microcomputer family used in these processes.®Text Editor I CRT EditorEvaluation KitH68SD5Intel MDSPDP·11VAX-11IBM370Crou AgemblerEvaluation KitH68SD5Intel MDSPDP-11VAX-11IBM370NoEvaluation KitEvaluation BoardH68SD5EPROM on the Package TypeMicrocomputerHD68P01V07HD68P05V07HD68P05WO[ HD63P01M1HD63P05YO(E xplanat ion)CD When the user programs the system, the predetermined functions areassigned to the I/O pin and the RAM before the programming.® A flow chart is designed to achieve the predetermined functions and the flowchart is coded by using the prenumeric code.@ The coded flow chart is punched into the card or the paper tape or written intothe floppy disk, to generate a source program.@ The source program is assembled by the resident system (evaluation kit) or thecross system, to generate the object program. In this case, errors duringthe assembling are also detected.® Hardware simulation is performed to confirm the program.The company provides four kinds of hardware, the H68SD5, the evaluation kit,the evaluation board and the EPROM on the package type microcomputer. Theconsumers are able to choose the best suitable tool.® The completed program is sent to the company in the form of EPROM or theobject tape.Q) Options such as ROM is masked by the company, LSI is testatively producedand the sample is handed in to the user. After the user has evaluated thesample and confirmed that the program is correct, mass production isstarted.Figure 1 Program Design Procedure36~HITACHI

DESIGN PROCEDURE AND SUPPORT TOOLS-------------------------FOR 8-BIT SINGLE-CHIP MICROCOMPUTERSTable 1 System Development Support ToolsType No.Evaluation KitEvaluationBoardResident SystemEPROM onthe PackageH68SDS + Emulator Set(Hardware + Software)Cross SystemIntel PDP-11/IBM 370 M DS220/230 VAX -11HD6801S0HD6801VOH61 EVT2 (Hardware)+S61MIX2-R (Software)HD68P01V07H68SDS + H61MIX1S31MDS1-FS31XSY1-T (ISIS-II) 0S31MDS2-F(CP/M)HD6301V1H31EVT1 (Hardware)+ - HD63P01M1 H68SDS + H31MIX1S31MIX1-R (Software)S31XSY1-T S31MDS1-F------+--'=-=-.:~::"O"':"..:....:.....J=:...:..:..:..:=--+--'---_+---__:-_;-------___1 (ISIS-II) ~H 0630..:..;1 X~O-;;*:;d· ____HD6301YO- - ** - H68SDS + H31MIX3- (CP/M) 0-___ -4---:..H-"3_1_EV~0_'_1_*t__'_'_H=.D.=.:63=-=7-=0'-'-1 :.;.Xo=-t*_*-t--'-H..;...:6:....=8-=-SD~~S _+...:..H:....=3...:..1 M~I X-,2'--J S31 MDS2-F ~HD630SUO- ** H68SDS + **HD630~~V~~_*r_-----------r_------~---------r_---------_+---------HD630SXO*H3SEVOO* HD63POSYO-S6SMDS1-FHD630Sxf* H3SEVT1(ISIS-II) *~HD630SYO'" (Hardware + Software) 1----*-*---f-H-D-6-3-PO-S-Y-0--c::--i H68SDS + H3SMIX1S3SMDS1-FHD630SY1*(ISIS-II)---------+----------------r--------r--------~--------------_+-----~ S3SMDS2-F*~H3LSEVT1 (Hardware)(CP/M)HD63LOSF1 + H3LSEVOO - H68SDS + H3L5MIX1S3LSMIX1-R (Software* Preliminary ** Under development t EPROM On-chip Type 0 Available from Microtec.o~HITACHI 37

DESIGN PROCEDURE AND SUPPORT TOOLSFOR 8-BIT SINGLE-CHIP MICROCOMPUTERS------------------------• SINGLE-CHIP MICROCOMPUTER DEVELOPMENT SYSTEMThe H68S0S is a development system for Hitachi 4-bit and8-bit single-chip microcomputers.It is a compact H06800-based CRT/Key board microcomputerterminal, with two Floppy disk drivers, and has standardinterface for the TTY (RS-232C or TTL level) and printer (Centronicsparallel interface). An optional EPROM Writer isavailable.Features• Supports system development for 8-bit and 4-bit single-chipmicrocomputers.• Disk based low cost system• Provides the CRT Editor, Assembler, Emulator, andEPROM Writer controlled by FOOS-III• S6k-byte RAM• Allows linking between the H68S0S and the I/O devices(TTY and Printer)• Easy to debug user's prototype system using the EmulatorModuleSystem ConfigurationH68SD5EPROM WriterEmulator Module8-bit single-chip miCrO-]computer familyHMCS40 series138 ~HITACHI

DATA SHEETS

Preliminary data sheets herein contain information on new products. Specificationsand information are subject to change without notice.Advance Information data sheets herein contain information on productsunder development. Hitachi reserves the right to change or discontinue theseproducts without notice.

HD6801S0, HD6801S5--­MCU (Microcomputer Unit)The H))6801S MCU is an 8·bit microcomputer systemwhich is compatible with the HMCS6800 family of parts. TheH))6801S MCU is object code compatible with the H06800with improved execution times of key instructions plus severalnew. 16.oit and 8·bit instructions including an 8x8 unsignedmultiply with 16-bit result. The HD6801S MCV can operateas a single - chip microcomputer or be expanded to 65kwords. The H06801S MCV is TTL compatible and requiresone +5.0 volt power supply. The HD6801S MCV has 2kbytes of ROM and 128 bytes of RAM on chip. Serial Com·munications interface (S.C.I.), and parallel I/O as well as athree function 16-bit timer. Features and Block diagram ofthe H06801S include the following:HD6801S0PHD6801S5P(DP-40)• FEATURES• Expanded HMCS6800 Instruction Set• 8 x 8 Multiply• On·Chip Serial Communications Interface (S.C.I.)• Object Code Compatible With The HD6800 MPU• H)·Bit Timer• Single Chip Or Expandable To 65k Words• 2k Bytes Of ROM• 128 Bytes Of RAM (64 Bytes Retainable On PowerDown)• 29 Parallel I/O Lines And 2 Handshake Control Lines• Internal Clock/Divided-By-Four Circuitry• TTL Compatible Inputs And Outputs• Interrupt Capability• Compatible with MC6801 and MC6801-1• BLOCK DIAGRAM• PIN ARRANGEMENToHD6801SP 17(Top View)SC,SC2P30P 3 ,P32P33P 34P 35P 38P 37Poep.,p. 2P 43P44P4ep. 71 Vee Standby• TYPE OF PRODUCTSMCUHD6801SOHD6801S5Bus Timing1 MHz1.25 MHza.---P,o~ ==:PII P"PI)~==:~::1----PI6I----P"@HITACHI41

HD6801S0,HD6801S5--------------------------------------------~~--~• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee * -0.3-+7.0 VInput Voltage Vln * -0.3 - +7.0 VOperating Temperature Topr 0 -+70 °cStorage Temperature TIIa - 55 -+150 °c- With respect to VSS (SYSTEM GND)[NOTE] Permanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operatingconditions. If these conditions are exceeded. it- could aftect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee -5.0V±5%, Vss - OV, Ta" 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitRES 4.0 - VeeInput "High" VoltageV1HVOther Inputs· 2.0 - VeeInput "Low" Voltage All Inputs· VIL -0.3 - 0.8 VP40 - P47 - - 0.5Vi" = 0- 2.4VInput Load Current SCI lIinl- 0.8 mAEXTAL Vi" = 0- Vee - - 0.8Input Leakage Current NMI. IRQI, RES Ilinl Vi" = 0 - 5.25V - - 2.5 p.AThree State (Offset) P IO - P 17 , P30 - P37 - - 10Leakage Current P20 - P 24 II TS Vi" = 0.5 - 2.4V"- - 100P 30 "" P 37 I LOAD = -205 p.A 2.4 - -Output "High" Voltage P 40 - P 47 , E, SCI. SC 2 VOH I LOAD = -145 p.A 2.4 - - VOther Outputs I LOAD = -100 p.A 2.4 - -Output "Low" Voltage All Outputs VOL I LOAD = 1.6 rnA - - 0.5 VDarlington Drive Current P IO - P 17 -IOH V out = 1.5V 1.0 - 10.0 rnAPower Dissipation Po - - 1200 rnWInput CapacitanceVee StandbyP 30 - P 37 , P 40 - P 47 , SCI Vi" = OV, Ta = 25°C, - - 12.5CinOther Inputsf=1.0MHz 10.0- -Powerdown VSBB 4.0 - 5.25OperatingVSB 4.75 - 5.25Standby Current Powerdown ISBB VSBB = 4.0V - - 8.0 rnA-Except Mode Programming levels.p.ApFV42 eHITACHI

-----------------------------------------------------HD6801S0,HD6801S5• AC CHARACTERISTICSBUS TIMING (Vee = 5.0V±5%, Vss '"' OV, Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test ConditionHDS801S0 HDS801S5min typ max min typ maxCycle Time tCYC 1 - 10 0.8 - 10 /J.sAddress Strobe Pulse Width "High" PWASH 200 - - 150 - - nsAddress Strobe Rise Time tASr 5 - 50 5 - 50 nsAddress Strobe Fall Time tASf 5 - 50 5 - 50 nsAddress Strobe Delay Time tASO SO - - 30 - - nsEnable Rise Time ' ter 5 - 50 5 - 50 nsEnable Fall Time tEf 5 - 50 5 - 50 nsEnable Pulse Width "High" Time PW EH 450 - - 340 - - nsEnable Pulse Width "Low" Time PWEL 450 - - 350 - - nsAddress Strobe to Enable.Delay Time tASEO SO - - 30 - - nsAddress Delay Time tAD Fig. 1 - - 250 - - 260 nsAddress Delay Time for Latch (f = 1.0MHz) tAOL Fig. 2 - - 270 - - 260 nsData Set-up Write Time tosw 225 - - 115 - - nsData Set-up Read Time tOSR 80 - - 70 - - nsData Hold Time l Read tHR 10 - - 10 - - nsI Write tHW 20 - - 20 - -Address Set-up Time for Latch tASL 60 - - 50 - - nsAddress Hold Time for Latch tAHL 20 - - 20 - - nsAddress Hold Time tAH 20 - - 20 - - nsPeripheral Read I Non-Multiplexed Bus (tACCN) - - (510) - - (420)nsAccess TimeI Multiplexed Bus (tACCM) - - (600) - - (420)Oscillator stabilization Time tRC Fig. 10 100 - - 100 - - msProcessor Control Set-up Time tpcs Fig. 11 200 - - 200 - - nsUnitPERIPHERAL PORT TIMING (Vee = 5.0V ±S%, Vss = OV. Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitPeripheral Data Setup Time Port 1, 2,3,4 tpDSU Fig. 3 200 - - nsPeripheral Data Hold Time Port 1,2,3,4 tpDH Fig. 3 200 - - nsDelay Time, Enable Positive Transitionto 053 Negative TransitionDelay Time, Enable Positive Transitionto 053 Positive TransitiontOS01 Fig. 5 - - 350 nstOSD2 Fig. 5 - - 350 nsDelay Time, Enable NegativeTransition to Peripheral Data Port 1, 2*,3,4 tpwD Fig. 4 - - 400 nsValidDelay Time, Enable Negative*Transition to Peripheral Port 2**, 4 tCMOS Fig. 4 - - 2.0 lASCMOS Data ValidInput Strobe Pulse Width tpWIS Fig. 6 200 - - nsInput Data Hold Time port 3 tlH Fig. 6 50 - - nsInput Data Set-up Time Port 3 tIS Fig. 6 20 - - ns**'Okn pull up register required for Port 2~HITACHI 43

H06801 SO,H06801 55TIMER, SCI TIMING (Vee" 5.0V ±5%, vss" OV, Ta = 0"'" +70°C, unless otherwise noted.)Item Symbol Test Condition minTimer Input Pulse Width tpWT 2tcvc+200Delay Time, Enable Positive Transition toTimer OuttTOD Fig. 7 -SCI Input Clock Cycle tSCYC 1SCI Input Clock Pulse Width tpwsCK 0.4typ max Unit- - ns- 600 ns- - tCYC- 0.6 tScYcMODE PROGRAMMING (Vee· 5.0V ±5%, VSS'" OV, T8 - 0"'" +70°C, unless otherwise noted.)Item Symbol Test Condition minMode Programming Input "Low" Voltage VMPL -Mode Programming Input "High" Voltage VMPH 4.0RES " Low" Pulse Width PWRSTL Fig. 8 3.0Mode Programming Set-up Time tMPS 2.0Mode Programming l m Rise Time ~ 11ls 0tMPHHold Time I m Rise Time < 11ls 100typ max Unit- 1.7 V- - V- - tcyc- - tcyc- -ns- -~---------------------t~----------------------~Address Strobe(AS)2.2VEnable(E)R/VV Aa-A15(Sell' (Port4)MCUWriteDo-D,.A.-A,(Port 3)MCU Read0.-0" A.-A,(Port 3)44Figure 1 Expanded Multiplexed Bus Timing_HITACHI

-----------------------------------------------------HD680150,HD680155EnableCEIO.5V., I PWEL~2~k--tAD---tEr--tEt-tAH--()2.2V)f-0.6~Address Valid1\J~-tosw--_t_MCU Write0.-0,(Port 3).2.2V ,..J Data Valid0.6V\"-tOSR-_IHR-hACCNI .M~~~~:d------------------------------------------2._0_V

HD6801SO,HD6801S5----------------------------------------------------Enable(E)TimerCounter ____ ...J '-~~-..,;,;......., '-__ _P lIOutputFigure 7 Timer Output TimingI~,I:;':: 1.----....;.:::;~"1I:...-----~rFigure 8 Mode Programming TimingVeeTest Point CO)-----l.. 30pFrla) CMOS LoadFigure 9 Bus Timing Test LoadsmRL.Z.ZkllTlSt Point152074 ®0' EQuiv.C RC· SOpF fM p .. -P.,. p •• -p ... E. SC .. SC,• 30pF fM p •• -p".p .. -p,.R: ~~g ::~ k.:"p'.';."r.:~;'.~E.SC .. 5C,Ib) TTL LoadLM' Ins"uc'ion -IIn,,,nll__ .~.~~_~n.-~~~~~~~_~"-_~~~~~ ~_~n.~~~~_"~~,,-~~_~~__iiiO.*----..,NIiI~1IUf. ~~~-------------------------------------------------------In .. 'n.I~r_--_v---..,.--~r_-'""'~-'V'---~-""",...-~--'V'---..,.-"""\,..--v_-~~-_v--V"'-0 .... uIJl __ ~ __ ~"__-"~_.".~-""-....J"-_~~_.A __ "" __ ..... ~ _ _''__ ..... ''_ _ _'''~_A_~~_In,,,no' AfiV *IROz .... Internal Interrupt \,, ___________________ ~E $\\\\\\\\\\\\\\\ ~\\\\\\\\\\\\\\\1-Figure 10 Interrupt,SequenceLrLfl. ~ fl[l..flI;':Ii.~2Ii:':'V---""', )0\ ------------11 'I " I.------------'AC--------~--.. -'''CSVa: •. 7SV ~__ • dO t 1I: __ o;:,.v~ -I'CII _____"U ------"""1,Iol-------------I- ......::.'.''":' %§\\\w\%\%\\\t _\\\\S\\\\§\S\\\\\\~~ ~ ... lUI FFFE ~ FIn,.,nII AfIR 1'I&~~rtS~S\rtS~$~~rtS'f'S\:rtS~ijrtS"&~~~ .... S ... ~I"'IS~S'\..'\\:I"'IS:'\'S...\\I"'ISI"'l'\~S'\...S .. S~~rtS ... S .. \\~SI"'lSYiW'--------------------~:=x::=r-~___B\1NO,VllodFigure 11 Reset Timing46_HITACHI

-----------------------------------------------------HD6801S0,HD6801S5• SIGNAL' DESCRIPTIONS• Vee.nd VssThese two pins are used to supply power and ground to thechip. The voltage supplied will be +5 volts ±5%.• XTAL.mt EXTALThese connections are for a parallel resoll .• ( fundamentalcrystal. AT cut. Divide by 4 circuitry is included with theinternal clock. so a 4 MHz crystal may be used to run thesystem at 1 MHz. The divide by 4 circuitry allows for use of theinexpensive 3.58 MHz Color TV crystal for non·time criticalapplications. Two 22pF capacitors are needed from the twocrystal pins to ground to insure reliable operation. EXT AL maybe driven by an external clock source at a 4 MHz rate to run at1 MHz with a 40/60% duty cycle. It is not restricted to 4 MHz,IS it wnI divide by 4 any frequency less than or equal to 4 MHz.XTAL must be grounded if an external clock is used. Thefollowing are the recommended crystal parameters:~ItemNominal Crystal Parameter4MHz 5MHzCo 7 pF max. 4.7 pF max.Rs 6Onmax. 3OnWp.XTAL~--~-----'CJE)(TAL~-"'...,tL2 Jr CL1Figure 12 Crystal InterfaceCL 1 ., CL2 = 22pF :t 20%(3.2 - 5MHz)[Note] These are representativeAT cut parallel resonancecrystal parameters.• Reset (RES)This input is used to reset and start the MCU from a powerdown condition, resulting from a power failure or an initialstartup of the processor. On power up, the reset must be held"Low" for at least 100 ms. During operation, REs, whenbrought "Low", must be held "Low" at least 3 clock cycles.When a "High" level is detected, the MCV does the following:I) All the higher order address lines will be forced "High".2) I/O Port 2 bits 2, I, and 0 are latched into programmedcontrol bits PC2, PC 1 and PCO.3) The last two ($FFFE, $FFFF) locations in memory willbe used to load the program addressed by the programcounter_4) The interrupt mask bit is set, must be cleared before theCPU can recognize maskable interrupts.• Enable (E)This supplies the external clock for the rest of the systemwhen the internal oscillator is used. It is a single phase, TTLcompatible clock, and will be the divide by 4 result of the'crystal frequency. It will drive one TTL load and 90 pF.• Non·Maskable Interrupt (NMI)A low·going edge on this input requests that a non·maskable·interrupt sequence be generated within the processor. As withinterrupt Request signal, the processor will complete the currentinstruction that is being executed before it recognizes the NMIsignal. The interrupt mask bit in the Condition Code Registerhas no effect on NMI.In response to an NMI interrupt, the Index Register, ProgramCounter, Accumulators, and Condition Code Register are storedon the stack. At the end of the sequence, a 16·bit address willbe loaded that points to a vectoring address located in memorylocations $FFFC and $FFFD. An address loaded at these loca·tions causes the CPU to branch to a non·maskable interruptservice routine in memory.A 3.3 kn external resistor to Vee should be used forwire·OR and optimum control of interrupts.Inputs IRQl and NMI are hardware interrupt lines that aresampled during E and will start the interrupt routine on theE following the completion of an instruction.• Vee StMldbyThis pin wnI supply +5 volts ±5% to the standby RAM on thechip. The first 64 bytes of RAM wnI be maintained in the powerdown mode with 8 mA current max. The circuit of figure 13can be utilized to assure that Vee Standby does not go belowV SBB during power down.To retain information in the RAM during power down thefollowing procedure is necessary:I) Write "0·· into the RAM enable bit, RAM E. RAM E is bit6 of the RAM Control Register at location $0014. Thisdisables the standby RAM, thereby protecting it at powerdown.2) Keep Vee Standby greater than VSBB.Vee Standbyi'_,LI'"J,Figure 13 Battery Backup for Vee Standby• Interrupt Request (lRQl)This level sensitiv~ input requests that an interrupt sequencebe generated within the machine. The processor will wait until itcompletes the current instruction that it being executed beforeit recognizes the request. At that time, if the interrupt mask bitin the Condition Code Register is not set, the'ml\chine will beginan interrupt sequence. The Index Register, Progr;un Counter,Accumulators, and Condition Code Register are stored on thestack. Next the CPU will respond to the interrupt request bysetting the interrupt mask bit "High" so that no further mask·able interrupts m~y occur. At the end of the cycle, a 16-bitaddress will be loaded that points to a vectoring address which islocated in memory locations $FFF8 and $FFF9. An addressloaded at these locations causes the CPU to branch to an inter·rupt routine in memory.The IRQl requires a 3.3 kSl external resister to Vee whichshould be used for wire·OR and optimum control of inte'!!!!pts.Internal Interrupts will use an internal interrupt line (IRQ,).This interrupt will operate the same as IRQl except that it willuse the vector address of $FFFO through $FFF7. ~ willhave priority over IRQ 2 if both occur at the same time. TheInterrupt Mask Bit in the condition code register masks bothinterrupts (See Table 1)._HITACHI 47

HD6801S0,HD6801S5---------------------------------------------------HighestPriorityLowestPriorityTable 1 Interrupt Vector LocationVectorInterruptMSB LSBFFFE FFFF rnFFFC FFFD NMIFFFA FFFB Software Interrupt (SWIIFFF8 FFF9 IRQ, (or IS3)FFF6 FFF7 ICF (Input Capture)PFF4 FFF5 OCF (Output Compare)FFF2 FFF3 TOF (Timer Overflow)FFFO FFF1 SC, (RDRF + ORFE + TORE)-• PORTSThere are four I/O ports on the HD6801S MCU; three 8-bitports and one 5-bit port. There are two control lines associatedwith one of the 8-bit ports. Each port has an associated writeonly Data Direction Register which allows each I/O line to beprogrammed to act as an input or an output·. A "1" iii thecorresponding Data Direction Register bit will cause that I/Oline to be an output. A "0" in the corresponding Data DirectionRegister bit will cause that I/O line to be an input. There arefour ports: Port 1, Port 2, Port 3, and Port 4. Their addressesand the addresses of their Data Direction registers are given inTable 2.• The only exception is bit 1 of Port 2, which can either be datainput or Timer output.The following pins are available in the Single Chip Mode, andare associated with Port 3 only.• Input Strobe (lS3) (SCI)This sets an interrupt for the processor when the IS3 Enablebit is set. As shown in Figure 6 Input Strobe Tim.!!!B, IS3 willfall tIS minimum after data is valid on Port 3. If IS3 Enable isset in the I/O Port 3 Control/Status Register, an interrupt willoccur. If the latch enable bit in the I/O Port 3 Control/StatusRegister is set, this strobe will latch the input data from anotherdevice when that device has indicated that it has valid data.• Output Strobe (Oft) (SC2 )This signal is used by the processor to strobe an externaldevice, indicating valid data is on the I/O pins. The timing forthe Output Strobe is shown in Figure 5 I/O Port 3 Control/Status Register is discussed in the following section.The following pins are available in the Expanded Modes.• ReadlWrite (RM) (SC 2 )This TTL compatible output signals the peripherals andmemory devices whether the CPU is in a Read ("High") or aWrite ("Low") state. The normal standby state of this signal isRead ("High"). This output is capable of driving one TTL loadand 90 pF.• 1/0 Strobe (iOS) (SCI)In the expanded non-multiplexed mode of operation, lOSinternally decodes A9 through Au as zero's and As as a one.This allows external access of the 256 locations from $0100 toSOIFF. The timing diagrams are shown as figure 2.• AcIdren Strobe (AS) (SCI)In the expanded multiplexed mode of operation addressstrobe is output on this pin. This signal is used to latch the 8LSB's of address which are multiplexed with data on Port 3. An8-bit latch is utilized in conjunction with Address Strobe, asshoWl\ in figure 19. Expanded Multiplexed Mode. AddressStrobe siplals the latch when it is time to latch the address linesso the lines can become data bus lines during the E pulse. Thetiming for this singal is shown in Figure I of Bus Timing. ThisIipal is also used to disable the address from the multiplexedbus allowing a deselect time, tASD before the data is enabled tothe bus.48 eHITACHITable 2 Port and Data Direction Register AddressesPortsPort AddressData DirectionRegister Addrass1/0 Port 1 $0002 $00001/0 Port 2 $0003 $00011/0 Port 3 $0006 $00041/0 Port 4 $0007 $0005• I/O Port 1This is an 8-bit port whose individual bits may be defined asinputs or outputs by the corresponding bit in its data directionregister. The 8 output buffers have three-state capability,allowing them to enter a high impedance state when the.peripheral data lines are used as inputs. In order to be readproperly, the voltage on the input lines must be greater than 2.0V for a logic "I" and less than 0.8 V for a logic "0". As out·puts, these lines are TTL compatible and may also be used asa source of up to 1 rnA at 1.5 V to directly drive a Darlingtonbase. After Reset, the I/O lines are configured as inputs. In allthree modes, Port 1 is always parallel I/O.• 1/0 Port 2This port has five lines that may be defined as inputs oroutputs by its data direction register. The 5 output buffers havethree-state capability, allowing them to enter a high impedancestate when used as an input. In order to be read properly, thevoltage on the input lines must be greater than 2.0 V for alogic "1" and less than 0.8 V for a logic "'0". As outputs, thisport has no internal pullup resistors but will drive TTL inputsdirectly. For driving CMOS inputs, external pullup resistors arerequired. After Reset, the I/O lines are configured as inputs.Three pins on Port 2 (pins 10, 9, and 8 of the chip) are usedto program the mode of operation during reset. The values ofthese pins at reset are latched into the three MSB's (bits 7, 6,and 5) of Port 2 which are read only. This is explained in theMode Selection Section.In all three modes, Port 2 can be configured as I/O andprovides access to the Serial Communications Interface and theTimer. Bit 1 is the only pin restricted to data input or Timeroutput.• 1/0 Port 3 ,...This is an 8-bit port that can be configured as I/O, a data bus,or an address bus multiplexed with the data bus - depending onthe mode of operation hardware programmed by the user atreset. As a data bus, Port 3 is bi-directional. As an input forperipherals, it must be supplied regular TTL levels, that is,greater than 2.0 V for a logic "I "and less than 0.8 V for a logic"0".

---------------------------HD680150,HD680155Its TTL compatible three-state output buffers are capable ofdriving one TTL load and 90 pF. In the Expanded Modes, afterreset, the data direction register is inhibited and data flowdepends on the state of the R/W line. The input strobe (lS3)and the output strobe (083) used for handshaking are explainedlater.In the three modes, Port 3 assumes the following characteristics:Single Chip Mode: Parallel Inputs/Outputs as programmed byits associated Data Direction Register. There are two controllines associated with this port in this mode, an input strobe andan output strobe, that can be used for handshaking. They arecontrolled by the I/O Port 3 Control/Status Register explainedat the end of this section. Three options of Port 3 operationsare sumarized as follows: (I) Port 3 input data can be latchedusing IS3 (SC,) as a control signal, (2) OS3 can be generated byeither an CPU read or write to Port 3's Data Register, and (3)and IRQI interrupt can be enabled by an IS3 negative edge.Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.Expanded Non-Multiplexed Mode: In this mode, Port 3becomes the data bus (Do -D,).Expanded Multiplexed Mode: In this mode, Port 3 becomesboth the data bus (Do -D,) and lower bits of the address bus(Ao"" A,). An address strobe output is true when the address ison the port.I/O PORT 3 COt,aTROL/STATUS REGISTER7 6IS3TS3mer.$OOOF FLAG ENABLE5 4 3 2X OSS LATCH X XENABLEBit 0; Not used.Bit I; Not used.Bit 2; Not used.Bit 3; LATCH ENABLE. This controls the input latch for I/OPort 3. If this bit is set "High" the input data will belatched with the falling edge of the Input Strobe, IS3.This bit is cleared by reset, and the latch is "re-opened"with CPU read Port 3.Bit 4; OSS. (Output Strobe Select) This bit will select if theOutput Strobe should be generated at ()S3 (SC 2 ) by awrite to I/O Port 3 or a read of I/O Port 3. When this bitis cleared the strobe is generated by a read Port 3. Whenthis bit is set the strobe is generated by a write Port 3.Bit 5; Not used.Bit 6; IS3 IRQ, ENABLE. When set, interrupt will be enabledwhenever IS3 FLAG is set; when clear, interrupt isinhibited. This bit is· cleared by RES.Bit 7; IS3 FLAG. This is a read only status bit that is set bythe falling edge of the input strobe, IS3 (SC,). It iscleared by a read of the Control/Status Register followedby a read or write of I/O Port 3. Reset will clearthis bit.• I/O Port 4This is an 8-bit port that can be configured as I/O or asaddress lines depending on the mode of operation. In order tobe read properly, the voltage on the input lines must be greaterthan 2.0 V for a logic "I" and less than 0.8 V for a logic "0".As outputs, each line is TTL compatible and can drive 1 TTLoXload and 90 pF. After reset, the lines are configured as inputs.To use the pins as addresses, therefore, they should beprogrammed as outputs. In the three modes, Port 4 assumes thefollowing characteristics:Single Chip Mode: Parallel Inputs/Outputs as programmed byits associated Data Direction Register.Expanded Non-Multiplexed Mode: In this mode, Port 4 isconfigured as the lower order address lines (Ao-A,) by writingone's to the data direction register. When all eight address linesare not needed, the remaining lines, starting with the mostsignificant bit, may be used as I/O (inputs only).Expanded Multiplexed Mode: In this mode, Port 4 isconfigured as the higher order address lines (As-Au) by writingone's to the data direction register. When all eight addresslines are not needed, the remaining lines, starting with the mostSignificant bit, may be used as I/O (inputs only).• OPERATION MODESThe mode of operation that HD680lS will operate in afterReset is determined by hardware that the user must wire on pins10,9, and 8 of the chip. These pins are the three LSD's (I/O 2,I/O I, and I/O 0 respectively) of Port 2. They are latched intoprogrammed control bits PC2, PC I, and PeO when reset goeshigh. I/O Port 2 Register is shown below.PORT 2 DATA REGISTER6543210$00031 PC21 PC1 I PCO 11/0 411/0311/0211/0 1 1110 0 IAn example of external hardware that could be used forMode Selection is shown in Fig. 14. The HDI40S3B providesthe isolation between the peripheral device and MCV duringReset, which is necessary if data conflict can occur betweenperipheral device and Mode generation circuit.As bits 5, 6 and 7 of Port 2 are read only, the mode cannotbe changed through software. The mode selections are shown inTable 3.The HD6801S is capable of operating in three basic modes;(I) Single Chip Mode, (2) Expanded Multiplexed Mode (compatiblewith HMCS6800 peripheral family) (3) Expanded Non­Multiplexed Mode.• Single Chip ModeIn the Single Chip Mode the Ports are configured for I/O.This is shown in Figure 16 the single Chip Mode. In thismode, Port 3 will have two associated control lines, an inputstrobe and an output strobe for handshaking data.• Expanded Non-Multiplexed ModeIn this mode the HD680 I S will directly address HMCS6800peripherals with no external logic. In this mode Port 3 becomesthe data bus. Port 4 becomes the Ao""A, address bus or partialaddress and I/O (inputs only). Port 2 can be parallel I/O, serialI/O, Timer, or any combination of them. Port 1 is parallel 1/0only. In this mode the HD6801S is expandable to 256 locations.The eight address lines associated with Port 4 may besubstituted for 1/0 (inputs only) if a fewer number of addresslines will satisfy the application (See Figure 17).eHITACHI 49

HD6801S0,HD6801S5---------------------------------------------------Vee(A !AI RI RI1 T TABCX.Y. X~ Z. YXIY IZ6AESHD6801S8P 20 (PCOI9P 2I(PC1110p •• (PC21ZICCI ??? ModeControl~ SwitchInhJrHD14053B[NOTES)Figure 14 Recommended Circuit for Mode Selection11 Mode 7 as shown21 AC"Aeset time constant31 A I=10knTruth TableInhABCBinary to 1-of-2Decoder withInhibitXoo-----------------~U-~~4-~Xlcr------------------4C~+-~--~yoo-------------------~~~~~ylo---------------------~~~~Zoo-----------------------~~~Zlcr------------------------~~xyzControl InputInhibit000000001CSelectOn SwitchB A HD14053B0 0 0 Z. Yo XII0 0 1 Zo Vo XI0 1 0 Zo Y I Xo0 1 1 ZO Y I XI1 0 0 ZI Yo X.1 0 1 ZI Vo 'XI1 1 0 ZI Y I Xo1 1 1 ZI VI XIX X X -Figure 15 HD14053B Multiplexers/DemultiplexersVeeVee2 7 40 EnableEnablePort 18110 LinesPort 381/0 LinesPort 18 Parallel 1/0Port 38 Data LinesPort 48110 LinesVssPort 25110 LinesSCITimerFigure 16 HD6801S MCU Single-Chip Mode50 ~HITACHIPort 25 Parallel 1/0SCITimerVssPort 4To 8 AddressLines or To8110 Lines(Inputs On IV)Figure 17 HD6801S MCU Expanded Non-Multiplexed Mode

--------------------------- HD680150,HD680155• Expanded Multiplexed ModeIn this mode Port 4 becomes higher order address lines withan alternative of substituting some of the address lines for I/O(inputs only). Port 3 is the data bus multiplexed with the lowerorder address lines differentiated by an output called AddressStrobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or anycombination of them. Port I is 8 Parallel I/O lines. In this modeit is expandable to 65k words. (See Figure 18).VeeEnable• Lower order Address Bus LatchesSince the data bus is multiplexed with the lower orderaddress bus in Port 3, latches are required to latch those addressbits. The 74LS373 Transparent octal D-type latch can be usedwith the HD6801S to latch the least significant address byte.Figure 19 shows how to connect the latch to the HD6801S.The output control to the 74LS373 may be connected toground.Port 181/0 LinesPort 251/0 LinesSCITimerVss8 LinesMultiplexedData/AddressPort 4To 8 AddressLines or To8 I/O Lines(Inputs Only)Figure 18 HD6801S MCU Expanded Multiplexed ModeGNOPort 3Address/DataAS[IG OC0, 0,74 LS3730 8 0 81 Add,", A. -A,1 ~~ 0.-0,OutputControlLLLHFunction TableEnable OutputG 0 0H H HH L LL X 0 0X X ZFigure 19 Latch Connection• Mode and Port Summary MCU Signal DescriptionThis section gives a description of the MCU signals for the various modes. SCI and S~ are signals which vary with the modethat the chip is in.MODEPORT 1 PORT 2 PORT3 PORT 4Eight Lines Five Lines Eight Lines Eight LinesSCI ~SINGLE CHIP I/O I/O I/O I/O 1S3 (I) 083(0)ADDRESS BUSEXPANDED MUX I/O I/O(Ao-A 7 ) ADDRESS BUS·DATA BUS (As-AIs )AS(O) RAY(O)(0 0 -0 7 )EXPANDED NON-MUX I/O I/ODATA BUS ADDRESS BUS·(0 0 -0 7 ) (Ao-A 7 )-These lines can be substituted for I/O (Input Only) starting with the most significant address line.I - Input m .. Input Strobe SC" Strobe Controlo .. Output ~ .. Output Strobe AS .. Address StrobeR/W .. Read/WriiiiOS .. I/O Select10S(0)RM(O)_HITACHI 51

HD6801S0,HD6801S5---------------------------------------____________ ___Table 3 Mode Selection SummaryModeP a(PC2)7 H6 H5 H4 H3 L2 L1 L0 LP Z1(PC1)LEGEND:I -InternalE - ExternalMUX - MultiplexedNMUX - Non-MultiplexedL - Logic "0"H - Logic "1"HHLLHHLLP zn(PCO)HLHLHLHLROMRAMInterrupt Bus OperatingVectors Mode ModeI I I I Single ChipI I I MUX(6) Multiplexed/Partial DecodeI I I NMUX(6) Non-Multiplexed/Partial Decode1(2) 1(1) I I Single Chip TestE E E MUX Multiplexed/No RAM & ROME I E MUX Multiplexed/RAMI I E MUX Multiplexed/RAM & ROMI I 1(3) MUX Multiplexed Test(NOTES)1) Internal RAM is addressed at $XX802) Internal ROM is disabled3) RES vector is external for 2 cycles after RES goes "High"4) Addresses associated with Ports 3 and 4 are considered external in Modes 0,1,2, and 35) Addresses associated with Port 3 are considered external in Modes 5 and 66) Port 4 default is user data input; address output is optional by writing to Port 4Data Direction Register• MEMORY MAPSThe MCV can provide up to 6Sk byte address space dependingon the operating mode. A memory map for each operatingmode is shown in Figure 20. The rust 32 locations of each mapare reserved for the MCV's internal register area, as shown inTable 4. With exceptions as indicated.• INTERRUPT FLOWCHARTThe Interrupt flow chart is depicted in Figure 24 and is commonto every interrupt excluding reset.Table 4 Internal Register AreaRegisterAddressPort 1 Data Direction Register··· 00Port 2 Data Direction Register··· 01Port 1 Data Register 02Port 2 Data Register 03Port 3 Data Direction Register"· 04·Port 4 Data Direction Register··· 05··Port 3 Data Register 06·Port 4 Data Register 07··Timer Control and Status Register 08Counter (High Byte) 09Counter (Low Byte)OAOutput Compare Register (High Byte)OBOutput Compare Register (Low Byte)OCInput Capture Register (High Byte) 00Input Capture Register (Low Byte)OEPort 3 Control and Status RegisterOF·Rate and Mode Control Register 10Transmit/Receive Control and Status Register 11Receive Data Register 12Transmit Data Register 13RAM Control Register 14Reserved 15-1F• External address in Mode!..2. 1,2,3, 5,6; cannot beaccessed in Mode 5 (No. lOS)•• External addresses in Modes 0, 1, 2, 3••• 1 =Output, O"Input·52 _HITACHI

---------------------------HD6801S0,HD6801S5HD6801SModeoHD6801SMode1Multiplexed Test mode$0000(1)} Internal Registers$001F$0080$OOFF}IExternal Memory SpaceInternal RAMExternal Memory SpaceMultiplexed/RAM & ROM$0000(1)Internal Registers$OOlFExternal Memory Space$0080Internal RAM$OOFFExternal Memory Space$F8oo$FFFF(2)Internal ROMInternal Interrupt Vectors(2$F8oo$FFEF$FFFO$FFFF '--___ ~JInternal ROMExternal Interrupt Vectors[NOTES!1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and $OF2) Addresses $FFFE and $FFFF are consideredexternal if accessed within 2 cycles alter apositive edge of RES and internal at all othertimes.3) After 2 CPU cycles, there must be no overlappingof internal and external memoryspaces to avoid driving the data bus with morethan one device.4) This mode is the only mode which may be usedto examine the interrupt vectors "in internalROM using an external Reset vector.[NOTES]1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and$OF.2) Internal ROM addresses $FFFO to $FFFF arenot usable.Figure 20 HD6801S Memory MapseHITACHI 53

HD6801S0,HD6801S5-----------------------------------------------------HD6801SMode2HD6801SMode3Multiplexed/RAM$0000(1)Internal Registers$001FExternal Memory Space$0080Internal RAMMultiplexed/No RAM or ROM$0000(1)} Internal Registers$001F$OOFFExternal Memory SpaceExternal Memory Space$FFFOa----,.;}$FFFF '-____ External Interrupt Vectors[NOTE]1) Excludes the following addresses which maybe used externally: $04, $Os, $06, $07, and$OF.$FFFO ~----I$FFFF '-___-'} External Interrupt Vectors[NOTE]1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and$OF.Figure 20 HD6801S Memory Maps(Continued)54_HITACHI

.-------------HD6801S0,HD6801S5HD6801S 4ModeHD6801S 5ModeSingle Chip Test$0000Internal Registers$OO1FNon-Multiplexed/Partial Decode$0000(1)} Internal Registers$001FUe(1)(4)$0080Internal RAM}$OOFF$0100 }_~__... External Memory Space$01FFL$F8oo$XX80$XXFF}Internal RAMInternal Interrupt Vectors$FFFFInternal ROMInternal Interrupt Vectors[NOTES)1) The internal ROM is disabled.2) Mode 4 may be changed to Mode 5 withouthaving to assert RESET by writing a "1" intothe PCO bit of Port 2 Data Register.31 Addresses As to A •• are treated as "don'tcares" to decode internal RAM.4) Internal RAM will appear at $XX80 to $XXFF.[NOTES)1) Excludes the following addresses which maynot be used externally: $04, $06, and $OF.(No 105)2) This mode may be entered without goingthrough RES by using Mode 4 and subsequentlywriting a "1" into the PCO bit ofPort 2 Data Register.3) Address lines Ao -A. will not contain addressesuntil the Data Direction Register for Port 4has been written with "1's" in the appropriatebits. These address lines will assert "1's" untilmade outputs by writing the Data DirectionRegister.Figure 20 HD6801S Memory Maps (Continued)eHITACHI 55

HOS801 SO,H06801 55 -----HD6801S 6ModeHD6801S7ModeMultiplexed/Partial DecodeSingle Chip$0000(1)$001F$0080$OOFFInternal RegistersExternal Memory SpaceInternal RAM$0080$ooFFInternal RAMExternal Memory Space$F8oo$FFFFjlnternal ROMInternal Interrupt Vectors$F800$FFFFInternal ROMInternal Interrupt Vectors[NOTES]11 Excludes the following address which may beused externally: $04, $06, $OF.21 Address lines A.-A .. will not containaddresses until the Data Direction Register forPort 4 has been written with "1's" in theappropriate bits. These address lines willassert "1's" until made outputs by writing the"Data Direction Register.Figure 20 HD6801S Memory Maps (Continued)56 $ HITACHI

.-------------H06801 SO,HOS801 S5• PROGRAMMABLE TIMERThe H0680lS contains an on-chip 16-bit programmabletimer which may be used to perform measurements on an inputwaveform while independently generating an output waveform.Pulse widths for both input and output signals may vary from afew microseconds to many seconds. The timer hardware consistsof• an 8-bit control and status register,• a 16-bit free running counter,• a 16-bit output compare register, and• a 16-bit input capture registerA block diagram of the timer registen is- shown in Figure 21.• Free Running Counter ($OOO9:000A)The key elen:tent in the programmable timer is a 16-bit freerunning counter which is driven to increasing values by E (Enable).The counter value may be read by the CPU software atany time. The counter is cleared to zero on RES and may beconsidered a read-only register with one exception. Any CPUwrite to the counter's address ($09) will always result in presetvalue of $FFF8 being loaded into the counter regardless of thevalue involved in the -write. This preset figure is intended fortesting operation of the part, but may be of value in someapplications.• Output Compare Register ($OOOB:OOOC)The Output Compare Register is a 16-bit read/write registerwhich is used to control an output wavefonn. The contents ofthis register are constantly compared with the current value ofthe free running counter. When a match is found, a flag is set(OCF) in the Timer Control and Status Register (TCSR) and thecurrent value of the Output Level bit (OLVL) in the TCSR isclocked to the Output Level Register. Providing the DataDirection Register for Port 2, Bit 1 contains a "I" (Output),the output level register value will appear on the pin for Port 2Bit I. The values in the Output Compare Register and Outputlevel bit may then be changed to control the output level on thenext compare value. The Output Compare Register is set to$FFFF during RES. The Compare function is inhibited forone cycle following a write to the high byte of the OutputCompare Register to insure a valid 16-bit value is in the registerbefore a compare is made.• Input Capture Register ($OOOO:OOOE)The Input Capture Register is a 16-bit read-only register usedto store the current value of the free running counter when theproper transition of an external input signal occurs. The inputtransition change required to trigger the counter transfer iscontrolled by the input Edge bit (IEDG) in the TCSR. The DataDirection Register bit for Port 2 Bit 0, should· be clear (zero)in order to gate in the external input signal to the edge detectunit in the timer.* With Port 2 Bit 0 conIJgured as an output and set to "1". theexternal input will still be seen by the edge detect unit.• Timer Control and Status Register (TCSR) ($0008)The Timer Control and Status Register consists of an 8-bitregister of which all 8 bits are readable but only the low order 5bits may be written. The upper three bits contain read-onlytimer status information and indicate that:• a proper transition has taken place on the input pin with asubsequent transfer of the current counter value to theinput capture register.• a match has been found between the value in the freerunning counter and the output compare register, and• when $0000 is in the free running counter.Each of the flags' may be enabled onto the H06801 internalbus (IRQ2) with an individual Enable bit in the TCSR. If theHD6801S Internal BusOutput I"pu tLevel EdgeBit 1 Sit 0Port 2 Port 2Figure 21Block Diagram of Programable Timer_HITACHI 57

HD6801S0,HD6801S5 -----Timer Control and Status Register6 5 4 3 2 1 0ICF I OCF TOF I EICI I EOCI I ETOIIIEDG I OLVLI $0008I-bit in the HD6801S Condition Code Register has been cleared,a priority vectored interrupt will occur corresponding to the flagbit(s) set. A description for each bit follows:Bit 0 OLVL Output Level - This value is clocked to the outputlevel register on a successful output compare. Ifthe DDR for Port 2 bit 1 is set, the value willappear on the output pin.Bit I IEDG Input Edge - This bit controls which transition ofan input will trigger a transfer of the counter tothe input capture register. The DDR for Port 2 Bito must be cle;l( for this function to operate. IEDG= 0 Transfer takes place on a negative edge("High" ·to-"Low" transition).IEDG = I Transfer takes place on a positive edge("Low"-to-"High" transition).Bit 2 ETOI Enable Timer Overflow Interrupt - When set, ti1isbit enables IRQ2 to occur on the internal bus for aTOF interrupt; when clear the interrupt is inhibited.Bit 3 EOCI Enable Output Compare Interrupt -Bit 4 EICIWhen set,this bit enables IRQ2 to appear on the internal busfor an output compare interrupt; when clear theinterrupt is inhibited.Enable Input Capture Interrupt- When set, thisbit enables IRQ2 to occur on the internal bus for. an input capture interrupt; when clear the interruptis inhibited.Bit 5 TOF Timer Overflow Flag - This read-only bit is setwhen the counter contains $FFFF. It is cleared bya read of the TCSR (with TOE set) followed by anCPU read of the Counter ($09).Bit 6 OCF Output Compare Flag - This read-only bit is setwhen a match is found between the outputcompare register and the free running counter. It iscleared by a read of the TCSR (with OCF set)followed by an CPU write to the output compareregister ($OB or SOC).Bit 7 ICF Input Capture Flag - This read-only status bit isset by a proper transition on the input; it is clearedby a read of the TCSR (with ICF set) followed byan CPU read of the Input Capture Register ($OD).• SERIAL COMMUNICATIONS INTERFACEThe H06801S contains a full-duplex asynchronous serialcommunications interface (SCI) on chip. The controllercomprises a transmitter and a receiver which operate independentlyor each other but in the same data format and at the samedata rate. Both transmitter and receiver communicate with theCPU via the data bus and with the outside world via pins 2, 3,and 4 of Port 2. The hardware, software, and registers are explainedin the following paragraphs.• Wake-Up FeatureIn a typical multi-processor application, the softwareprotocol will usually contain a destination address in the initialbyte(s) of the message. In order to permit non-selected MCU'sto ignore the remainder of the message, a wake-up feature isincluded whereby all further interrupt processing may beoptionally inhibited until the beginning of the next message.When the next message appears, the hardware re-enables (or"wakes-up") the for the next message. The "wake-up" isautomatically triggered by a string of ten consecutive 1 's whichindicates an idle transmit line. The software protocol mustprovide for the short idle period between any two consecutivemessages.• Programmable OptionsThe following features of the HD6801 S serial I/O section areprogrammable:· format - standard mark/space (NRZ)• Clock - external or internal• baud rate- one of 4 per given CPU tP2 clock frequency orexternal clock x8 input• wake-up feature - enabled or disabled• Interrupt requests - enabled or masked individually fortransmitter and receiver data registers• clock output - internal clock enabled or disabled to Port2 (Bit 2)• Port 2 (bits 3 and 4) - dedicated or not dedicated to serialI/O individually for transmitter and receiver.• Serial Communications HardwareThe serial conununications hardware is controlled by 4registers as shown in Figure 22. The registers include:• an 8-bit control and status register• a 4-bit rate and mode control register (write only)• an 8-bit read only receive data register and• an 8-bit write only transmit data register.In addi"tion to the four registers, the serial I/O section utilizesbit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 ofPort 2 is utilized if the internal-clock-out or external-clock-inoptions are selected .Transmit/Receive Control and Status (TRCS) RegisterThe TRCS register consists of an 8-bit register of which all 8bits may be read while only bits 0-4 may be written. Theregister is initialized to $20 on RES. The bits in the TRCSregister are defined as follows:Transmit/Receive Control and Status Register76543210IRDREloRFEITDREI RIE I RE I TIE I TE I wu IADDR:SO01158 eHITACHI

--------------------------HD6801S0,HD6801S5Bit 7 Rate and Mode Control Register Bit 0I I CCI I CCO I SSI I SSO ISloTransmit/Receive Control and Status RegisterPort 2Receive Shift RegisterClock 10Bit ....----'~------~2I+----ETxBit 124Figure 22 Serial I/O RegistersBitOWU "Wake-up" on Next Message - set by HD6801Ssoftware and cleared by hardware on receipt often consecutive 1 's or reset of RE flag. It shouldbe noted that RE flag should be set in advance ofCPU set of WU flag.Bit 1 TE Transmit Enable - set by HD6801 S to producepre am ble of nine consecutive 1 's and to enablegating of transmitter output to Port 2, bit 4regardless of the DDR value corresponding to thisbit; when clear, serial I/O has no effect on Port 2bit 4.TE set should be after at least one bit time of datatransmit rate from the set-up of transmit datarate and mode.Bit 2 TIE Transmit Interrupt Enable - when set, will permitan IRQ2 interrupt to occur when bit 5 (TDRE) isset; when clear, the TDRE value is masked fromthe bus.Bit 3 RE Receiver Enable - when set, gates Port 2 bit 3 toinput of receiver regardless of DDR value for thisbit; when clear, serial I/O has no effect on Port 2bit 3.Bit 4 RIE Receiver Interrupt Enable - when set, will permitan IRQ2 interrupt to occur when bit 7 (RDRF) orbit 6 (ORFE) is set; when clear, the interrupt ismasked.Bit 5 TORE Transmit Data Register Empty - set by hardwarewhen a transfer is made from the transmit dataregister to the output shift register. The TDRE bitis cleared by reading the status register, thenwriting a new byte into the transmit data register,TDRE is initialized to 1 by RES.Bit 6 ORFE Over-Run-Framing Error - set by hardware whenan overrun or framing error occurs (receive only).An overrun is defined as a new byte received withlast byte still in Data Register/Buffer. A !ramingerror has occurred when the byte boundaries in bitstream are not synchronized to bit counter. TheORFE bit is cleared by reading the status register,then reading the Receive Data Register, or byRES.Bit 7 RORF Receiver Data Register Fun - Set by hardwarewhen a transfer from the input shift register to thereceiver data register is made. The RDRF bit iscleared by reading the status register, then readingthe Receive Data Register, or by RES.Rate and Mode Control RegisterThe Rate and Mode Control register controls the followingserial I/O variables:• Baud rate• format• clocking source, and• Port 2 bit 2 configurationThe register consists of 4 bits all of which are write-only andcleared on RES. The 4 bits in the register may be considered asa pair of 2-bit fields. The two low order bits control the bit ratefor internal clocking and the remaining two bits control theformat and clock select logic. The register definition is asfollows:Rate and Mode Control Register7 6 5 4 3 2 ox x x x I eel I eeo I S51 sso ADDR: $0010~HITACHI 59

HD6801S0,HD6801S5-----------------------------------------------------Bit 0 SSO Speed Select - These bits select the Baud rate forBit 1 SS1 the internal clock. The four rates which may beselected are a function of the CPU f/>2 clockfrequency. Table 5 lists the available Baud rates.Bit 2 CCO Clock Control and Format Select - this 2-bit fieldBit 3 CC1 controls the format and clock select logic. Table 6defines the bit field.SS1 : SSOTable 5 SCI Bit Times and RatesXTAL 2.4576 MHz 4.0 MHz 4.9152 MHz*E 614.4 kHz 1.0 MHz 1.2288 MHz0 0 E+ 16 26 #5/38,400 Baud 16 #5/62,500 Baud 13 #5/76,800 Baud0 1 E + 128 208 #5/4,800 Baud 128 #5/7812.5 Baud 104.2 #s/9,600 Baud1 0 E + 1024 1.67 ms/600 Baud 1.024 ms/976.6 Baud 833.3 #5/1,200 Baud1 1 E + 4096 6.67 ms/150 Baud 4.096 ms/244.1 Baud 3.33 ms/300 Baud* HD6801S5 OnlyTable 6 SCI Format and Clock Source ControlCC1:CCO Format Clock Source Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 40 0 - - - ** **0 1 NRZ Internal Not Used ** **1 0 NRZ Internal Output* ** **1 1 NRZ External Input ** *** Clock output is available regardless of values for bits RE and TE.Bit 3 is used for serial input if RE = "1" in TRCS; bit 4 is used for serial output if TE = "1" in TRCS.Internally Generated ClockIf the user wishes for the serial I/O to furnish a clock, thefollowing requirements are applicable:• the values of RE and TE are immaterial.• Cel, CCO must be set to 10• the maximum clock rate will be E + 16.• the clock will be at Ix the bit rate and will have a risingedge at mid-bit.Externally Generated ClockIf the user wishes to provide an external clock for the serialI/O, the following requirements are applicable:• the CCI, CCO, field in the Rate and Mode Control Registermust be set to II,• the external clock must be set to 8 times (x8) the desiredbaud rate and• the maximum external clock frequency is .I.O MHz.• Serial OperationsThe serial I/O hardware should be initialized by theHD6801S software prior to operation. This sequence willnormally consist of;• writing the desired operation control bits to the Rate andMode Control Register and• writing the desired operational control bits in the Transmit!Receive Control and Status Register.The Transmitter Enable (TE) and Receiver Enable (RE) bitsmay be left set for dedicated operations.Transmit OperationsThe transmit operation is enabled by the TE bit in theTransmit/Receive Control and Status Register. This bit whenset, gates the output of the serial transmit shift register to Port 2Bit 4 and takes unconditional control over the Data DirectionRegister value for Port 2, Bit 4.Following a RES the user should configure both the Rateand Mode Control Register and the Transmit/Receive Controland Status Register for desired operation. Setting the TE bitduring this procedure initiates the serial output by firsttransmitting a nine-bit preamble of 1 'so Following the preamble,internal synchronization is established and the transmittersection is ready for operation.At this point one of two situation exist:1) if the Transmit Data Register is empty (TORE = 1), acontinuous string of ones will be sent indicating an idleline, or,2) if data has been loaded into the Transmit Data Register(TORE = 0), the word is transferred to the output shiftregister and transmission of the data word will begin.During the transfer itself, the 0 start bit is first transmitted.Then the 8 data bits (beginning with bit 0) followed by the stopbit, are transmitted. When the Transmitter Data Register hasbeen emptied, the hardware sets the TORE flag bit.If the HD6801S fails to respond to the flag within the propertime, (TORE is still set when the next normal transfer from th~parallel data register to the serial output register should occur)then a I will be sent (instead of a 0) at "Start" bit time,followed by more 1 's until more data is supplied to the dataregister. No O's will be sent while TORE remains a 1.60 eHITACHI

------------------------------------------------------HD6801S0,HD6801S5Receive OperationThe receive operation is enabled by the RE bit which gates inthe serial input through Port 2 Bit 3. The receiver sectionoperation is conditioned by the contents of the Transmit/Receive Control and Status Register and the Rate and ModeControl Register.The receiver bit interval is divided into 8 sub-intervals forinternal synchronization. In the NRZ Mode, the received bitstream is synchronized by the first 0 (space) encountered.The approximate center of each bit time is strobed duringthe next 10 bits. If the tenth bit is not a I (stop bit) a framingerror is assumed, and bit ORFE is set. If the tenth bit as a I, thedata is transferred to the Receive Data Register, and interruptflag RDRF is set.·If RDRF is still set at the next tenth bit time,ORFE will be set, indicating an over-run has occurred. When theHD6801S responds to either flag (RDRF or ORFE) by readingthe status register followed by reading the Data Register, RDRF(or ORFE) will be cleared.• RAM CONTROL REGISTERThis register, which is addressed at $0014, gives statusinformation about the standby RAM. A 0 in the RAM enablebit (RAM E) will disable the standby RAM, thereby protectingit at power down if Vee Standby is held greater than V SBBvolts, as explained previously in the signal description for VeeStandby.RAM Control Register$00141 s~ I RAM. 1 X I X I X I X I X I X IBit 0 Not used.Bit 1 Not used.Bit 2 Not used.Bit 3 Not used.Bit 4 Not used.Bit 5 Not used.Bit 6 RAME The RAM Enable control bit allows the user theability to disable the standby RAM. This bit is setto a logic "1" by RES which enables the standbyRAM and can be written to one or zero uner programcontrol. When the RAM is disabled, data isread from external memory.Big 7 STBY The Standby Power bit is cleared when the stand-PWR by voltage is removed. This bit is a read/write statusflag that the user can read which indicates thatthe standby RAM voltage has been applied, andthe data in the standby RAM is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD6801S is upward object code compatible with theHD6800 as it implements the full HMCS6800 instruction set.The execution times of key instructions have been reduced toincrease throughout. In addition, new instructions have beenadded; these include 16-bit operations and a hardware multiply.Included in the instruction set section are the following:• CPU Programming Model (Figure 23)• AddreSsing modes• Accumulator and memory instructions - Table 7• New instructions• Index register and stack manipulations instructions - Table8• Jump and branch instructions - Table 9• Condition code register manipulation instructions - Table 10• Instructions Execution times in machine cycles - TableII• Summary of cycle by cycle operation - Table 12• Op codes Map - Table 13• CPU Programming ModelThe programming model for the HD6801S is shown in Figure23. The double (D) accumulator is physically the same as theAccumulator A concatenated with the Accumulator B so thatany operation using accumulator D will destroy information inA and B.8·81t Accumulators A and BOr 16-Blt Double Accumulator 015 X 0 Index Register IX)11 15 SP 0 Stack POinter ISP)11 15 PC ol Program Counter IPC)Figure 23 CPU Programming Model.Condition Code Register ICCR)Carry/Borrow from MSBOverflowZeroNegativeInterruptHalf Carry IFrom Bit 3)• CPU Addressing ModesThe HD6801S eight-bit microcomputer unit has sevenaddress modes that can be used by a programmer, with theaddressing mode a function of both the type of instruction andthe coding within the instruction. A summary of the addressingmodes for a particular instruction can be found in Table 11along with the associated instruction execution time that isgiven in machine cycles. With a clock frequency of 4 MHz, thesetimes would be microseconds.Accumulator (ACCX) AddressingIn accumulator only addressing, either accumulator A oraccumulator B is specified. These are one-byte instructions.Immediate AddressingIn immediate addressing, the operand is contained in thesecond byte of the instruction except LDS and LDX which havethe operand in the second and third bytes of the instruction.The CPU addresses this location when it fetches the immediateinstruction for execution. These are two or three-byte instructions._HITACHI 61

HD6801S0,HD6801S5---------------------------------------------------Table 7 Accumulator & Memory InstructionsAddressing ModesOperations Mnemonic Boolean/IMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic OperationCondition CodeRegister5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V CAdd ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+B-.A t • t t t tADDB CB 2 2 DB 3 2 EB 4 2 FB 4· 3 B+M-.B t • t t t tAdd Double ADDD C3 4 3 03 5 2 f3 6 2 F3 6 3 A:B+M:M+1-.A:B • • t t t tAdd Accumulators ABA 1B 2 1 A + B-. A t • t t t tAdd With Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-'A t • : t t :ADCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-'B t • t t t :AND ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A·M-.A• • t t R•AN DB C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M-. B• • : : R •Bit Test BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M • • : t R •BIT B C5 2 2 05 3 2 E5 4 2 F5 4 3 B·M • • : t R •Clear CLR 6F 6 2 7F 6 3 00-. M • • R S R RCLRA 4F 2 1 OO-A • • RS R RCLRB 5F 2 1 00 -. B • S R RRCompare CMPA 81 2 2 91 3 2 A1 4 2 B1 4 3 A-M • • : t t tCMPB C1 2 2 01 3 ,2 E1 4 2 F1 4 3 B-M • • t t t tCompareCBA 11 2 1 A-B• • t t t tAccumulatorsComplement, 1's COM 63 6 2 73 6 3 M-.M• • t t R SCOMA 43 2 1 A -.A• • t t R SCOMB 53 2 1 B -.B • • t t R SComplement, 2's NEG 60 6 2 70 6 3 OO-M-'M • • t t

------------------------------------------------------HD6801S0,HD6801S5Table 7 Accumulator & Memory Instructions (Continued)OperationsMnemonicAddressing ModesIMMED. DIRECT INDEX EXTEND IMPLIEDOP - # OP - # OP - #Shift Left ASL 68 6 2ArithmeticAS LADouble ShiftLeft, ArithmeticASLBASLDShift Right ASR 67 6 2ArithmeticASRAASRBShift Right LSR 64 6 2LogicalLSRADouble ShiftRight LogicalLSRBLSRDStore STAA 97 3 2 A7 4 2Accumu latorSTAB 07 3 2 E7 4 2Store DoubleAccumulatorSTD DO 4 2 ED 5 2Subtract SUBA 80 2 2 90 3 2 AO 4 2SUBB CO 2 2 DO 3 2 EO 4 2Double Subtract SUBD 83 4 3 93 5 2 A3 6 2SubtractAccumulatorsSBASubtract SBCA 82 2 2 92 3 2 A2 4 2With CarrVSBCB C2 2 2 02 3 2 E2 4 2TransferAccumulatorsTABTBATest Zero or TST 60 6 2MinusTSTATSTB. .The Condition Code Re(jlster notes are listed after Table 10 •OP787774B7F7FDBOFOB3B2F270BooleanlArithmetic OperationCondition CodeRegister5 4 3 2 1 0- # OP - # H I N Z V C6 3M} _ • • t t @t48 2 1 A [}o-IIIIIIIII-o • • t f @fa c b1 bO58 2 1• • f f ~f05 3 1 ~ A~~ iiJ A~~ II 1-0 f~t· • tA1 AQ B1 BQ6 3• • f t @ t47 2 1 ~} C?I IIIIIIJ~ - • • t t ® ta b157 2 1 • • f f @ t6 3~}o-oi I -• • t t ~ t44 2 1 1IIIIIJ-oQ • • t f @ t· · t t @ f54 2 1a b1---+04 3 1 0-01 ACC AI ACCa ~• • R A1 AO B1 BOf @ t4 3 A- M • • t t R •4 3 B_M• • f t R •A_ M5 3• • t f RB_M+1•4 3 A-M_A• • f t t t4 3 B-M-+B • • t t f t6 3 A:B-M:M+1-+A:B• • t f f t10 2 1 A-B-+A• • f t t t4 3 A-M-C-+A• • f t t t4 3 B-M-C-+B • f t f t16 2 1 A-+B • • t t R 17 2 1 B-+A • ·f t R •6 3 M-OO • • t f R R40 2 1 A -00 • • t f R R50 2 1 B - 00 • • t t R RDirect AddressingIn direct addressing, the address of the operand is contained~ the second byte of the instruction. Direct addressing allowsthe user to directly address the lowest 256 bytes in the machineLe., locations zero through 255. Enhanced execution times areachieved by storing data in these locations. In most configurations,it should be a random access memory. These are two-byteinstructions.Extended AddressingIn extended addressing, the address contained in the secondbyte of the instruction is used as the higher eight-bits of theaddress of the operand. The third byte of the instruction is usedas the lower eight-bits of the address for the operand. This is anabsolute address in memory. These are three-byte instructions.Indexed AddressingIn indexed addressing, the address contained in the secondbyte of the instruction is added to the index register's lowesteight bits in the CPU. The carry is then added to the higherorder eight bits of the index register. This result is then used toaddress memory. The modified address is held in a temporaryaddress register so there is no change to the in~ex register. Theseare two-byte instructions.I mplied AddressingIn the implied addressing mode the instruction gives theaddress (Le., stack pointer, index register, etc.). These areone-byte instructions.Relative AddressingIn relative addressing, the address contained in the secondbyte of the instruction is added to the program counter's lowesteight bits plus two. The carry or borrow is then added to thehigh eight bits. This allows the user to address data within arange of -126 to + 129 bytes of the present instruction. Theseare two-byte instructions.eHITACHI 63

HD6801S0,HD6801S5-----------------------------------------------------• New InstructionsIn addition to the existin~ 6800 Instruction Set, the following new instructions areincorporated in the 8D6801S Microcomputer.ABX Adds the 8·bit unsigned accumulator B to the 16·bit X·Register taking into accountthe po~ible carry out of the low order ,""Ie of the X.Register.ADDD Add!> the double precision ACCD· to 1 •. double precision value M:M+I and placesthe results in ACCD.ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit isloaded from the most significant bit of ACCD.LDD Loads the contents of double precision memory location into the doubleaccumulator A:B. The condition codes are set according to the data.LSRD Shifts ail bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bitis loaded from the least significant bit to ACCD.MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain al6-bit unsigned number in A:B, ACCA contains MSB of result.PSHX The contents of the index register is pushed onto the stack at the address containedin the stack pointer. The stack pointer is decremented by 2.PULX The index register is pulled from the stack' beginning at the current addresscontained in the stack pointer +1. The stack pointer is incremented by 2 in total.STD Stores the contents pf double accumulator A:B in memory. The contents of ACCDremain unchanged.S~BD Subtracts the contents of M:M + 1 from the contents of double accumulator ABand places the result in ACCD.BRN Never branches. If effect, this instruction can be considered a two byte NOP (Nooperation) requiring three cycles for execution.CPXInternal processing modified to permit its use with any conditional branch in·struction.-ACCD is the 16 bit register (A:B) formed by concatenating the A and 8 accumulators. The A-accumulatoris the most significant byte.Table 8 Index Register and Stack Manipulation InstructionsPointer OperationsMnemonicAddressing ModesBooleanlIMMED. DIRECT INDEX EXTND IMPLIED Arithmetic OperationOP- # OP - # OP - # OP- # OP - #Compare Index Reg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 X-M: M+ 1Decrement Index Reg DEX 09 3 1 X-1-XDecrement Stack Pntr DES 34 3 1 SP -1- SPIncrement Index Reg INX 08 3 1 X+1-XIncrement Stack Pntr INS 31 3 1 SP + 1 - SPLoad Index Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M- XH. (M+ 1)- XLLOid Stack Pntr LOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M- SPH. (M+1)-SPLStore Index Reg STX OF 4 2 EF 5 2 FF 5 3 XH - M. XL .... (M + 1)Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH .... M.SP L - (M+1)Index Reg -+ Stack Pntr TXS 35 3 1 X-1-SPStack Pntr -+ Index Reg TSX 30 3 1 SP+1-XAdd ABX 3A 3 1 B+X-XPush Data PSHX 3C 4 1 XL - Map. SP - 1 - SPXH .... Map. SP -1 - SPPull Data PULX 38 5 1 SP + 1- SP. Map - XHThe Condition Code Register notes are listed after Table 10.SP + 1- SP. Map -XLCondition CodeRegister5 4 3 2 1 0HI N Z V C• • t J t J• • • J • •• • • • • •• • • J • •• • • • • •• • 'j) J R •• • (f) J R •• • (f) J R •• • (j) J R •• • • • • •• • • • • •• • • • • •• • • • • •• • • • • •64 $ HITACHI

------------------------------------------------------HD6801S0,HD6801S5Table 9 Jump and Branch InstructionsOperationsMnemonicRELATIVEAddressing Modes--DIRECT INDEX EXTND IMPLIEDBranch TestCondition CodeRegister5 4 3 2 1 0OP- # OP - # OP - # OP - # OP - # H I N 2 V CBranch Always BRA 20 3 2 None • • • • • •Branch Never BRN 21 3 2 None • • • • • •Branch If Carry Clear BCC 24 3 2 C=O • • • • • •Branch If Carry Set BCS 25 3 2 C=1 • • • • • •Branch If • Zero BEQ 27 3 2 2=1·• • • •Branch If .. Zero BGE 2C 3 2 NV=O • • • • •Branch If > Zero BGT 2E 3 2 2 + IN 0 V) = 0 • • • •Branch If Higher BHI 22 3 2 C+Z=O • • • • Branch If < ZerO BlE 2F 3 2 2 + IN 0 V) = 1 • • • • • •Branch If lower OrBlS 23 3 2 C+Z = 1Slme• • • • • •Branch If < Zero BlT 20 3 2 N

HD6801S0,HD6801S5---------------------------------------------------66ABAABXAOCADDAOOOANDASLASLOASRBCCBCSBEQBGEBGTBHIBITBLEBLSBLTBMIBNEBPLBRABRNBSRBVCBVSCBACLCCLICLRCLVCMPCOMCPXDAADECDESDEXEORINCINSTable 11Instruction Execution Times in Machine CyclesCC Imme- 0" Ex- In- 1m-A X diete Ifect tended dexed plied• • • • • 2•••••2•2••,••••••••••••••••••2••2••2•••2••2242•••••••••2••••••••••••••••2•4••••2•••3353•••••••••3••••••••••••••••3•5••••3•••44646•6••••••4••••••••••••••6•466•6••46••44646•6••••••4••••••••••••••6•466•6••46•3•••••3•••••••••••••••••••222•2•••2•33••3Relative•••••••••333333•33333333633••••••••••••••INXJMPJSRLOALOOLOSLOXLSRLSROMULNEGNOPORAPSHPSHXPULPULXROLRORRTIRTSSBASBeSECSEISEVSTASTOSTSSTXSUBSUBOSWITABTAPTBATPATSTTSXTXSWAIeHITACHIAcex ~~a:- Direct te~;~ d~~~•••••••2••2••3•4•22••••••••••••••••••2••••••2333•••••2•••••••••2•••••••24•••••••••••53444•••••3•••••••••3•••344435••••••••••3645556••6•4••••66•••4•••455546•••••6•••3645556••6•4••••66•••4•••455546•••••6••Implied3•••••••310•2••4•5••1052•222••••••122222•339Relative•••••••••••••••••••••••••••••••••••••••••

-----------------------------------------------------HD6801S0,HD6801S5• Summary of Cycle by Cycle OperationTable 12 provides a detailed description of the informationpresent on the Address Bus, Data Bus, and the Read/Write line(R/W) during each cycle for each instruction.This information is useful in comparing actual with expectedresults during debug of both software and hardware as thecontrol program is executed. The information is categorized ingroups according to addressing mode and number of cycles perinstruction. (In general, instructions with the same addressingmode and number of cycles execute in the same manner; exceptionsare indicated in the table).Table 12 Cycle by Cycle OperationAddress Mode &InstructionsAddresl> BusData BusIMMEDIATEADC EORADD LDAAND ORABIT SBCCMP SUB2 12Op Code Address 1Op Code Address + 1 1Op CodeOperand DataLDSLDXLDDCPXSUBDADDD3 1234 1234Op Code Address 1Op Code Address + 1 1Op Code Address + 2 1Op Code Address 1Op Code Address + 1 1Op Code Address + 2 1Address Bus F F F F 1Op CodeOperand Data (High Order Byte)Operand Data (Low Order Byte)Op CodeOperand Data (High Order Byte)Operand Data (Low Order Byte)Low Byte of Restart VectorDIRECTADC EORADD LDAAND ORABIT SBCCMP SUB3 123Op Code Address 1Op Code Address + 1 1Address of Operand 1Op CodeAddress of OperandOperand DataSTALDSLDXLDDSTSSTXSTDCPXSUBDADDDJSR3 1234 12344 12345 123455 12345Op Code Address 1Op Code Address + 1 1Destination Address 0Op Code Address 1Op Code Address + 1 1Address of Operand 1Operand Address + 1 1Op Code Address 1Op Code Address + 1 1Address of Operand 0Address of Operand + 1 0Op Code Address 1Op Code Address + 1 1Operand Address 1Operand Address + 1 1Address Bus FFFF 1Op Code Address 1Op Code Address + 1 1Subroutine Address 1Stack Pointer 0Stack Pointer + 1 0Op CodeDestination AddressData from AccumulatorOp CodeAddress of OperandOperand Data (High Order Byte)Operand Data (Low Order Byte)Op CodeAddress of OperandRegister Data (High Order Byte)Register Data (Low Order Byte)Op CodeAddress of OperandOperand Data (High Order Byte)Operand Data (Low Order Byte)Low Byte of Restart VectorOp CodeIrrelevant DataFirst Subroutine Op CodeReturn Address (Low Order Byte)Return Address (High Order Byte)(Continued)$ HITACHI67

HD6801S0,HD6801S5-----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusINDEXEDJMPADC EORADD lOAAND ORABIT SBCCMP SUBSTALOSLOXLDDSTSSTXSTDASl lSRASR NEGClR ROlCOM RORDEC TST*INCCPXSUBDADDDJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 OpCodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 low Byte of Restart VectorIndex Register Plus Offset 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 low Byte of Restart VectorIndex Register Plus Offset 0 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 low Byte of Restart VectorIndex Register Plus Offset 1 Operand Data (High Order Byte)Index Register Plus Offset + 1 1 Operand Data (low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 low Byte of Restart VectorIndex Register Plus Offset 0 Operand Data (High Order Byte)Index Register Plus Offset + 1 0 Operand Data (low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 low Byte of Restart VectorIndex Register Plus Offset 1 Current Operand DataAddress Bus F F F F 1 low Byte of Restart VectorIndex Register Plus Offset 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 low Byte of Restart VectorIndex Register + Offset 1 Operand Data (High Order Byte)Index Register +,Dffset + 1 1 Operand Data (low Order Byte)Address Bus F F F F 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 low Byte of Restart VectorIndex Register + Offset 1 First Subroutine Op CodeStack Pointer 0 Return Address (low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)(Continued)*In the TST instruction, R/W line of the sixth cycle is "1"level, and AB = FFFF, DB = low Byte of Reset Vector.68_HITACHI

------------------------------------------------------HD6801S0,HD6801S5Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusEXTENDEDJMPADC EORADD LOAAND ORABIT SBCCMP SUBSTALOSLOXLDDSTSSTXSTDASL LSRASR NEGCLR ROLCOM RORDEC TST*INCCPXSUBDADDDJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 Op CodeOp Code Address + 1 1 Jump Address (High Order Byte)Op Code Address + 2 1 Jump Address (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 21 Address of Operand (Low Order Byte)Address of Operand 1 i Operand DataIOp Code Address1 lOp CodeOp Code Address + 1 I 1 I Destination Address (High Order Byte)Op Code Address + 2 1 Destination Address (Low Order Byte)Operand Destination Address 0 Data from AccumulatorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand Data (High Order Byte)Address of Operand + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 0 Operand Data (High Order Byte)Address of Operand + 1 0 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Current Operand DataAddress Bus F F F F 1 Low Byte of Restart VectorAddress of Operand 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Operand Address (High Order Byte)Op Code Address + 2 1 Operand Address (Low Order Byte)Operand Address 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Address Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Subroutine (High Order Byte)Op Code Address + 2 1 Address of Subroutine (Low Order Byte)Subroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)"In the TST instruction, R/IN line of the sixth cycle is"1" level, and AB=FFFF, DB=Low Byte of Reset Vector,(Continued)eHITACHI 69

HD6801S0,HD6801S5--------~-------------------------------------------Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusIMPLIEDABA DAA SECASl DEC SEIASR INC SEVCBA lSR TABClC NEG TAPCli NOP TBAClR ROl TPAClV ROR TSTCOM SBAABXASlDlSRDDESINSINXDEXPSHA.PSHBTSXTXSPULAPUlBPSHXPUlXRTSWAI**2 123 1233 1233 1233 1233 1233 1233 1234 12344 12345 123455 123459 1234Op Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataAddress Bus F F F F 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataAddress Bus FFFF 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionPrevious Register Contents 1 Irrelevant DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionAddress Bus F F F F 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 0 Accumulator DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 1 Irrelevant DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionAddress Bus FFFF 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 1 Irrelevant DataStack Pointer + 1 1Op Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataStack Pointer 0 Index Register (low Order Byte)Stack Pointer - 1 0 Index Register (High Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataStack Pointer 1 Irrelevant DataStack Pointer + 1 1 Index Register (High Order Byte)Stack Pointer +2 1 Index Register (low Order Byte)Op Code Address 1 OpCodeOp Code Address + 1 1 Irrelevant DataStack Pointer 1 Irrelevant DataStack Pointer + 1 1 Address of Next Instruction(High Order Byte)Stack Pointer + 2 1 Address of Next Instruction(low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 0 Return Address (low Order Byte)Stack Pointer - 1 0 Return Address (H igh Order Byte)70eHITACHI(Contmued)

------------------------------------------------------HD6801S0,HD6801S5Table 12 Cvcle by Cycle Opeiation (Continued)Address Mode &CycleR/WCycle~Address BusInstructions # LineData BusWAin 5 Stack Pointer - 2 0 Index Register (low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code RegisterMUL 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data.3 Address Bus FFFF 1 Low Byte of Restart Vector4 Address Bus F F F F 11 Low Byte of Restart Vector5 Address Bus F F FF 1 Low Byte of Restart Vector6 Address Bus F F F F 1 Low Byte of Restart Vector7 Address Bus F F F F 1 Low Byte of Restart Vector8 Address Bus F F FF 1 Low Byte of Restart Vector9 Address Bus FFFF 1 Low Byte of Restart Vector10 Address Bus F F F F 1 Low Byte of Restart VectorRTI 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Contents of Cond. Code Reg.from Stack5 Stack Pointer + 2 1 Contents of Accumulator Bfrom Stack6 Stack Pointer + 3 1 Contents of Accumulator Afrom Stack7 Stack Pointer + 4 1 Index Register from Stack(High Order Byte)8 Stack Pointer + 5 1 Index Register from Stack(Low Order Byte)9 Stack Pointer + 6 1 Next Instruction Address fromStack (High Order Byte)10 Stack Pointer + 7 1 Next Instruction Address fromStack (Low Order Byte)SWI 12 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 0 Return Address (low Order Byte)4 Stack Pointer - 1 0 Return Address (High Order Byte)5 Stack Pointer - 2 0 Index·Register (Low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code Register10 Stack Pointer - 7 1 I rrelevant Data11 Vector Address FFFA (Hex) 1 Address of Subroutine(High Order Byte)12 Vector Address FFF8 (Hex) 1 Address of Subroutine(Low Order Byte)"While the MCU is in th. "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than theoriginal contents of the $tack Pointer. Contrary to the HD6800. none of the ports are driven to the high impedance state by a WAI instruction.(Continued)$ HITACHI 71

HD6801S0,HD6801S5---------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusRELATIVEBCC BHT BNEBCS BlE BPlBEQ BlS BRABGE BlT BVCBGT BMT BVSBRNBSR3 1236 123456Op Code Address 1 OpCodeOp Code Address + 1 1 Branch OffsetAddress Bus FFFF 1 low Byte of Restart VectorOp Code Address 1 OpCodeOp Code Address + 1 1 Branch OffsetAddress Bus FFFF 1 low Byte of Restart VectorSubroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 Return Address (low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)• Sum....-y of Undefined Instruction OperationsThe HD6801 S has 36 undefmed instructions. When these arecarried out, the contents of Register and Memory in MeVchange at random.When the op codes (4E, SE) are used to execute, the MeVcontinues to increase the program counter and it will not stopuntil the Reset signal enters. These op codes are used to test theLSI.Table 13 Op codes MapHD6801S MICROCOMPUTER INSTRUCTIONSACCAor SPACCB or XOP ACC ACCINo EXTCODE A BIMM j olRjlNo j EXT~ ---- ----SBA BRA TSX NEG SUB0001 1 NOP CBA BRN INS CMP0010 2---~ BHI PULA (+1) SBe0011 3 BLS PULB (+1) COM . SUBD (+2) : ADDD (+2)·0100 4 LSRo (+1) ~ Bce DES LSR AND0101 6 ASLo (+1) ~ BCS TXS BIT0110 6 TAP TAB BNE PSHA -----=-=-=-= ROR LOA0111 7 TPA TBA BEQ PSHB ASR/I STA ~ STA----1000 8 INX (+11 ~ BVC PULX (+2) ASL EOR1001 9 oEX(+lI DAA BVS RTS (+2) ROL Aoe1010 A CLV ~ BPL ABX DEC ORA1011 B SEV ABA BMI RTI (+7) . ADD1100 C CLC ~ BGE PSHX (+1) INC : CPX (+2) LoD (+1)·LOX (+1)0000 0---IMM I DIR liND I EXT0000 0001 0010 0011 0100 0101 0110 0111 1000j1001j 1010j1011 1100 11101 11110111110 1 2 3 4 5 6 7 8 I 9 I A I B C I 0 I ElF1101 0 SEC/BLT MUL (+7) TST~~IJSR (+2) t:: (+1~ STD(+lI1110 E Cli / BGT WAI(+6) --.. - JMP(-3) . LOS (+11·1111 F SEI ~ BlE SWI (+9) ClR ::. (+iil STS(+1) • (+1ij STX (+1)BYTE/CYCLE 112 1/2 2/3 1/3 1/2 1/2 2/6 3/6 2/2 I 2/3 1 2/4 1 3/4 2/2 I 2/3 I 2/4 I 3/40123456789ABC0EF[NOTES)1) Undefined Op codes are marked with ~ •2) I I indicate that the number in parenthesis must be added to the cycle count for that instruction.31 The instructions shown below are all 3 bytes and are marked with ......Immediate addressing mode of SUBD, CPX, LOS, Aooo, loD and lOX instructions, and undefined op codes(8F, CD, CFI.41 The Op codes (4E, 6EI are 1 byte/oo cycles instructiOns. and are marked with .......72eHITACHI

e%~()!·SCI = TIE-TORE + RIE-(RORF + ORFE)......wFigure 24 Interrupt FlowchartVector-' PCfiIMi FFFC FFFOSWI FFFA FFFBIRQ. FFF8 FFF9ICF FFF6 FFF7OCF FFF4 FFF5TOF FFF2 FFF3SCI FFFO FFF1Non-Maskable InterruptSoftware InterruptMaskable Interrupt Request 1Input Capture InterruptOutpUt Compare InterruptTimer Overflow InterruptSCI Interrupt (TORE + RORF + ORFE)~C0)00o~fJ)p~C0)00o~fJ)C1I

HD6801S0,HD6801S5-----------------------------------------------------VeeVeeEnableEnableNMIPort 38 TransferLinesPort 18110LinesP"",181/0 linesPort 48110 LinesVSSPort 251/0 LinesSCI16 Bit TimerPorI 251/0 Lines "...-.,.' __ ~ __ I"'-""SCIVSSPor148110 lonesFigure 25 H068D1 S MCU Single-Chip Dual Processor ConfigurationHD6801SMCUAddressBusDataBusFigure 26 H06801 S MCU Expanded Non-Multiplexed ModeAddress BusData BusFigure 27 H06801 S MCU Expanded Multiplexed Mode74_HITACHI

HD6801VO,HD6801V5MCU (Microcomputer Unit)The HD6801V MCU is an 8-bit microcomputer system whichis compatible with the H06801S except the ROM size. TheHD6801V MCU is object code compatible with the H06800with improved execution times of key instructions plus severalnew 16-bit and 8-bit instructions including an 8x8 unsignedmultiply with 16-bit result. The HD680lV MCU can operate asa single chip microcomputer or be expanded to 65k words. TheHD6801V MCU is TTL compatible and requires one +5.0 voltpower supply. The H0680 1 V MCU has 4k bytes of ROM and128 bytes of RAM on chip. Serial Communications interface(SCI), and parallel I/O as well as a three function 16-bit timer.Features and Block diagram of the HD680lV include thefollowing:HD6801VOPHD6801V5P(DP-40)• FEATURES• Expanded HMCS6800 Instruction Set• 8 x 8 Multiply• On-Chip Serial Communications Interface (SCI)• Object Code Compatible With The HD6800 MPU• 16-Bit Timer• Single Chip Or Expandable To 65k Words• 4k Bytes Of ROM• 128 Bytes Of RAM (64 Bytes Retainable On PowerDown)• 29 Parallel I/O Lines And 2 Handshake Control Lines• Internal Clock/Divided-By-Four Circuitry• TTL Compatible Inputs And Outputs• Interrupt Capability• Compatible with MC6801 (except ROM size)• BLOCK DIAGRAM• PIN ARRANGEMENT0HD6801V(Top View)SC,sc,p)(\P"P"P 3~P"P ;\~P)6P"P"P"P"P"P"P.,P"P"Vee Standby....... --4-4--+--. P20Iooh~--+--' P2IJ.H~""""'P22,,*"",f-H-r-'" ~~!• TYPE OF PRODUCTSMCUBus TimingHD6801VOHD6801V51 MHz1.25 MHz$ HITACHI75

HD6801VO,HD6801V5------------------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee * -0.3-+7.0 VInput Voltage V 'n * -0.3 - +7.0 VOperating Temperature Topr 0 -+70 °cStorage Temperature TIIg - 55 -+150 °c* With re~pect to VSS (SYSTEM GND)[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operatingconditions. If these conditions are exceeded, it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee -S.OV±S%, Vss • OV, Ta - 0- +70°C, unless otherwise noted.)Input "High" VoltageInput "Low" VoltageItem Symbol Test Condition min typ max UnitRES 4.0 - VeeOther Inputs*V'HV2.0 - VeeEXTAL -0;3 - 0.6Other Inputs·VIL-0.3 - 0.8 VP40 - P47 - - 0.5Input load Current SCI IbnlVin =0-2.4V- -EXTAl Vin = 0- Vee - - 1.20.8 mAInput leakage Current NMI, IRQI, RES Ilinl Vin = 0 - 5.2SV - - 2.5 IJ.AThree State (Offset) P-,o - P 17 , P30 - P37 - - 10leaka.ge CurrentIITs.! Vin = 0.5 - 2.4VIJ.AP20 - P24- - 100P30 - P37 I LOAO = -2051J.A 2.4 - -Output "High" Voltage P 40 - P47 , E, SCI, SC2 VOH I LOAD = -1451J.A 2.4 - - VOther Outputs I LOAD = -100 IJ.A 2.4 - -Output "low" Voltage All Outputs VOL ILOAD = 1.6 mA - - 0.5 VDarlington Drive Current PIO - PI7 -IDH Vout = 1.5V 1.0 - 10.0 mAPower Dissipation Po - - 1200 mWInput CapacitanceVee StandbyP 30 - P37 , P 40 - P47 , SCI Vin = OV, Ta = 25°C, - - 12.5CinOther Inputsf = 1.0 MHz - -10.0Powerdown VSBB 4.0 - 5.25Operating VSB 4.75 - 5.25Standby Current Powerdown ISBB VSBB = 4.0 V - - 8.0 mA*Except Mode Programming Levels.pFV76$ HITACHI

-----------------------------------------------------HD6801VO,HD6801V5• AC CHARACTERISTICSBUS TIMING (Vee'" 5.0V±5%, Vss - OV, Ta· 0 - +70°C, unless otherwise noted.)HD6801VO HD6801V5Item Symbol Test ConditionUnitmin typ max min typ maxCycle Time tcyc 1 - 10 .0.8 - 10 p.sAddress Strobe Pulse Width "High" PWASH 200 - - 150 - - nsAddress Strobe Rise Time tASr 5 - 50 5 - 50 nsAddress Strobe Fall Time tASf 5 - 50 5 - 50 nsAddress Strobe Delay Time tASO 60 - - 30 - - nsEnable Rise Time tEr 5 - 50 5 - 50 nsEnable Fall Time tEf 5 - 50 5 - 50 nsEnable Pulse Width "High" Time PW EH 450 - - 340 - - nsEnable Pulse Width "Low" Time ,PW EL 450 - - 350 - - nsAddress Strobe to Enable Delay Time tAsEO 60 - - 30 - - nsAddress Delay Time tAD Fig. 1 - - 260 - - 260 nsAddress Delay Time for Latch tAOL Fig. 2 - - 270 - - 260 nsData Set-up Write Time tosw 225 - - 115 - - nsData Set-up Read Time tOSR 80 - - 80 - - nsI Read tHR 10 - - 10 - -Data Hold TimensI Write tHW 20 - - 20 - -Address Set-up Time for Latch tASL 60 - - 50 - - nsAddress Hold Time for Latch tAHL 20 - - 20 - - nsAddress Hold Time tAH 20 - - 20 - - nsPeripheral Read I Non-Multiplexed Bus (tACCN) - - (610) - - (410)nsAccess TimeI Multiplexed Bus (tACCM) - - (600) - - (410)Oscillator stabilization Time tRC Fig. 10 100 - - 100 - - msProcessor Control Set-up Time tpcs Fig. 11 200 - - 200 - - nsPERIPHERAL PORT TIMING (Vee = 5.0V ±5%, Vss = OV, Ta" 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitPeripheral Data Setup Time Port 1,2,3,4 tposu Fig. 3 200 - - nsPeripheral Data Hold Time Port 1, 2,3,4 tpOH Fig. 3 200 - - nsDelay Time, Enable Positive Transitiontos01 Fig. 5 350to 053 Negative Transition- - nsDelay Time, Enable Positive Transitionto 053 Positive Transition- - nstos02 Fig. 5 350Delay Time, Enable NegativeTransition to Peripheral Data Port 1, 2*,3,4 tpwo Fig.4 - - 400 nsValidDelay Time, Enable Negative*Transition to Peripheral Port 2**, 4 t CMOS Fig.4 - - 2.0 /JSCMOS Data ValidInput Strobe Pulse Width tpWIS Fig. 6 200 - - nsInput Data Hold Time port 3 tlH Fig. 6 50 - - nsInput Data Set-up Time Port 3 tiS Fig. 6 20 - - ns.... 'Okn pull up register required for Port 2eHITACHI 77

HD6801VO,HD6801V5------------------------------------------------------TIMER, SCI TIMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0'" +70°C, unless otherwise noted.)Item Symbol Test Condition minTimer Input Pulse Width tpWT 2tcvc+200Delay Time, Enable Positive Transition toTimer OuttTOo Fig. 7 -SCI Input Clock Cycle tScvc 1SCI Input Clock Pulse Width tpWSCK 0.4typ max Unit- - ns- 600 ns- - tcvc- 0.6 tScvcMODE PROGRAMMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0'" +70°C, unless otherwise noted.)Item Symbol Test Gondition minMode Programming Input "Low" Voltage VMPL -Mode Programming Input "High" Voltage VMPH 4.0RES "Low" Pulse Width PW RSTL Fig. 8 3.0Mode Programming Set-up Time tMPs 2.0Mode Programming I m Rise Time ~ lJ.ls 0tMPHHold Time I RES Rise Time < lJ.ls 100typ max Unit- 1.7 V- - V- - tcyc- - tcyc- -ns- -~---------------------t~----------------------~Address Strobe(AS)2.4VEnable(E)R/iN, Ar-A."(SC~ (Port4)MCU WriteDo -D? A. -A,(Port 3)tHRMCU Read0.-0,. A.-A,(Port 3)1+----ItACCM)---~78Figure 1 Expanded Multiplexed Bus Timing$ HITACHI

----------------------------------------------------HD6801VO,HD6801V51----------- teye ----------1ENIbIeeEl,1-----PWEL----II JtE,~A"Port4)R!IiI (SC21IO'S (set!-------.JMCU Writ..;e _______ -II-________ 2_._2V-C10.-0,(Port 3) O.6V 1'-____ +-+"11+----- etACCNI----.. 1MCU Read ___________________ 2_Ȯ_V.(10.-0,(Port 3)Figure 2 Expanded Non-Multiplexed Bus TimingO.SV t------""IEnable(E)p •• - P"p. o - p,.p .. -PO'Inputsp .. -P"Inputs"rMCURead"Port 3 Non-Latched Operation (LATCH ENABLE = OlFigure 3 Data Set-up and Hold Times(MCU Read)rMCU WriteEnable(E)~O.SVCMOStpwo tAll DataPort Outputs _______ .J(Note)11-" - --- 0.7 Vce~:!~ 08ta Valid1. 10 kU Pullup resistor required for Port 2 to reach 0.7 Vee~: ~~r~1~i~~~~e::'Ued above VeeFigure 4 Port Data Delay Timing(MCU Write)rMCU access of Port 3*Enable(E)Add ....8us053 .... -----* Access matches Output Strobe Select (OSS = 0, a read;OSS = 1, a write)Figure 5 Port 3 Output Strobe Timing(Single Chip Mode)PM -p ..Inputs ...::::.:.r-1& ..... ----~ ...... ~::.:.---Figure 6 Port 3 Latch Timing(Single Chip Mode)eHITACHI79

\~ .....HD6801VO,HD6801V5----------------------------------------------------Enable(E)TimerCounterp ..Output-----Figure 7 Timer Output TimingFigure 8 Mode Programming TimingVeeTest Point 0 .......---1.., 30pFImRL.2.2kOTest Point152074 ®or EqUiV.C Rlal CMOS LoadFigure 9 Bus Timing Test loadsIbl TTL LoadiRa,*-----""\~Or1Ra2 ~---------------------------------------------------------------------Data 8usJ\-....... ~--.J\:~...J~~~~~~~~~~~~~~~"-A~CC""!8~-=:=-"!-"-==', ~VOC~''''''''''''!'!VIC=tor~,..~ ..'!'''..... ~.~-Dot. MS8 LA .-.optI nl~' nal R iW* iR0 2-- Internal Interrupt_______________ .JI_t_Figure 10 Interrupt SequenceE ~\~\~\\\\\\\\\ ~\\\\\\\\\\\\\ ~ rtJl.JL[1..1LIl ~-5.2W _-l ----41~' ~,_ ~tI ~._V~ ~~-4-.75-V------------------,~ ______ ~ ~ ~ __RES , ..., ______________________ -t,4.OV t ....08::,::V ____ _A.:;,o.n;, M\\\\\\\%\\\\\\\~ SSSS\§\\\\\SSS~~ ~,on u. FFFE ~ FFFE'nto.n" RM \\\\\\\\\\\\\§\\\\N: ~\\\\\\\§\\\SS\\S\§\\S\\\y . ~ ::::x=:r-~;,':';~:~\\\\\\§\\\\\\%\~ I'MS\\\\\\\%\SS\\~ =pc:::x::x:PCB-PC.S PCo--PCl FI ...I .... lructionFigure 11 Reset Timing80_HITACHI

------------------------------------------------------HD6801VO,HD6801V5• SIGNAL DESCRIPTIONS• Vee and VssThese two pins are used to supply power and ground to thechip. The voltage supplied will be +5 volts ±5%.• XTAL and EXT ALThese connections are for a parallel resonant fundamentalcrystal, AT cut. Divide by 4 circuitry is included with theinternal clock, so a 4 MHz crystal may be used to run thesystem at 1 MHz. The divide by 4 circuitry allows for use of theinexpensive 3.58 MHz Color TV crystal for non-time criticalapplications. Two 22pF capacitors are needed from the twocrystal pins to ground to insure reliable operation. EXT AL maybe driven by an external TTL compatible clock source with a50% (±IO%) duty cycle. It will divide by 4 any frequency lessthan or equal to 5 MHz. XTAL must be grounded if an externalclock is used. The following are the recommended crystal parameters:Nominal Crystal ParameterItem~·4 MHz 5 MHzCo 7 pF max. 4.7 pF max.Rs 600 max. 300 typoXTAL~--~----~EXTAL 1---__ ..,tL2 JrC UFigure 12 Crystal InterfaceCL 1 = CL2 = 22pF ± 20%(3.2 - 5 MHz)[Note] These are representativeAT cut parallel resonancecrystal parameters.• Vcc StandbyThis pin will supply +5 volts ±5% to the standby RAM on thechip. The first 64 bytes of RAM will be maintained in the powerdown mode with 8 rnA current max. The circuit of figure 13can be utilized to assure that Vee Standby does not go belowV SBB during power down.To retain information in the RAM during power down thefollowing procedure is necessary:1) Write "0" into the RAM enable bit, RAM E. RAM E is bit6 of the RAM Control Register at location $0014. Thisdisables the standby RAM, thereby protecting it at powerdown.2) Keep Vee StandbyTgreater than VSBB.Vee S",db, Pow", L;~Figure 13 Battery Backup for Vee Standby• Reset (RES)This input is used to reset and start the CPU from a powerdown condition, resulting from a power failure or an initialstartup of the processor. On power up, the reset must be held"Low" for at least 100 ms. During operation, RES, whenbrought "Low" must be held "Low" at least 3 clock cycles.When a "High" level is detected, the MCU does the following:1) All the higher order address lines will be forced "High".2) I/O Port 2 bits 2, I, and 0 are latched into programmedcontrol bits PC2, PCI and PeO.3) The last two ($FFFE, $FFFF) locations in memory willbe used to load the program addressed by the programcounter.4) The interrupt mask bit is set, must be cleared before theCPU can recognize maskable interrupts.• Enable (E)This supplies the external clock for the rest of the systemwhen the internal oscillator is used. It is a single phase, TILcompatible clock, and will be the divide by 4 result of thecrystal frequency. It will drive one TTL I()ad and 90 pF.• Non-Maskable Interrupt (NMI)A low-going edge on this input requests that a non-maskableinterruptsequence be generated within the processor. As withinterrupt Request signal, the processor will complete the currentinstruction that is being executed before it recognizes the NMIsignal. The interrupt mask bit in the Condition Code Registerhas no effect on NMI.In response to an NMI interrupt, the Index Register, ProgramCounter, Accumulators, and Condition Code Register are storedon the stack. At the end of the sequence, a 16-bit address willbe loaded that points to a vectoring address located in memorylocations $FFFC and $FFFD. An address loaded at these locationscauses the CPU to branch to a non-maskable interruptservice routine in memory.A 3.3 kn external resistor to Vee should be used forwire-OR and optimum control of interrupts.Inputs l'RQ. and NMI are hardware interrupt lines that aresampled during E and will start the interrupt routine on theE following the completion of an instruction.• Interrupt Request (IRQ.)This level sensitiv~ input requests that an interrupt sequencebe generated within the machine. The processor will wait until itcompletes the current instruction that it being executed beforeit recognizes the request. At that time, if the interrupt mask bitin the Condition Code Register is not set, the'ml!chine will beginan interrupt sequence. The Index Register, Progr.am Counter,Accumulators, and Condition Code Register are stored on thestack. Next the CPU will respond to the interrupt request bysetting the interrupt mask bit "High" so that no further maskableinterrupts m~y occur. At the end of the cycle, a 16-bitaddress will be loaded that points to a vectoring address which islocated in memory locations $FFF8 and $FFF9. An addressloaded at these locations causes the CPU to branch to an interruptroutine in memory.The IRQ. requires a 3.3 kn external resister to Vee whichshould be used for wire-OR and optimum control of in te.!!!Pts.Internal Interrupts will use an internal interrupt line (IRQ2).This interrupt will operate the same as IRQ. except that it willuse the vector address of $FFFO through $FFF7. IRQ. willhave priority over IRQz if both occur at the same time. TheInterrupt Mask Bit in the condition c()de register masks bothinterrupts (See Table I).eHITACHI 81

HD6801VO,HD6801V5-----------------------------------------------------HighestPriorityLowestPriorityTable 1 Interrupt Vector LocationVectorMSB LSBFFFEFFFCFFFAFFF8FFF6FFF4FFF2FFFOFFFFFFFDFFFBFFF9. FFF7FFF5FFF3FFF1InterruptRESNM1Software Interrupt (SWIIIR.Q. (or IS3)ICF (Input Capture)OCF (Output Compare)TOF (Timer Overflow)SCI (RDRF + ORFE + TORE)• PORTSThere are four I/O ports on the HD6801V MCU; three 8-bitports and one 5-bit port. There are two control lines associatedwith one of the 8-bit ports. Each port has an associated writeonly Data Direction Register which allows each I/O line to beprogrammed to act as an input or an output * . A "1" in thecorresponding Data Direction Register bit will cause that I/Oline to be an output. A "0" in the corresponding Data DirectionRegister bit will cause that I/O line to be an input. There arefour ports: Port 1, Port 2, Port 3, and Port 4. Their addressesand the addresses of their Data Direction registers are given inTable 2.* The only exception is bit .1 of Port 2, which can either be datainput or Timer output.Table 2 Port and Data Direction Register AddressesThe following pins are available in the Single Chip Mode, andare associated with Port 3 only.• Input Strobe (lS3) (SCdThe function of the IS3 signal depends on the I/O Port 3Control/Status Register. If IS3 Enable bit is set, an interruptwill occur by the fall of the IS3 signal. If the latch enable bit isset, the data in the I/O Port 3 will be latched at the I/O Port 3Data Register. The timing condition of the IS3 signal that isnecessary to be latched the input data normally is shown inFigure 6.• Output Strobe (OS3) (SC 2 )This signal is used by the processor to strobe an externaldevice, indicating valid data is on the I/O pins. The timing forthe Output Strobe is shown in Figure 5 I/O Port 3 Control/Status Register is discussed in the following section.The follOWing pins are available in the Expanded Modes.PortsPort AddressData DirectionRegister AddressI/O Port 1 $0002 $0000110 Port 2 $0003 $0001110 Port 3 $0006 $0004110 Port 4 $0007 $0005• I/O Port 1This is an 8-bit port whose individual bits may be defined asinputs or outputs by the corresponding bit in its data directionregister. The 8 output buffers have three-state capability,allowing them to enter a high impedance state when theperipheral data lines are used as inputs. In order to be readproperly, the voltage on the input lines must be greater than 2.0V for a logic "1" and less than 0.8 V for a logic "0". As outputsthese lines are TTL compatible and may also be used asa source of up to 1 rnA at 1.5 V to directly drive a Darlingtonbase. After Reset, the I/O lines are configured as inputs. In allthree modes, Port 1 is always parallel I/O.• Read/Write (R/Wl (SC2 )This TTL compatible output signals the peripherals andmemory devices whether the CPU is in a Read ("High") or aWrite ("Low") state. The normal standby state of this signal isRead ("High"). This output is capable of driving one TTL loadand 90 pF.• I/O Strobe (lOS) (SCI)In the expanded non-multiplexed mode of operation, lOSinternally decodes A9 through AI5 as zero's and As as a one.This allows external access of the 256 locations from $0100 to$OIFF. The timing diagrams are shown as figure 2.• Address Strobe (AS) (SCI)In the expanded multiplexed mode of operation addressstrobe is output on this pin. This signal is used to latch the 8LS~'s of address which are multiplexed with data on Port 3. An8-bit latch is utilized in conjunction with Address Strobe, asshown, in figure 19. Expanded Multiplexed Mode. AddressStrobe signals the latch when it is time to latch the address linesso the lines can become data bus lines during the E pulse. Thetiming for this singal is shown in Figure 1 of Bus Timing. Thissignal is also used to disable the address from the multiplexedbus allowing a deselect time, tASD before the data is enabled tothe bus.82 _HITACHI• I/O Port 2This port has five lines that may be defined as inputs oroutputs by its data direction register. The 5 output buffers havethree-state capability, allowing them to enter a high impedancestate when used as an input. In order to be read properly, thevoltage on the input lines must be greater than 2.0 V for alogic "1" and less than 0.8 V for a logic "0". As outputs, thisport has no internal pullup resistors but will drive TTL inputs·directly. For driving CMOS inputs, external pullup resistors arerequired. After Reset, the I/O lines are configured as inputs.Three pins on Port 2 (pins 10, 9, and 8 of the chip) are usedto program the mode of operation durmg reset. The values ofthese pins at reset are latched into the three MSB's (bits 7 6and 5) of Port 2 which are read only. This is explained in th~Mode Selection Section.In all three modes, Port 2 can be configured as I/O andprovides access to the Serial Communications Interface and theTimer. Bit 1 is the only pin restricted to data input or Timeroutput.• I/O Port 3This is an 8-bit port that can be configured as I/O, a data bus,or an address bus multiplexed with the data bus - depending onthe mode of operation hardware programmed by the user atreset. As a data bus, Port 3 is bi-directional. As an input forperipherals, it must be supplied regular TTL levels, that is,greater than 2.0 V for a logic "1" and less than 0.8 V for a logic"0".

----------------------------------------------------HD6801VO,HD6801V5Its TTL compatible three-state output buffers are capable ofdriving one TTL load and 90 pF. In the Expanded Modes, afterreset, the data direction register is inhibited and data flowdepends on the state of the R/W line. The input strobe (IS3)and the output strobe (OS3) used for handshaking are explainedlater.•In the three modes, Port 3 assumes the following characteristics:Single Chip Mode: Parallel Inputs/Outputs as programmed byits associated Data Direction Register. There are two controllines associated with this port in this mode, an input strobe andan. output strobe, that can be used for handshaking. They arecontrolled by the I/O Port 3 Control/Status Register explainedat the end of this section. Three options of Port 3 operationsare sumarized as follows: (1) Port 3 input data can be latchedusing IS3 (SCI) as a control signal, (2) OS3 can be generated byeither an CPU read or write to Port 3's Data Register, and (3)and IRQI interrupt can be enabled by an IS3 negative edge.Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.Expanded Non-Multiplexed Mode: In this mode, Port 3becomes the data bus (0 0 -0,).Expanded Multiplexed Mode: In this mode, Port 3 becomesboth the data bus (Do-0,) and lower bits of the address bus(Ao-A,). An address strobe output is true when the address ison the port.I/O PORT 3 CONTROL/STATUS REGISTER7 6IS3IS3IRQ 1$OOOF FLAG ENABLE5 4 3 2X OSS LATCH X XENABLEBit 0; Not used.Bit 1; Not used.Bit 2; Not used.Bit 3; LATCH ENABLE. This controls the input latch for I/OPort 3. If this bit is set "High" the input data will belatched with the falling edge of the Input Strobe, IS3.This bit is cleared by reset, and the latch is "re-opened"with CPU read Port 3.Bit 4; OSS. (Output Strobe Select) This bit will select if theOutput Strobe should be generated at OS3 (SC 2 ) by awrite to I/O Port 3 or a read of I/O Port 3. When this bitis cleared the strobe is generated by a read Port 3. Whenthis bit is set the strobe is generated by a write Port 3.Bit 5; Not used.Bit 6; IS3 IRQ1 ENABLE. When set, interrupt will be enabledwhenever IS3 FLAG is set; when clear, interrupt isinhibited. This bit is Cleared by RES.Bit 7; IS3 FLAG. This is a read only status bit that is set bythe falling edge of the input strobe, IS3 (SC I). It iscleared by a .read of the Control/Status Register followedby a read or write of I/O Port 3. Reset will clearthis bit.• I/O Port 4This is an 8-bit port that can be configured as I/O or asaddress lines depending on the mode of operation. In order tobe read properly, the voltage on the input lines must be greaterthan 2.0 V for a logic "1" and less than 0.8 V for a logic "0" .As outputs, each line is TTL compatible and can drive 1 TTLoXload and 90 pF. After reset, the lines are configured as inputs.To use the pins as addresses, therefore, they should beprogrammed as outputs. In the three modes, Port 4 assumes thefollowing characteristics:Single Chip Mode: Parallel Inputs/Outputs as programmed byits associated Data Direction Register.Expanded Non-Multiplexed Mode: In this mode, Port 4 isconfigured as the lower order address lines (Ao-A7)by writingone's to the data direction register. When all eight address linesare not needed, the remaining lines, starting with the mostsignificant bit, may be used as I/O (inputs only).Expanded Multiplexed Mode: In this mode, Port 4 isconfigured 3Slthe higher order address lines (As-Au) by writingone's to the data direction register. When all eight addresslines are not needed, the remaining lines, starting with the mostsignificant bit, may be used as I/O (inputs only).• OPERATION MODESThe mode of operation that HD680lV will operate in afterReset is determined by hardware that the user must wire on pins10, 9, and 8 of the chip. These pins are the three LSB's (I/O 2,I/O 1, and I/O 0 respectively) of Port 2. They are latched intoprogrammed control bits PC2, PC1, and PCO when reset goeshigh. I/O Port 2 Register is shown below.PORT 2 DATA REGISTER7 6 5 4 3 2 o$0003 ~-PC-2-TI-p-C-1~I-p-C-o~I~I-IO-·-4-1~1-IO--3~1~I/O--2~1 -1/-O-1~1-I/-O-O~An example of external hardware that could be used forMode Se}ection is shown in Fig 14. The HDl4053B providesthe isolation between the peripheral device and MCV duringReset, which is necessary if data conflict can occur betweenperipheral device and Mode generation circuit.As bits 5, 6 and 7 of Port 2 are read only, the mode cannotbe changed through software. The mode selections are shown inTable 3.The HD6801V is capable of operating in three basic modes;(1) Single Chip Mode, (2) Expanded Multiplexed Mode (compatiblewith HMCS6800 peripheral family) (3) Expanded Non­Multiplexed Mode.• Single Chip ModeIn the Single Chip Mode the Ports are configured for I/O.This is shown in Figure 16 the single Chip Mode. In thismode, Port 3 will have two associated, control lines, an inputstrobe and an output strobe for handshaking data.• Expanded Non-Multiplexed ModeIn this mode the HD680-lV will directly address HMCS6800peripherals with no external logic. In this mode Port 3 becomesthe data bus. Port 4 becomes the Ao-A7 address bus or partialaddress and I/O (inputs only). Port 2 can be parallel I/O, serialI/O, Timer, or any combination of them. Port 1 is parallel I/Oonly. In this mode the HD6801V is expandable to 256 locations.The eight address lines associated with Port 4 may besubstituted for I/O (inputs only) if a fewer number of addresslines will satisfy the application (See Figure 17)._HITACHI 83

HD6801VO,HD6801V5-----------------------------------------------------Vee(R~! ~R, R,~ R,T T TABCXoYo X..-- Zo YX, ZY,Z,( (CI ??? ModeControl~ SwitchInhJ,HD14053B689RESHD6801VP 20 (PCOIP 2, (PC1110 P 22(PC21[NOTES)Figure 14 Recommended Circuit for Mode Selection11 Mode 7 as shown21 RC",Reset time constant31 R, =10knTruth TableInhABCBinary to 1-of-2Decoder withInhibitXocr----------------~~~4-~~~Xl~------------------~~+-~--~yocr--------------------~~~--~ylcr--------------------~C*~--~Zocr----------------------~~~~Zlcr-------------------------K~~xyZControl InputOn SwitchSelectInhibitC B A HD14053B0 0 0 0 Zo Yo Xu0 0 0 1 Zo Yo X,0 0 1 0 Zo Y, X.0 0 1 1 Zo Y, X,0 1 0 0 Z, Yo Xo0 1 0 1 Z, Y. 'X,0 1 1 0 Z, Y, Xo0 1 1 1 Z, Y, X,1 X X X -Figure 15 HD14053B Multiplexers/DemultiplexersVeeVee2 7 40 EnableEnablePort 181/0 LinesPort 38110 linesPort 18 Parallel 110Port 38 Data LinesPort 481/0 LinesVssPort 251/0 linesSCITimerPort 25 Parallel 110SCITimerVssPort 4To 8 Addresslines or To8110 Lines(Inputs OnlvlFigure 16 HD6801V MCU Single-Chip ModeFigure 17 HD6801V MCU Expanded Non-Multiplexed Mode84 $ HITACHI

------------------------------------------------------HD6801VO,HD6801V5• Expanded Multiplexed ModeIn this mode Port 4 becomes higher order address lines withan alternative of substituting some of the address lines for I/O(inputs only). Port 3 is the data bus multiplexed with the lowerorder address lines differentiated by an output called AddressStrobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or anycombination of them. Port 1 is 8 Parallel I/O lines. In this modeit is expandable to 65k words. (See Figure 18).VeeEnable• Lower order Address Bus LatchesSince the data bus is multipfexed with the lower orderaddress bus in Port 3, latches are required tei latch those addressbits. The 74LS373 Transparent octal D-type latch can be usedwith the HD6801V to latch the least significant address byte.Figure 19 shows how to connect the latch to the HD6801V.The output control to the 74LS373 may be connected toground.Port 18 I/O LinesPort 25 I/O LinesSCITimerVss8 LinesMultiplexedData/AddressPort 4To 8 AddressLines or ToB I/O Lines(Inputs Only)Figure 18 HD6801V MCU Expanded Multiplexed ModeGNDPort 3Address/Data[AS\G OC0, Q,174LS373D. Q.A

HD6801VO,HD6801V5 --------------------------Table 3 Mode Selection SummaryMode(~~2)7 H6 H5 H4 H3 L2 L1 L0 L(~tI1)HHLLHHLLLEGEND:1- Interna!E - ExternalMUX - MultiplexedNMUX - Non-MultiplexedL- Logic "0"H - Logic "1"(~t'b)HLHLHLHLROM RAMInterruptVectorsBusModeOperatingModeI I I I Single ChipI I I MUX(S) Multiplexed/Partial DecodeI I I NMUX(S) Non-Multiplexed/Partial Decode1(2) 1(1 ) I I Single Chip TestE E E MUX Multiplexed/No RAM & ROME I E MUX Multiplexed/RAMI I E MUX Multiplexed/RAM & ROMI I 1(3) MUX Multiplexed Test(NOTES)1) Internal RAM is addressed at $XX802) Internal ROM is disabled3) RES vector is external for 2 cycles after RES goes "High"4) Addresses associated with Ports 3 and 4 are considered external in Modes 0,1,2, and 35) Addresses associated with Port 3 are considered external in Modes 5 and 66) Port 4 default is user data input; address output is optional by writing to Port 4Data Direction Register• MEMORY MAPSThe MCU can provide up to 65k byte address space dependingon the operating mode_ A memory map for each operatingmode is shown in Figure 20. The fust 321ocations of each mapare reserved for the MCV's internal register area, as shown inTable 4. With exceptions as indicated.• INTERRUPT FLOWCHARTThe Interrupt flowchart is depicted in Figure 24 and is commonto every interrupt excluding reset.Table 4 Internal Register AreaRegisterAddressPort 1 Data Direction Register"" 00Port 2 Data Direction Register""" 01Port 1 Data Register 02Port 2 Data Register 03Port 3 Data Direction Register""" 04"Port 4 Data Direction Register""" 05""Port 3 Data Register 06"Port 4 Data Register 07""Timer Control and Status Register 08Counter (High Byte) 09Counter (Low Byte)OAOutput Compare Register (High Byte)OBOutput Compare Register (Low Byte)OCInput Capture Register (High Byte) 00Input Capture Register (Low Byte)OEPort 3 Control and Status RegisterOF"Rate and Mode Control Register 10Transmit/Receive Control and Status Register 11Receive Data Register 12Transmit Data Register 13RAM Control Register 14Reserved 15-1F• External address in Mode~ 1,2,3,5,6; cannot beaccessed in Mode 5 (No_ lOs)•• External addresses in Modes 0, 1, 2, 3•• " 1-output, O=lnput.86 $ HITACHI

------------------------------------------------------HD6801VO,HD6801V5HD6801VModeoHD6801VMode1Multiplexed Test modeMultiplexed/RAM & ROM$0000(1)$001FI nternal RegistersExternal Memory Space$0000(1)$001FInternal RegistersExternal Memory Space$0080$0080$OOFFInternal RAM$ooFFInternal RAMExternal Memory SpaceExternal Memory Space$FOOO$FooOInternal ROMInternal Interrupt Vectors(2$FFEF$FFFO$FFj:F .....---"',Internal ROMExternal Interrupt Vectors(NOTES)1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and $OF.2) Addresses $FFFE and $FFFF are consideredexternal if accessed within 2 cycles alter apositive edge of RES and internal at all othertimes.3) After 2 CPU cycles, there must be no overlappingof internal and external memoryspaces to avoid driving the data bus with morethan one device.4) This mode is the only mode which may be usedto examine the interrupt vectors in internalROM using an external Reset vector.[NOTES]1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and$OF.2) Internal ROM addresses $FFFO to $FFFF arenot usable.Figure 20 HD6801V Memory Maps_HITACHI 87

HD6801VO,HD6801V5----------------------------------------------------$0000(1)$001F$0080Multiplexed/RAMHD6801VMode2Internal RegistersExternal Memory SpaceInternal RAMMultiplexed/No RAM or ROM$0000(1)$OO1FHD6801V3Mode} Internal Registers$OOFFExternal Memory SpaceExternal Memory Space$FFFO .....----t.} External Interrupt Vectors$FFFF '--___...[NOTE)1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07, and$OF.$FFFO ~----t .} External Interrupt Vectors$FFFF '--___ "'"[NOTE)1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and$OF.Figure 20 HD6801 V Memory Maps (Continued)88$ HITACHI

----------------------------------------------------HD6801VO,HD6801V5HD6801 V 4ModeHD6801VMode5$001Single Chip TestInternal RegistersNon-Multiplexed/Partial Decode$0000(1)} Internal Registers$001F$0080} Internal RAM$OOFF$0100} External Memory Space$01FF ....._ ....._..11)(4)$FOOOInternal ROM$XX80$XXFFInternal RAM}Internal Interrupt Vectors$FFFFInternal Interrupt Vectors(NOTES]11 The internal ROM is disabled.21 Mode 4 may be changed to Mode 5 withouthaving to assert RESET by writing a "1" intothe PCO bit of Port 2 Data Register.31 Addresses A. to A, s are treated as "don'tcares" to decode internal RAM.41 Internal RAM will appear at $XX80 to $XXFF.(NOTES]1) Excludes the following addresses which maynot be used externally: $04, $06, and $OF.(No 10SI21 This mode may be entered without goingthrough RES by using Mode 4 and sub·sequently writing a "1" into the PCO bit ofPort 2 Data Register.31 Address lines Ao-A,will not contain addressasuntil the Data Direction Register for Port 4has bean written with "1 's" in the appropriatebits. These address lines will assert "1's" untilmade outputs by writing the Data DirectionRegister.Figure 20 H 0680 1 V Memory Maps (Continued)eHITACHI 89

HD6801VO,HD6801V5----------------------------------------------------HD6801V6ModeHD6801V7ModeMultiplexed/Partial DecodeSingle Chip$0000(1)$001F$0080$OOFFInternal RegistersExternal Memory SpaceInternal RAM$0000$001F$0080$OOFFInternal RegistersExternal Memory Space$FOOO$FOOOInternal ROMInternal ROM$FFFFInternal Interrupt Vectors$FFFFInternal Interrupt Vectors[NOTES]1) Excludes the following address which may beused externallv: $04, $06, $OF.2) Address lines A. -Au will not containaddresses until the Data Direction Register forPort 4 has been written with "1'5" in theappropriate bits. These address lines willassert "1 's" until made outputs by writing theData Direction Register.Figure 20 HD6801V Memory Maps (Continued)90_HITACHI

------------------------------------------------------HD6801VO,HD6801V5• PROGRAMMABLE TIMERThe HD6801V contains an on-chip 16-bit programmabletimer which may be used to perform measurements on an inputwaveform while independently generating an output waveform.Pulse widths for both input and output signals may vary from afew microseconds to many seconds. The timer hardware consistsof• an 8-bit control and status register,• a 16-bit free running counter,• a 16-bit output compare register, and• a 16-bit input capture registerA block diagram of the timer registers is- shown in Figure 21.• Free Running Counter ($0009:000A)The key element in the programmable timer is a 16-bit freerunning counter which is driven to increasing values by E (Enable).The counter value may be read by the CPU software atany time. The counter is cleared to zero on RES and may beconsidered a read-only register with one exception. Any CPUwrite to the counter's address ($09) will always result in presetvalue of $FFF8 being loaded into the counter regardless of thevalue involved in the write. This preset figure is intended fortesting operation of the patt, but may be of value in someapplications.• Output Compare Register ($OOOB:OOOC)The Output Compare Register is a 16-bit read/write registerwhich is used to control an output waveform. The contents ofthis register are constantly compared with the current value ofthe free running counter. When a match is found, a flag is set(OCF) in the Timer Control and Status Register (TCSR) and thecurrent value of the Output Level bit (OLVL) in the TCSR isclocked to the Output Level Register. Providing the DataDirection Register for Port 2, Bit 1 contains a "1" (Output),the output level register value will appear on the pin for Port 2Bit 1. The values in the Output Compare Register and Outputlevel bit may then be changed to control the output level on thenext compare value. The Output Compare Register is set to$FFFF during RES. The Compare function is inhIbited forone cycle following a write to the high byte of the OutputCompare Register to insure a valid 16-bit value is in the registerbefore a compare is made.• Input Capture Register ($OOOD:OOOE)The Input Capture Register is a 16-bit read-only register usedto store the current value of the free running counter when theproper transition of an external input signal occurs. The inputtransition change required to trigger the counter transfer iscontrolled by the input Edge bit (IEDG) in the TCSR. The DataDirection Register bit for Port 2 Bit 0, should· be clear (zero)in order to gate in the external input signal to the edge detectunit in the timer.* With Port 2 Bit 0 conilgured as an output and set to "1". theexternal input will still be seen by the edge detect unit.• Timer Control and Status Register (TCSR) ($0008)The Timer Control and Status Register consists of an 8-bitregister of which all 8 bits are readable but only the low order 5bits may be written. The upper three bits contain read-onlytimer status information and indicate that:• a proper transition has taken place on the input pin with asubsequent transfer of the current counter value to theinput capture register.• a match has been found between the value in the freerunning counter and the output compare register, and• when $0000 is in the free running counter.Each of the flags may be enabled onto the HD680 1 V internalbus (IRQ2) with an individual Enable bit in the TCSR. If theIRQ,HD6801V Internal BusOutput InputLevel EdgeBit 1 Bit 0port 2 Port 2Figure 21Block Diagram of Programmable Timer$ HITACHI 91

HD6801VO,HD6801V5----------------------------------------------------Timer Control and Status Register7 6 5 4 3 2 1 0'ICF I OCF TOF I EICI I EOCI I ETOIIIEDG I OLVLI $0008I-bit in the H0680 1 V Condition Code Register has been cleared,apriority vectored interrupt will occur corresponding to the flagbit(s) set. A description for each bit follows:Bit 0 OLVL Output Level - This value is clocked to the outputlevel register on a successful output comp'are. Ifthe OOR for Port 2 bit 1 is set, the value willappear on the output pin.Bit 1 IEDG Input Edge - This bit controls which transition ofan input will trigger a transfer of the counter tothe input capture register. The OOR for Port 2 Bito must be clear for this function to operate. IEOG= 0 Transfer takes place on a negative edge("High"-to-"Low" transition).IEDG = 1 Transfer takes place on a positive edge("Low"-to-"High" transition).Bit 2 ETOI Enable Timer Overflow Interrupt - When set, thisbit enables IRQ 2 to occur on the internal bus for aTOF interrupt; when clear the interrupt is inhibited.Bit 3 EOCI Enable Output Compare Interrupt - When set,this bit enables IRQ2 to appear on the internal busfor an output compare interrupt; when clear theinterrupt is inhibited.Bit 4 EICI Enable Input Capture Interrupt - When set, thisbit enables IRQ2 to occur on the internal bus foran input capture interrupt; when clear the interruptis inhibited.Bit 5 TOF Timer Overflow Flag - This read-only bit is setwhen the counter contains $FFFF. It is cleared bya read of the TCSR (with TOE set) followed by anCPU read of the Counter ($09).Bit 6 OCF Output Compare Flag - This read-only bit is setwhen a match is found between the outputcompare register and the free running counter. It iscleared by a read of the TCSR (with OCF set)followed by an CPU write to the output compareregister ($OB or SOC).Bit 7 ICF Input Capture Flag - This read-only status bit isset by a proper transition on the input; it is clearedby a read of the TCSR (with ICF set) followed byan CPU read of the Input Capture Register ($00).• SERIAL COMMUNICATIONS INTERFACEThe HD6801V contains a full-duplex asynchronous serialcommunications interface (SCI) on chip. The controllercomprises a transmitter and a receiver which operate independentlyor each other but in the same data format and at the samedata rate. Both transmitter and receiver communicate with theCPU via the data bus and with the outside world via pins 2, 3,and 4 of Port 2. The hardware, software, and registers are explainedin the following paragraphs.• Wake-Up FeatureIn a typical multi-processor application, the softwareprotocol will usually contain a destination address in the initialbyte(s) of the message. In order to permit non-selected MCU'sto ignore the remainder of the message, a wake-up feature· isincluded whereby all further interrupt processing may beoptionally inhibited until the beginning of the next message.When the next message appears, the hardware re-enables (or''wakes-up'') for the next message. The ''wake-up'' is automaticallytriggered by a string of ten consecutive 1 's whichindicates an idle transmit line. The software protocol mustprovide for the short idle period between any two consecutivemessages.• Programmable OptionsThe following features of the HD6801V serial I/O section areprogrammable:• format - standard mark/space (NRZ)• Clock - external or internal• baud rate - one of 4 per given CPU CP2 clock frequency orexternal clock x8 input• wake-up feature - enabled or disabled• Interrupt requests - enabled or masked individually fortransmitter and receiver data registers• clock output - internal clock enabled or disabled to Port2 (Bit 2)• Port 2 (bits 3 and 4) - dedicated or not dedicated to serialI/O individually for transmitter and receiver.• Serial Communications HardwareThe serial communications hardware is controlled by 4registers as shown in Figure 22. The registers include:• an 8-bit control and status register• a 4-bit rate and mode control register (write only)• an 8-bit read only receive data register and• an 8-bit write only transmit data register.In addition to the four registers, the serial I/O section utilizesbit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 ofPort 2 is utilized if the internal-clock-out or external-clock-inoptions are selected .Transmit/Receive Control and Status (TRCS) RegisterThe TRCS register consists of an 8-bit register of which all 8bits may be read while only bits 0"'4 may be written. Theregister is initialized to $20 on RES. The bits in tile TRCSregister are defined as follows:__Transmit/Receive Control and Status Register765432 0~IR_D_R __ F~lo R_F_E~I_T_D_R_E~I __ R_IE~ __ R_E~ __ T_I_E~ __ T_E~ __ W_u~IADDR:$001192 _HITACHI

------------------------------------------------------HD6801VO,HD6801V5Bit 7 Rate and Mode Control Register Bit 0I I CCl I CCO I SSl I SSO ,$10Transmit/Receive Control and Status Register$12Port 2(Not Addressable).... ---E:rxBit 124Transmit Data RegisterFigure 22 Serial I/O RegistersBit 0 WU "Wake-up" on Next Message - set by HD6801Vsoftware and cleared by hardware on receipt often consecutive l's or reset of RE flag. It shouldbe noted that RE flag should be set in advance ofCPU set of WU flag.Bit 1 TE Transmit Enable - set by HD6801V to producepreamble of nine consecutive l's and to enablegating of transmitter output to Port 2, bit 4regardless of the DDR value corresponding to thisbit; when clear, serial I/O has no effect on Port 2bit 4.TE set should be after at least one bit time of datatransmit rate from the set-up of transmit datarate and mode.Bit 2 TIE Transmit Interrupt Enable - when set, will permitan IRQ2 interrupt to occur when bit 5 (TDRE) isset; when clear, the TDRE value is masked fromthe bus.Bit 3 RE Receiver Enable - when set, gates Port 2 bit 3 toinput of receiver regardless of DDR value for thisbit; when clear, serial I/O has no effect on Port 2bit 3.Bit 4 RIE Receiver Interrupt Enable - when set, will permitan IRQ2 interrupt to occur when bit 7 (RDRF) orbit 6 (ORFE) is set; when clear, the interrupt ismasked.Bit 5 TORE Transmit Data Register Empty - set by hardwarewhen a transfer is made from the transmit dataregister to the output shift register. The TDRE bitis cleared, by reading the status register, thenwriting a new byte into the transmit data register,TDRE is initialized to 1 by RES.Bit 6 ORFE Over-Run-Framing Error - set by hardware whenan overrun or framing error occurs (receive only).An overrun is defined as a new byte received withlast byte still in Data Register/Buffer. A framjngerror has occurred when the byte boundaries in bitstream are not synchronized to bit counter.IfWUflag is set, the ORFE bit will not be set. TheORFE bit is cleared by reading the status register,then reading the Receive Data Register, or byRES.Rate and Mode Control Register7 6 5 432 oBit 7 RORF Receiver Data Register Full - set by hardwarewhen a transfer from the input shift register to thereceiver data register is made. If WU flag is set,the RDRF bit will not be set. The RDRF bit iscleared by reading the status register, then readingthe Receive Data Register, or by RES.Rate and Mode Control RegisterThe Rate and Mode Control register controls the followingserial I/O variables:• Baud rate• format• clocking source, and• Port 2 bit 2 configurationThe register consists of 4 bits all of which are write-only andcleared on RES. The 4 bits in the register may be considered asa pair of 2-bit fields. The two low order bits control the bit ratefor internal clocking and the remaining two bits control theformat and clock select logic. The register definition is asfollows:x I x x x I eel I eeo I SS1 SSO ADDR : $0010_HITACHI 93

HD6801VO.HD6801V5----------------------------------------------------Bit 0 SSO Speed Select - These bits select the Baud rate forBit I SS1 the internal clock. The four rates which may beselected are a function of the CPU

------------------------------------------------------HD6801VO,HD6801V5Receive OperationThe receive operation is enabled by the RE bit which gates inthe serial input through Port 2 Bit 3. The receiver sectionoperation is conditioned by the contents of the Transmit/Receive Control and Status Register and the Rate and ModeControl Register.The receiver bit interval is divided into 8 sub-intervals forinternal synchronization. In the NRZ Mode, the received bitstream is synchronized by the first 0 (space) encountered.The approximate center of each bit time is strobed duringthe next 10 bits. If the tenth bit is not a I (stop bit) a framingerror is assumed, and bit ORFE is set. If the tenth bit as a I, thedata is transferred to the Receive Data Register, and interruptflag RDRF is set. If RDRF is still set at the next tenth bit time,ORFE will be set, indicating an over-run has occurred. When theH06801V responds to either flag (RDRF or ORFE) by readingthe status register foUowed by reading the Data Register, RDRF(or ORFE) will be cleared.• RAM CONTROL REGISTERThis register, which is addressed at $0014, gives statusinformation about the standby RAM. A 0 in the RAM enablebit (RAM E) wiD disable the standby RAM, thereby protectingit at power down if Vee Standby is held greater than VSBBvolts, as explained previously in the signal description for VeeStandby.RAM Control Register~141 ~ IRAMEI X I X I X I X IX I X IBit 0 Not used.Bit 1 Not used.Bit 2 Not used.Bit 3 Not used.Bit 4 Not used.Bit 5 Not used.Bit 6 RAME The RAM Enable control bit allows the user theability to disable the standby RAM. This bit is setto a logic •• 1" by RES which enables the standbyRAM and can be written to one or zero under programcontrol. When the RAM is disabled, data isread from external memory.Big 7 STaY The Standby Power bit is cleared when the stand-PWR by voltage is removed. This bit is a read/write statusflag that the user can read which indicates thatthe standby RAM voltage has been applied, andthe data in the standby RAM is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD680IV is upward object code compatible with theH06800 as it implements the full HMCS6800 instruction set.The execution times of key instructions have been reduced toincrease throughout. In addition, new instructions have beenadded; these include I6-OOt operations and a hardware mUltiply.Included in the instruction set section are the follOWing:• CPU Programming Model (Figure 23)• Addressing modes• Accumulator and memory instructions - Table 7• New instructions• Index register and stack manipulations instructions - Table8• Jump and branch instructions - Table 9• Condition code register manipulation instructions - Table 10• Instructions Execution times in machine cycles - Table11• Summary of cycle by cycle operation - Table 12• Summary of undefmed instructions operation• Op codes Map ~ Table 13• CPU Programming ModelThe programming model for the HD680 1 V is shown in Figure23. The double (D) accumulator is physically the same as theAccumulator A concatenated with the Accumulator B so thatany operation using accumulator D will destroy information inA and B.8-Bit Accumulators A and 8Or 16·Bit Double Accumulator D1 '5 X 0 I ndex Register (X)11 '5 SP 0 Stack Pointer (SP)11 '5 PC 0 Program Counter (PC)1Figure 23 CPU Programming ModelCondition Code Register (CCR)Carry/Borrow from MSBOverflowZeroNesativeInterruptHalf Carry (From Bit 3)• CPU Addressing ModesThe HD680 1 V eight-bit microcomputer unit has seven addressmodes that can be used by a programmer, with the addressingmode a function of both the type of instruction and the codingwithin the instruction. A summary of the addressing modes fora particular instruction can be found in Table 11 along with theassociated instruction execution time that is given in machinecycles. With a clock frequency of 4 MHz, these times would bemicroseconds.Accumulator (ACCX) AddressingIn accumulator only addreSSing, either accumulator A oraccumulator B is specified. These are one-byte instructions.Immediate AddressingIn immediate addressing, the operand is contained in thesecond byte of the instruction except LDS and LDX which havethe operand in the second and third bytes of the instruction.The CPU addresses this location when it fetches the immediateinstruction for execution. These are two or three-byte instructions.eHITACHI 95

HD6801VO,HD6801V5-------------------------Table 7 Accumulator & Memory InstructionsCondition CodeOperations MnemonicAddressing ModesRegisterBoolean/IMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V CAdd ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A + B-+ A• f f f ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-+B* * f Add Double*ADDD C3 4 3 03 5 2 E3 6 2 F3 6 3 A:B+M:M+1-+A:B• * f f fAdd Accumulators ABA 1B 2 1 A+B-+A* f f fAdd With Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-+A'* ADCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-+8 * * * ** f f f tAND ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A'M-+A t t R ANDB C4 2 2 04 3 2 E4 4 2 F4 4 '3 B'M-+ B * t R Bit Test BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M t t R BIT B C5 2 2 05 3 2 E5 4 2 F5 4 3 B'M • t f R •Clear CLR 6F 6 2 7F 6 3 00-+ M • S R R• RCLRA 4F 2 1 00 .... A • • RS R RCLRB 5F 2 1. 00 -+ B• • R S R RCompare CMPA 81 2 2 91 3 2 A1 4 2 B1 4 3 A-M• • t t t tCMPB C1 2 2 01 3 ,2 E1 4 2 F1 4 3 B-M • • t t t tCompareAccumulatorsCBA 11 2 1 A-B • • t * * *Complement, 1 '5 COM 63 6 2 73 6 3 M-+M • • t t R SCOMA 43 2 1 A -+A• • t t R SCOMB 53 2 1 B -+B • • t t R SComplement, 2'5 NEG 60 6 2 70 6 3 OO-M .... M• • t t (j)~(Negate) NEGA 40 2 1 OO-A-+A • • t t (l)~NEGB 50 2 1 OO-B .... B• • t * (j)~Converts binary add of BCDcharacters into BCD format • • t t t @Decima' Adjust, A DAA 19 2 1Decrement DEC 6A 6 2 7A 6 3 M-1 .... M• • t t @ •DECA 4A 2 1 A-1-+A• • t * @ •DECB 5A 2 1 B-1-+B • • t * @ •Exclusive OR EORA 88 2 2 98 3 2 AS 4 2 B8 4 3 A@ M-+A • • t * R •EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 B @ M- B • • t t R •Increment INC 6C 6 2 7C 6 3 M+1-+M • • t t @ •INCA 4C 2 , A+1 .... A• • t t @.INCB 5C 2 1 B + , .... B t f @ •Load LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-+A • f f R AccumulatorLDAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M-+B• • f f R •Load DoubleLDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1 - B, M - A • • f f R •AccumulatorMultiply Unsignad MUL 3D 10 1 AxB-A:B • • • @OR, Inclusive ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+M .... A t f R •ORAB CA 2 2 DA 3 ;Z EA 4 2 FA 4 3 B +M .... B • f t R •Push Data PSHA 36 3 1 A .... Msp, SP - 1- SP PSHB 37 3 1 B .... Msp, SP - 1 -+ SP Pull Oata PULA 32 4 1 SP + 1- SP, Msp- A PULB 33 4 1 SP + 1 -+ SP, Msp - B • • • •Rotate Left ROL 69 6 2 79 6 3:}I:~tl I 1 Ii I,::Jt t @ tROLA 49 2 160t f (0) fB '67ROLB 59 2 1f f @ tRotate Right ROR 66 6 2 76 6 3:} 4]:11 I~ * * @ tRORA 46 2 1 I I I I I t t @ tB C b7 bOROR8 56 2 1 • • t t :j, ,The Condition Code Register notes are hstad after Table 10,(Continued).. *96 eHITACHI

--------------------------HD6801VO,HD6801V5Table 7 Accumulator & Memory Instructions (Continued)OperationsMnemonicAddressing ModesIMMED. DIRECT INDEX EXTEND IMPLIEDOP - # OP - # OP - #Shift Left ASL 68 6 2ArithmeticASLADouble ShiftLeft, ArithmeticASLBASLDShift Right ASR 67 6 2ArithmeticASRAASJ:!BShift Right LSR 64 6 2LogicalLSRADouble ShiftRight LogicalLSRBLSRDStore STAA 97 3 2 A7 4 2AccumulatorSTAB 07 3 2 E7 4 2Store DoubleAccumulatorSTD DO 4 2 ED 5 2Subtract SUBA 80 2 2 90 3 2 AO 4 2SUBB CO 2 2 DO 3 2 EO 4 2Double Subtract SUI3D 83 4 3 93 5 2 A3 6 2SubtractAccu mu latorsSBASubtract SBCA 82 2 2 92 3 2 A2 4 2With CarrySBCB C2 2 2 02 3 2 E2 4 2TransferAccumulatorsTABTBATest Zero or TST 60 6 2MinusTSTATSTB. .The CondItIon Code RegIster notes are listed after Table 10 •OP787774B7F7FDBOFOB3B2F270BooleanlArithmetic OperationCondition CodeRegister5 4 3 2 1 0- - # OP # H I N Z V C6 3 M} __ • • t t @t6 36 348 2 1 A [fllllllill-o • • t t ~tB C b7 bO58 2 1• • t t ® t-05 3 1 ~ A

HD6801VO,HD6801V5-----• New InstructionsIn addition to the existing 6800 Instruction Set, the following new instructions areincorporated in the HD680lV Microcomputer.ABX Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into accountthe possible carry out of the low order byte of the X-Register.ADOD Adds the double precision ACCD· to the double precision value M:M+l and placesthe results in ACCD.ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit isloaded from the most significant bit of ACCD.LDO Loads the contents of double precision memory location into the doubleaccumulator A:B. The condition codes are set according to the data.LSRD Shifts· all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bitis loaded from the least significant bit to ACCD.MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a16-bit unsigned number in A:B, ACCA contains MSB of result.PSHX The contents of the index register is pushed onto the stack at the address containedin the stack pointer. The stack pointer is decremented by 2.PULX The .index register is pulled from the stack beginning at the current addresscontained in the stack pointer + 1. The stack pointer is incremented by 2 in total.STO Stores the contents pf double accumulator A:B in memory. The contents of ACCDremain unchanged.SUBD Subtracts the contents of M:M + 1 from the contents of double accumulator ABand places the result in ACCD.BRN Never branches. If effect, this instruction can be considered a two byte NOP (Nooperation) requiring three cycles for execution.CPXInternal processing modified to permit its use with any conditional branch instruction.·ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulatoris the most significant byte.Pointer OperationsMnemonicTable 8 Index Register and Stack Manipulation InstructionsAddressing ModesBooleanlIMMED. DIRECT INDEX EXTND IMPLIED Arithmetic OperationOP - # OP - # OP - # OP- # OP - #Compare Index Reg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 X-M:M+1Decrement Index Reg DEX 09 3 1 X -1-+ XDecrement Stack Pntr DES 34 3 1 SP -1-+ SPIncrement Index Reg INX 08 3 1 X·+ 1-+ XIncrement Stack Pntr INS 31 3 1 SP+1-SPLoad Index Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M- XH, (M+ 1) - XLLoad Stack Pntr LOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M-+ SPH. (M+1)-SPLStore Index Reg STX OF: 4 2 EF 5 2 FF 5 3 XH - M. XL - (M + 1)Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH -+ M. SP L - (M+ ,.Index Reg -+ Stack Pntr TXS 35 3 1 X-1-+SPStack Pntr -+ Index Reg TSX 30 3 1 SP+1-+XAdd ABX 3A 3 1 B+X-+XPush Data PSHX 3C 4 1 XL -+ Mil). SP - 1 - SPXH- Mil). SP -1-+ SPPull Data PULX 38 5 1 SP + 1- SP, MIP - XHThe Condition Code Register notes are listed after Table 10.SP+ 1- SP,M IP -XLCondition CodeRegister5 4 3 2 1 0H I N Z V Ctt t tt • • • • t • •• • • • • •• • (i) tR•• (i) t R • • (i) t R •• • (i) tR•• • • • • •• • • • • •98 eHITACHI

OperationsMnemonic--------------------------HD6801VO,HD6801V5Table 9 Jump and Branch InstructionsAddressing ModesRELATIVE DIRECT INDEX EXTND IMPLIEDBranch TestCondition CodeRegister5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V CBranch Always BRA 20 3 2 None • • • • • •Branch Never BRN 21 3 2 None • • • • • •Branch If Carry Clear BCC 24 3 2 C"O • • • • • •Branch If Carry Set BCS 25 3 2 C = 1 • • • • • •Branch If = Zero BEQ 27 3 2 Z=1 • • • • • •Branch If ;> Zero BGE 2C 3 2 N(±)V-O• • • • • •Branch If > Zero BGT 2E 3 2 Z + (N (±) VI .. 0• • • • • •Branch If Higher BHI 22 3 2 C+Z-O • • • • • •Branch If" Zero BlE 2F 3 2 Z + (N (±) VI .. 1• • • • • •Branch If lower OrBlS 23 3 2 C+Z -1Same• • • • • •Branch If < Zero BLT 20 3 2 N(±)V=1 Branch If Minus BMI 2B 3 2 N" 1 • • • • • •Branch If Not EqualZeroBNE 26 3 2 Z=O • • • • • •Branch If OverflowBVC 28 3 2 V-OClear• • • • • •Branch If Overflow Set BVS 29 3 2 V-1 • Branch If Plus BPl 2A 3 2 N"O Branch To Subroutine BSR 80 6 2 • • Jump JMP 6E 3 2 7E 3 3 • Jump To Subroutine JSR 90 5 2 AD 6 2 BD 6 3-- • • • • • •No Operation NOP 01Advances Prog. Cntr.2 1Only • • • • • •Return From Interrupt RTI 3B 10 1 -@-Return FromSubroutineRTS 39 5 1• • • • • •Software Interrupt SWI 3F 12 1 • S • Wait for Interrupt WAI 3E 9 1 • @. • • •Table10 Condition Code Register Manipulation InstructionsAddressingModesCondition Code RegisterOperations Mnemonic IMPLIED Bool.ean Operation 5 4 3 2 1 0OP - # H I N Z V CClear Carry ClC OC 2 1 O-+C • • • • • RClear Interrupt Mask Cli OE 2 1 0-+1 • R • • • •Clear Overflow ClV OA 2 1 O-+V• • • • R •Set Carry SEC 00 2 1 1-+C • • • • • SSet Interrupt Mask SEI OF 2 1 1 -+ I• S • • • •Set Overflow SEV OB 2 1 1"'V • • • • S •Accumulator A -+ CCR TAP 06 2 1 A ... CCR ---@) -----CCR -+ Accumulator A TPA 07 2 1 CCR-+ A• • • • • •Condition Code Register Notes: (Bit set it test is true and cleared otherwisel

HD6801VO,HD6801V5----------------------------------------------------100ABAABXADCADDADDDANDASLASLDASRBCCBCSBEQBGEBGTBHIBITBLEBLSBLTBMIBNEBPLBRABRNBSRBVCBVSCBACLCCLICLRCLVCMPCOMCPXDAADECDESDEXEORINCINSTable 11Instruction Execution Times in Machine CycleACCX I~~:- Direct te~~~ del:~••••••2•2••••••••••••••••••••2•2••2•••2•••2242•••••••••2••••••••••••••••2•4••••2••••3353•••••••••3•••••••••••••••3•5••••3••••44646•6••••••4••••••••••••••6•466•6••46•••44646•6•••••4•••••••••••••6•466•6••46•Implied23•••••3••••••••••••••••••222•2•••2•33••3Relative•••••••••333333•33333333633•••••••••••••••INXJMPJSRLOALDDLOSLOXLSRLSRDMULNEGNOPORAPSHPSHXPULPULXROLRORRTIRTSSBASBCSECSEISEVSTASTDSTSSTXSUBSUBDSWITABTAPTBATPATSTTSXTXSWAIeHITACHIACCX 1;::- Direct te~~~ d~~~•••••••2••2••3•4•22••••••••••••••••••2••••••2333•••••2•••••••••2•••••••24•••••••••••53444••••3•••••••••3•••344435••••••••••3645556•6•4••••66•••4•••455546•••••6••••3645556•6•4••••66•••4•••455546•••••6•••Implied3•••••••310•2••4•5••1052•222••••••122,222•339Relative•••••••••••••••••••••••••••••••••••••••••

--------------------------HD6801VO,HD6801V5• Summary of Cyde by Cyde OperationTable 12 provides a detailed description of the informationpresent on the Address Bus, Data Bus, and the Read/Write line(R/W) during each cycle for each instruction.This information is useful in comparing actual with expectedresults during debug of both software and hardware as thecontrol program is executed. The information is categorized ingroups according to addressing mode and number of cycles perinstruction. (In general, instructions with the same addressingmode and number of cycles execute in the same manner; exceptionsare indicated in the table).Table 12 Cycle by Cycle OperationAddress Mode &InstructionsAddress BusData BusIMMEDIATEADC EORADD LOAAND ORABIT SBCCMP SUB21 Op Code Address 12 Op Code Address + 1 1Op CodeOperand DataLOS~DXLDDCPXSUBDADDD341 Op Code Address 12 Op Code Address + 1 13 Op Code Address + 2 11 Op Code Address 12 Op Code Address + 1 13 Op Code Address + 2 14 Address Bus FFFF 1Op CodeOperand Data (High Order Byte)Operand Data (low Order Byte)Op CodeOperand Data (High Order Byte)Operand Data (low Order Byte)low Byte of Restart VectorDIRECTADC EORADD LOAAND ORABIT SBCCMP SUB31 Op Code Address 12 Op Code Address + 1 13 Address of Operand 1Op CodeAddress of OperandOperand DataSTAlOSlOXlDDSTSSTXSTDCPXSUBDADDDJSR344551 Op Code Address 12 Op Code Address + 1 13 Destination Address 01 Op Code Address 12 Op Code Address + 1 13 Address of Operand 14 Operand Address + 1 11 Op Code Address 12 Op Code Address + 1 13 Address of Operand 04 Address of Operand + 1 01 Op Code Address 12 Op Code Address + 1 13 Operand Address 14 Operand Address + 1 15 Address Bus FFFF 11 Op Code Address 12 Op Code Address + 1 13 Subroutine Address 14 Stack Pointer 05 Stack Pointer + 1 0Op CodeDestination AddressData from AccumulatorOp CodeAddress of OperandOperand Data (High Order Byte)Operand Data (low Order Byte)Op CodeAddress of OperandRegister Data (High Order Byte)Register Data (low Order Byte)Op CodeAddress of OperandOperand Data (High Order Byte)Operand Data (low Order Byte)low Byte of Restart VectorOp CodeIrrelevant DataFirst Subroutine Op CodeReturn Address (low Order Byte)Return Address (High Order Byte)(Continued)_HITACHI101

HD6801VO HD6801V5-----,Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsINDEXEDAddress BusData BusJMPADC EORADD LOAAND ORABIT SBCCMP SUBSTALOSLOXLODSTSSTXSTDASL LSRASR NEGCLR ROLCOM RORDEC TST*INCCPXSUBDAODOJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op.CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register Plus Offset 11 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register Plus Offset 0 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register Plus Offset 1 Operand Data (High Order Byte)Index Register Plus Offset + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register Plus Offset 0 Operand Data (High Order Byte)Index Register Plus Offset + 1 0 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register Plus Offset 1 Current Operand DataAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register Plus Offset 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register + Offset 1 Operand Data (High Order Byte)Index Register + Offset + 1 1 Operand Data (Low Order Byte)Address Bus F F F F 1· Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restart VectorIndex Register + Offset 1 First Subroutine Op CodeStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)* In the TST instruction, Rm line of the sixth cycle is "1" level, and AB=FFFF, DB=Low Byte of Reset Vector. (Continued)102 _HITACHI

--------------------------HD6801VQ,HD6801V5Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusEXTENDEDJMPADC EORADD LOAAND ORABIT SBCCMP SUBSTALOSLOXLDDSTSSTXSTDASL LSRASR NEGCLR ROLCOM RORDEC TST*INCCPXSUBDADDDJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 Op CodeOp Code Address + 1 1 Jump Address (High Order Byte)Op Code Address + 2 1 Jump Address (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Destination Address (High Order Byte)Op Code Address + 2 1 . Destination Address (Low Order Byte)Operand Destination Address 0 Data from AccumulatorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand Data (High Order Byte)Address of Operand + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 0 Operand Data (High Order Byte)Address of Operand + 1 0 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Add,ess + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Current Operand DataAddress Bus F F F F 1 Low Byte of Restart VectorAddress of Operand 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Operand Address (High Order Byte)Op Code Address + 2 1 Operand Address (Low Order Byte)Operand Address 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Address Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Subroutine (High Order Byte)Op Code Address + 2 1 Address of Subroutine (Low Order Byte)Subroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)(Continued)• In theTST instruction, R/W line ofthe sixth cycle is "1" level,and AB= FFFF, DB= low Byte of Reset Vector.eHITACHI 103

HD6801VO,HD6801V5-----·Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsIMPLIEDABA DAA SECASL DEC SEIASR INC SEVCBA LSR TABCLC NEG TAPCLI NOP TBACLR ROL TPACLV ROR TSTCOM SBAABXASLDLSRDDESINSINXDEXPSHAPSHBT5XTXSPULAPULBPSHX-~-~--------PULXRTSWAI**2 123 1233 1233 1233 1233 1233 1233 1234 12344 1234r--- 5 123455 123459 1234Address BusData BusOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataAddress Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataAddress Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionPrevious Register

---------------------------HD6801VO,HD6801V5Table 12 Cycle by Cycle Operation (Continued)Address Mode &CycleR/WCyclesAddress BusInstructions # lineData BusWAI** 5 Stack Pointer - 2 0 Index Register (Low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code RegisterMUL 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Address Bus FFFF 1 Low Byte of Restart Vector4 Address Bus F F F F 1 Low Byte of Restart Vector5 Address Bus F F F F 1 Low Byte of Restart Vector6 Address Bus FFFF 1 Low Byte of Restart Vector7 Address Bus FFFF 1 Low Byte of Restart Vector8 Address Bus F F F F 1 Low Byte of Restart Vector9 Address Bus FFFF 1 Low Byte of Restart Vector10 Address Bus FFFF 1 Low Byte of Restart VectorRTI 10 1 Op Code Address 1 OpCode2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Contents of Condo Code Reg.from Stack5 Stack Pointer + 2 1 Contents of Accumulator Bfrom Stack6 Stack Pointer + 3 1 Contents of Accumulator Afrom Stack7 Stack Pointer + 4 1 Index Register from Stack(High Order Byte)8 Stack Pointer + 5 1 Index Register from Stack(Low Order Byte)9 Stack Pointer + 6 1 Next Instruction Address fromStack (High Order Byte)10 Stack Pointer + 7 1 Next Instruction Address fromStack (Low Order Byte)SWI 12 1 Op Code Address 1 OpCode2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 0 Return Address (Low· Order Byte)4 Stack Pointer - 1 0 Return Address (H igh Order Byte)5 Stack Pointer - 2 0 Index·Register (Low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accul!lulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code Register10 Stack Pointer - 7 1 Irrelevant Data11 Vector Address FFFA (Hex) 1 Address of Subroutine(High Order Byte)12 Vector Address FFFB (Hex) 1 Address of Subroutine(Low Order Byte)"While the MCU is in the "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than theoriginal contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI instruction.(Continued)$ HITACHI 105

HD6801VO,HD6801V5 -----Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionAddress BusData BusRELATIVEBCC BHT BNEBCS BlE BPlBEQ BlS BRABGE BlT BVCBGT BMT BVSBRNBSR3 1236 123456Op Code Address 1 Op CodeOp Code Address + 1 1 Branch OffsetAddress Bus FFFF 1 low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Branch OffsetAddress Bus FFF F 1 Low Byte of Restart VectorSubroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)• Summary of Undefined Instruction OperationsThe HD6801 V has 36 undefined instructions. When these arecarried out, the contents of Register and Memory in MCVchange at random.When the op codes (4E, SE) are used to execute, the MCVcontinues to increase the program counter and it will not stopuntil the Reset signal enters. These op codes are used to test theLSI.Table 13 Op codes MapHD6801V MICROCOMPUTER INSTRUCTIONSACCAorSPACCB or XOP---ACC ACC IND EXTCODE A B0080 0 SBA BRA TSX NEG SUB---- ----0001 1 NOP CBA BRN INS CMP0010 2 ~ BHI PULA 1+1) SBC0011 3 ~ BLS PULB 1+1) COM . SUBD 1+2) : ADDD 1+2)·0100 4 LSRD 1+1) ~ BCC DES LSR ANDBCS TXS BIT0110 6 TAP TAB BNE PSHA ROR LOA0111 7 TPA TBA BEQ PSHB ASR /1 STA ~I STA----1000 8 INX 1+11 ~ BVC PULX 1+2) ASL EOR1001 9 DEX 1+1) DAA BVS RTS 1+2) ROL ADC1010 A CLV ./ BPL ABX DEC . ORA1011 B SEV ABA BMI RTII+7) ADD1100 C CLC ./ · BGE PSHX 1+11 INC CPX 1+2) LDD 1+11BGT WAII+6) LOX 1+1)IMM I DIR liND I EXT IMM I DIR liND L EXT~ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1'00'1'0'011011 1100 11101 11110111110 1 2 3 4 5 6 7 8 I 9 I A I B C 101 ElF0101 5 ASLDI+1I ~-----.. ---JMP 1-3) . , LOS 1+1)·1101 0 SEC/BLT MUL 1+7) TST P!~IJSR 1+2) ·1+1~ STD 1+1)1110 E CLI /'_1111 F SEI ~ BLE SWII+9) CLR ::-1+111 STS 1+1) ·1+1)1 STX 1+11BYTE/CYCLE 112 1/2 2/3 113 1/2 112 2/6 3/6 2/2 I 2/3 I 2/4 I 3/4 2/2 I 2/3 I 2/4 I 3/4[NOTES) I) Undefined Op coclesare marked with ~.2) I ) indicate that the number in parenthesis must be edded to the cycle count for that instruction •.3) The instructions shown below are all 3 bytes and are marked with ".".Immediate eddressing mode of SUBD, CPX, LOS, ADDD, LDD and LOX instructions, and undefined op codes18F, CD, CF).4) The Op codes 14E, 5E) are 1 byte/ao cycles instructions, and are marked with " .....023456789ABC0EF106eHITACHI

e:z:~()!*SCI = TIE-TORE + RIE·(RORF + ORFE)Vector .... PC~ Figure 24 Interrupt FlowchartfiIMl FFFC FFFOSWI FFFA FFFB1M. FFF8 FFF9ICF FFF6 FFF7OCF FFF4 FFF5TOF FFF2 FFF3SCI FFFO FFF1Non-Maskable InterruptSoftware InterruptMaskable Interrupt Request 1Input Capture InterruptOutput Compare InterruptTimer Overflow InterruptSCI Interrupt (TORE + RORF + ORFE)~C0)00~

HD6801VO,HD6801V5----------------------------------------------------VeeVeeEnablePort 38 TransferLinesIRO,-Port 181/0 LinesPort 2.,..-,. ..__.,..._.....J.,..-.,. 51/0 LinesSCIPort 251/0 LinesSCIPort 481/0 LinesVssVssFigure 25 H06801 V MCU Single-Chip Dual Processor ConfigurationHD6801VMCUAddressBusDataBusFigure 26 H06801V MCU Expanded Non-Multiplexed ModeAddress BusData BusFigure 27 H06801V MCU Expanded Multiplexed Mode108$ HITACHI

H06803, H06803-1---­MPU (Micro Processing Unit)The H06803 MPU is an 8-bit microcomputer system whichis compatible with the HMCS6800 family of parts. The HD6803MPU is object code compatible with the HD6800 with improvedexecution times of key instructions plus several new 16-bit and8 bit instruction including an 8 x 8 unsigned multiply with16-bit result. The HD6803 MPU can be expanded to 65k words.The HD6803 MPU is TTL compatible and requires one +0.5volt power supply. The HD6803 MPU has 128 bytes of RAM,Serial Communications Interface (S.C.!.), and parallel I/O aswell as a three function 16-bit timer. Features and BlockDiagram of the HD6803 include the following:• FEATURES• Expanded HMCS6800 Instruction Set• 8 x 8 Multiply• On-Chip Serial Communications Interface (S.C.I.)• Object Code Compatible with The HD6800 MPU• f6-Bit Timer• Expandable to 65k Words• Multiplexed Address and Data• 128 Bytes of RAM (64 Bytes Retainable On PowerDown)• 13 Parallel 1/0 Lines• Internal Clock/Divided-By-Four• TTL Compatible Inputs and Outputs• Interrupt Capability• Compatible with MC6803 and MC6803-1• BLOCK DIAGRAMHD6803PHD6803P-l• PIN ARRANGEMENTXTALEXTALIRQ,REsVeeP2UPI!P.,P"P"P,.P"P"P"p ..P'So(DP-401HD6803ASAMDo/AoD,/A,Dz/A zOJ/A"D4 1A 4Do/A;D6/A bD7 /A 7AxAyA, •AllA12StandbyD./A.D,/A,D./A.D,/A,B ,/A. s/A.D./A.D'iA,R/\NASAddress..'DataBuffers--+--P ..~"""'-+--P2IIoo+-+-r ......-P••1o+-~ __ P23t-f-+-++-.-- P ..(Top View)A.A.A,.A"A ..AuA ..A,.AddressBuffersAddress.....---P,......---p" ----P.......---P,......---P..P,.----P"Pl1• TYPE OF PRODUCTSType No. Bus TimingHD6803 1.0MHzHD6803-1 1.25MHzVee Standby~HITACHI109

HD6803,HD6803-1------------"----------_--..,;... _____ _• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee.-0.3 -+7.0 VInput Voltage Vin * -0.3- +7.0 VOperating Temperature Topr 0 -+70 °cStorage Temperature Till! -55-+150 °c• With respect to vSS ISYSTEM GND)[NOTE) Permanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operatingconditions. If these conditions are exceeded, it could affect reliability of lSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee -=5.0V±5%, VSS· OV, Ta = G-+l70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitRES 4.0 - VeeInput "High" VoltageV 1HVOther Inputs·2.0 - VeeInput "low" Voltage Allinputs* V 1L -0.3 - 0.8 VInput Load Current EXTAl Ilinl Vin = 0- Vee - - 0.8 rnA- - ----In~ut Leakage Current NMI,IRQ I , RES Ilinl Vin = 0 - 5.25V - - 2.5 p.AThree State (Offset) P IO -- P I7 - - 10I ITS.! Vin = 0.5 -- 2.4Vleakage Current P 20 -- P24 - - 100Do/Ao -- D7/A7 I LOAD = -205 p.A 2.4 - -Output "High" Voltage As -- ~15, E, RIW, AS V OH I LOAD = -145p.A 2.4 - - VOther Outputs I LOAD = -100p.A 2.4 - -= 1.6 rnA - - 0.5 VOutput "low" Voltage All Outputs VOL ILOADDarlington Drive Current PIO -- PI7 -loH Vout = 1.5V 1.0 - 10.0 rnAPower Dissipation Po - - 1200 mWInput CapacitanceVee Standby= OV. Ta = 25°C, - - 12.5- -Ao 100 - A7/D7 VinC1nOther Inputsf = 1.0 MHz 10.0Powerdown VSBB 4.0 - 5.25Operating VSB 4.75 - 5.25Standby Current Powerdown ISBB VSBB = 4.0V - - 8.0 rnAp.ApFV"Except Mode Programming levels.110 _HITACHI

----------------------------------------------------------H06803,H06803-1• AC CHARACTERISTICSBUS TIMING (Vee· 5.0V ± 5%, V ss • OV, Ta - 0 - +70° C, unless otherwise noted.)Test HD6803 HD6803-1Item Symbol Condi- Unittion min typ max min typ maxCycle Time t cvc 1 - 10 0.8 - 10 JJ.SAddress Strobe Pulse Width "High" PWASH 200 - - 150 - - nsAddress Strobe Rise Time t ASr 5 - 50 5 - 50 nsAddress Strobe Fall Time tASf 5 - 50 5 - 50 nsAddress Strobe Delay Time tAso 60 - - 30 - - nsEnable Rise Time tEr 5 - 50 5 - 50 nsEnable Fall Time tEf 5 - 50 5 - 50 nsEnable Pulse Width "High" Time PWEH 450 - - 340 - - nsEnable Pulse Width "Low" Time PWEL 450 - - 350 - - nsAddress Strobe to Enable Delay Time tASEo Fig. 1 60 - - 30 - - nsAddress Delay Time tAD - - 260 - - 260 nsAddress Delay Time for Latch t AoL - - 270 - - 260 nsData Set-up Write Time tosw 225 - - 115 - - nsData Set-up Read Time tOSR 80 - - 70 - - nsI Read tHR 10 - - 10 - -Data Hold TimensI Write tHW 20 - - 20 - -Address Set-up Time for Latch t ASL 60 - - 50 - - nsAddress Hold Time for Latch tAHL 20 - - 20 - - nsAddress Hold Time tAH 20 - - 20 - - nsPeripheral Read Access Time (Multiplexed Bus) (tACCM) - - (600) - - (420) nsOscillator stabilization Time t RC Fig. 7 100 - - 100 - - msProcessor Control Set-up Time tpcs Fig.8 200 - - 200 - - nsPERIPHERAL PORT TIMING (Vee· 5.0V ± 5%, Vss - OV, Ta = 0"" +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitPeripheral Data Setup Time Port 1,2 tposu Fig.2 200 - - nsPeripheral Data Hold Time Port 1,2 tpoH Fig.2 200 - - nsDelay Time, Enable NegativeTransition to Peripheral Data Port 1,2* tpwo Fig. 3 - - 400 nsValid* Except P 21~HITACHI 111

H06803,H06803-1---------------------------TIMER, SCI TIMING (Vee - S.OV ±S"', Vss '" OV, Ta '" 0 -- +70°C, unless otherwise noted.)Item Symbol Test Condition min typTimer Input Pulse Width tpw'" ~ 2tcvc+200 -Delay Time, Enable Positive Transition totTOO Fig. 4 - -Timer OutSCI Input Clock Cycle tScVc 1 -SCI Input Clock Pulse Width tpwsCK 0.4 -max Unit- ns600 ns- tcvc0.6 tScVcMODE PROGRAMMING (Vee· S.OV is''', Vss • OV, Ta· 0 -- +70°C, unless otherwise noted.)ItemMode Programming Input "Low" Vo1tageMode Programming Input "High" Voltagem "Low" Pulse WidthMode Programming Set·up TimeMode Programming I RES Rise Time ~ 11lsHold TimeI m Rise Time < 11lsSymbolVMPLVMPHPWRSTLtMPStMPHTest Condition min typ- -4.0 -Fig. 8 3.0 -2.0 -0 -100 -maxUnit1.7 V- V- tcyc- tcyc-nstcycAddress Strobe(ASIEnablelEI/--tAS.~tASf~~--- - IASO l- ASE!:: -,\1\2.4 v) -J J t/PWEH-\~~-tEfR/W.A.-A ..MPUWrtteDo/An-D7/A.(Port 31I~ 2.2V I Address ValidO.SV i"'r-2.2V.,I--PWASH-o,svJ'-PWEL ,O.5V ~\I--tE.--IAO-IASL-~ ~IAHL-tosw- I--tHW-2.2V ..lI r-2.2V) Address \. J Data Valid~ValidI ~O.SVO.6V--I-IAH~~~~I(MPU ReadDn/A.-DdA,(Port 31- }-tAoL-~22V ""l~2.0V...,'-tOSR-Address \.Valid < Data ValidO.6V ... O.8VItACCMI--.-tHR..lI\.. /112Figure 1 Expanded Multiplexed Bus Timing~HITACHI

------------·-----------------H06803,H06803-1Enable (EIr-MPU Read.Enable (E)r MPUWriteosv'l"wc x /All Oat:Port Outputs~2~. 2~V----O.6V Data ValidFigure 2Data Set-up and Hold Times(MPU Read)• Not applicable to P 21Figure 3 Port Data Delay Timing(MPU Write)Enable (E)T,merCounter _____ ~ .... _-+ ___ _p ..OutputFigure 4Timer Output TimingMode Inputs _______-

H06803,H06803-1----------------------____ _Enable lEIIntornalA~NHau.-n--~~--~~---r~--~----~----~ __ _J~ __ _J~ __ ~~ __ ~ ____ ~ __ _J~ __ _'~ __ ~ ____ ~ __ __iiiMlor IRQ,·Internal""",.....--"'V---v---~,...--"""\,...--"'V---'V'----.v_-~,...-"""',.....-~ ...... --"'V----"""',.....-"'V---'V"--__..,...­Data au. ""'----"'''----'nOp--C-ode-''O-P-C-Od-.''-PC-o--P-C'''7"P-CS---PC-"5'...x-O--X-7","----""'-...... n.- ĀC - C - BJ'--""'I-rre-leva--n-t """Y-ec-tor--Yect--o-r"""F,-,.-t I-nst"'."o-, -Oata MSB LSB Interrupt RoutineInternal RNi• IRa, ; Internal interruptEriable IE) ~~\\\\\\\\\\\~ ~\\\\\\\\\\\\%\,'-------------------------------------------,Figure 7 Interrupt SequenceLJl...r4 [l...IlSl.fU'" nn...ru-"""*-4 5 . 7 25 Y tt . 1 J ~ U ~v~ 'r~--·-5Y--------------------_t~----------------------~ ~ ~ ~An -------.. n .....----------------04. ~4.6V tpcs .t~J'ii-O;;..BY.;....-PCS-----A: tern :, §\\\~\\\\\\\'§\\\1 ~\%\\\\SSS\\\\\\\\\\§mv--v~ ~res.u. ~~~~ ::::x::=r-Inlernal R/W \\\\\\\\%\\\\\~ ~\\§\\\\\\\\SSSSSS\\\SSSSSYci~::r;~! &\\\§\\\\\\\}\\§m1 {m\§\\\\\\\\\S\\S%\\\\SMG Pc::x::x:~NotYalidFigure 8 Reset Timing• SIGNAL DESCRIPTIONSNominal Crystal Parameter• Vee and VssThese two pins are used to supply power and ground to thechip. The voltage supplied will be +5 volts ±5%.• XTAL and EXTALThese connections are for a parallel resonant fundamentalcrystal, AT cut. Devided by 4 circuitry is included with theinternal clock, so a 4 MHz crystal may be used to run thesystem at 1 MHz. The devide by 4 circuitry allows for use of theinexpensive 3.58 MHz Color TV crystal for non-time criticalapplications. Two 22pF capacitors are needed from the twocrystal pins to ground to insure reliable operation. EXT AL maybe driven by an external TTL compatible source with a 50%(±10%) duty cycle. It will devided by 4 any frequency less thanor equal to 5 MHz. XTAL must be grounded if an externalclock is used. The following are the recommended crystalparameters:5MHz4.7pF max.30n typoXTAL~--~------~ClEXTAL ~--.... ---stL2 Jr CL1Figure 9 Crystal InterfaceCL1 = C L2 " 22pF:t 20%(3.2 - 5MHz)iNOTE) AT cut parallelresonance parameters114 ~HITACHI

----------------------------H06803,H06803-1• vee StandbyThis pin will supply +5 volts ±S% to the standby RAM on thechip. The first 64 bytes of RAM will be maintained in the powerdown mode with 8 rnA current max. The circuit of figure 13can be utilized to assure that Vee Standby does not go belowV SBB during power down.To retain information in the RAM during power down thefollowing procedure is necessary:1) Write "0" into the RAM enable bit, RAM E. RAM E is bit6 of the RAM Control Register at location $0014. Thisdisables the standby RAM, thereby protecting it at powerdown.2) Keep Vee Standby greater than VSBB.VCC""db'TPowe,u",Figure 10 Battery Backup for Vee Standby• Reset (RES)This input is used to reset and start the MPU from a powerdown condition, resulting from a power failure or an initialstartup of the processor. On power up, the reset must be held"Low" for at least 100 ms. During operation, RES, whenbroUght "Low", must be held "Low" at least 3 clock cycles.When a "High" level is detected, the CPU does the following;1) All the higher order address lines will be forced "High".2) I/O Port 2 bits, 2, 1, and 0 are latched into programmedcontrol bits PC2, PC 1 and PeO.3) The last two ($FFFE, $FFFF) locations in memory willbe used to load the program addressed by the programcounter.4) The interrupt mask bit is set, must be cleared before theCPU can recognize maskable interrupts.• Enable (E)This supplies the external clock for the rest of the systemwhen the internal oscillator is used. It is a single phase, TTLcompatible clock, and will be the divide by 4 result of thecrystal frequency. It will drive one TTL load and 90 pF.• Non-Maskable Interrupt (NMI)A low-going edge on this input requests that a non-maskableinterr\lptsequence be generated within' the processor. As withinterrupt Request signal, the processor will complete the currentinstruction that is being executed before it recognizes the NMIsignal. The interrupt mask bit in the Condition Code Registerhas no effect on NMI.In response to an NMI interrupt, the Index Register, ProgramCounter, Accumulators, and Condition Code Register are storedon the stack. At the end of the sequence, a I6-bit address willbe loaded that points to a vectoring address located in memorylocations $FFFC and $FFFD. An address loaded at these locationscauses the CPU to branch to a non-maskable interruptservice routine in memory.A 3.3 k!1 external resistor to Vee should be used forwire-OR and optimum control of interrupts.Inputs IROI and NMI are hardware interrupt lines that are~pled during E and will start the interrupt routine on theE following the completion of an instruction.• Interrupt Request (lRQI)This level sensitive input requests that an interrupt sequencebe generated within the machine. The processor will wait until itcompl.eies the current instruction that it being executed beforeit recognizes the request. At that time, if the interrupt mask bitin the Condition Code Register is not set, the-m~chine will beginan interrupt sequence. The Index Register, Program Counter,Accumulators, and Condition Code Register are stored on thestack. Next the CPU will respond to the interrupt request bysetting the interrupt mask bit "High" so that no further maskableinterrupts may occur. At the end of the cycle, a 16-bitaddress will be loaded that points to a vectoring address which islocated in memory locations $FFF8 and $FFF9. An addressloaded at these locations causes the CPU to branch to an interruptroutine in memory.The IRQI requires a 3.3 k!1 external resister to Vee whichshould be used for wire-OR and optimum control of interrupts.Internal Interrupts will use an internal interrupt line (lRQl)'This interrupt will operate the same as IRQ I except that it willuse the vector address of $FFFO through $FFF7. IRQ\ willhave priority over IRQ 2 if both occur at the same time. TheInterrupt Mask Bit in the condition code register masks bothinterrupts (See Table 1).HighestPriorityLowestPriorityTable 1 Interrupt Vector LocationVectorMSB LSBFFFE FFFFFFFC FFFOFFFA FFFBFFF8 FFF9FFF6 FFF7FFF4 FFF5FFF2 FFF3FFFO FFFlInterruptRESNMISoftware Interrupt (SWIlIRQ\ICF (Input Capture)OCF (Output Compare)TOF (Timer Overflow)SCI (RORF + ORFE + TORE)• ReadlWrite (R,w)This TTL compatible output signals the peripherals andmemory devices whether the CPU is in a Read ("High") or aWrite ("Low") state. The normal standby state of this signal isRead ("High"). This output is capable of ddving one TTL loadand 90 pF.• Address Strobe (AS)In the expanded multiplexed mode of operation addressstrobe is output on this pin. This signal is used to latch the 8LSB's of address which are multiplexed with data on Port 3. An8-bit latch is utilized in conjunction with Address Strobe, asshown. in figure 11. Expanded Multiplexed Mode. AddressStrobe signals the latch when it is time to latch the address linesso the lines can become data bus lines during the E pulse. Thetiming for this singal is shown in Figure 1 of Bus Timing. Thissignal is also used to disable the address from the multiplexedbus allowing a deselect time, tASD before the data is enabled tothe bus.• PORTSThere are two I/O ports on the H06803 MPU; one 8-bitport and one S-bit port. Each port has an associated write~HITACHI 115

H06803,H06803-1---------------------------------------------------------only Data Direction Register which allows each I/O line to be state when used as an input. In order to be read properly, theControl G 0 aD. a 8LH HHprogrammed to act as an input or an output *. A "1" in thecorresponding Data Direction Register bit will cause that I/Oline to be an output. A "0" in the corresponding Data DirectionRegister bit will cause that I/O line to be an input. There aretwo ports: Port I, Port 2. Their addresses and the addresses oftheir Data Direction registers are given in Table 2.voltage on the input lines must be greater than 2.0 V for alogic "I" and less than 0.8 V for a logic "0". As outputs, thisport has no internal pullup resistors but will drive TTL inputsdirectly. For driving CMOS inputs, external pullup resistors arerequired. After Reset, the I/O lines are configured as inputs.Three pins on Port 2 (pin 8, 9 and 10 of the chip) are requestedto set following values (Table 3) during reset. The values of* The only exception is bit 1 of Port 2, which can either be datainput or Timer output.above three pins during reset are latched into the three MSBs(Bit 5, 6 and 7) of Port 2 which are read only.Port 2 can be configured as I/O and provides access to theTable 2 Port and Data Direction Register AddressesSerial Communications Interface and the Timer. Bit 1 is thePortsPort AddressData Direction only pin restricted to data input or Timer output.Register Address110 Port 1$0002$0000Table 3 The Values of three pins110 Port 2$0003$0001Pin NumberValue8 L• I/O Port 19 HThis is an 8-bit port whose individual bits may be defined as10 Linputs or outputs by the corresponding bit in its data directionregister. The 8 output buffers have three-state capability,[NOTES) L; Logical ''0''H; Logical "1"allowing them to enter a high impedance state when theperipheral data lines are used as inputs. In order to be readproperly, the voltage on the input lines must be greater than 2.0 • BUSV for a logic "I" and less than 0.8 V for a logic "0". As outputs, • Data/Address Lines (Do/Ao - D7/A7)these lines are TTL compatible and may also be used as a source Since the data bus is multiplexed with the lower orderof up to 1 rnA at 1.5 V to directly drive a Darlington base. After address bus in Data/Address, latches are required to latch thoseReset, the I/O lines are configured as inputs.address bits. The 74LS373 Transparent OctalO-type latch canbe used with the "06803 to latch the least significant address• I/O Port 2This port has five lines that may be defined as inputs oroutputs by its data direction register. The 5 output buffers havethree·state capability, allowing them to enter a high impedancebyte. Figure 11 shows how to connect the latch to the "06803.The output control to the 74LS373 may be connected toground.• Address Lines (As - A1S)Each line is TTL compatible and can drive one TTL load and90 pF. After reset, these pins become output for upper orderaddress lines (As to Als )GND• INTERRUPT FLOWCHARTASIThe Interrupt flowchart is depicted in Figure 16 and is com·mon to every interrupt excluding reset.G DC0, a,Function Table74LS373 1 Add,~. A. -A,OutputEnable OutputLH LLLL x a oH x x Z10 ...,0.-0,Figure 11 Latch Connection116 $ HITACHI

---------------------------HD6803,HD6803-1• MEMORY MAPThe MPU can provide up to 65k byte address space. Amemory map is shown in Figure 12. The first 32 locations arereserved for the MPU's internal register area, as shown in Table4 with exceptions as indicated.Table 4 Internal Register AreaRegisterAddressPort 1 Data Direction Register-- 00Port 2 Data Direction Register-- 01Port 1 Data Register 02Port 2 Data Register 03Timer Control and Status Register 08Counter (High Byte) 09Counter (Low Byte)OAOutput Compare Register (High Byte)OBNot Used 04-Not Used 05-Not Used 06-Not Used 07-Output Compare Register (Low Byte)OCInput Capture Register (High Byte) 00Input Capture Register (Low Byte)OENot UsedOF-Rate and Mode Control Register 10Transmit/Receive Control and Status Register 11Receive Data Register 12Transmit Data Register 13RAM Control Register 14Reserved 15-1F- External Address-- 1; Output, 0; Input$0000$001F$0080$OOFFMultiplexed/RAMInternal RegistersExternal Memory SpaceI nternal RAMExternal Memory Space• PROGRAMMABLE TIMERThe HD6803 contains an on-chip l6-bit programmable timerwhich may be used to perform measurements on an inputwaveform while independently generating an output waveform.Pulse widths for both input and output signals may vary from afew microseconds to many se~onds. The timer hardware consistsof• an 8-bit control and status register,• a 16-bit free running counter,• a 16-bit output compare register, and• a 16-bit input capture registerA block diagram of the timer registers is shown in Figure 13.• Free Running Counter ($O009:000A)The key element in the programmable timer is a 16-bit freerunning counter which is driven to increasing values by E (Enable).The counter value may be read by the CPU software atany time. The counter is cleared to zero on RES and may beconsidered a read-only register with one exception. Any CPUwrite to the counter's address ($09) will always result in presetvalue of $FFF8 being loaded into the counter regardless of thevalue involved in the write. This preset figure is intended fortesting operation of the part, but may be of value in someapplications.• Output Compare Register ($OOOB:OOOC)The Output Compare Register is a 16-bit read/write registerwhich is used to control an output wavefonll_ The contents ofthis register are constantly compared with the current value ofthe free running counter. When a match is found, a flag is set(OCF) in the Timer Control and Status Register (TCSR) and thecurrent value of the Output Level bit (OLVL) in the TCSR isclocked to the Output Level Register. Providing the DataDirection Register for Port 2, Bit 1 contains a' "}" (Output),the output level register value will appear on the pin for Port 2Bit 1. The values in the Output Compare Register and OutputLevel bit may then be changed to control the output level onthe next compare value. The Output Compare Register is set to$FFFF during RES_ The Compare function is inhibited forone cycle follOWing a write to the high byte of the OutputCompare Register to insure a valid 16-bitvalue is in the registerbefore a compare is made.• Input Capture Register (SOOOD:OOOE)The Input Capture Register is a 16-bit read-only register usedto store the current value of the free running counter when theproper transition of an external input signal occurs. The inputtransition change required to trigger the counter transfer iscontrolled by the input Edge bit (IEDG) in the TCSR. The DataDirection Register bit for Port 2 Bit 0, should * be clear (zero)in order to gate in the external input signal to the edge detectunit in the timer.* With Port 2 Bit 0 configured as an output and set to "1", theexternal input will still be seen by the edge detect unit.$FFFO t----t,}$FFFF '"____... External Interrupt Vectors(NOTE)Excludes the following addresses which maybe used externally: $04, $05, $06, $07, and$OF.Figure 12 HD6803 Memory Map~HITACHI 117

H06803,H06803-1--------------------------------------______________ __HD6803 Internal Busr-..... -=~ DEOutput InputLevel EdgeBit 1 Bit DPort 2 Port 2Figure 13 Block Diagram of Programmable TimerTimer Control and Status Register76543210ICF I OCF I TOF I EICI I EOCI I ETOII'EDG I OlVll $0008• Timer Control and Status Register (TCSR) ($0008)The Timer Control and Status Register consists of an 8-bitregister of which all 8 bits are readable but only the low order 5bits may be written. The upper three bits contain read-onlytimer status information and indicate that:• a proper transition has taken place on the input pin with asubsequent transfer of the current counter value to theinput capture register..3' match has been found between the value in the freerunning counter and the output compare register, andwhen SOOOO is in the free running counter.Each of the flags may be enabled onto the H06803 internalbus (IRQ2) with an individual Enable bit in the TCSR. If theI-bit in the H06803 Condition Code register has been cleared, apriority vectored interrupt will occur corresponding to the flagbit(s) set. A description for each bit follows:Bit 0 Ol Vl Output Level - This value is clocked to the outputlevel register on a successful output comp:are. Ifthe OOR for Port 2 bit I is set. the value willappear on the output pin.Bit I IEDG Input Edge - This bit controls which transition ofan input will trigger a transfer of the counter tothe input capture register. The OOR for Port 2 Bito must be dear for this function to operate. IEOG= 0 Transfer takes place on a negative edgeC'High"-to-"Low" transition).IEDG = I Transfer takes place on a positive edge("Low"-to-"High" transition).Bit 2 ETOI Enable Timer Overflow Interrupt - When set, thisbit enables IRQ2 to occur on the internal bus for aTOF interrupt; when clear the interrupt is inhibited.Bit 3 EOCI Enable Output Compare Interrupt - When set,this bit enables IRQ 2 to appear on the internal 'busfor an output compare interrupt; when dear theinterrupt is inhibited.Bit 4 EICI Enable input Capture Interrupt - When set. thisbit enables IRQ2 to occur on the internal bus foran input capture interrupt; when dear the interruptis inhibited.Bit 5 TOF Timer Overflow Flag - This read-only bit is setwhen the counter contains $FFFF. It is cleared bya read of the TCSR (with TOE set) followed by anCPU read of the Counter ($09).Bit 6 OCF Output Compare Flag - This read-only bit is setwhen a match is found between the outputcompare register and the free running counter. It iscleared by a read of the TCSR (with OCF set)followed by an CPU write to the output compareregister (SOB or SOC).Bit 7 ICF Input Capture Flag - This read-only status bit isset by a proper transition on the input; it is clearedby a read of the TCSR (with ICF set) followed byan CPU read of the Input Capture Register ($00).118$ HITACHI

----------------------------HD6803,HD6803-1• SERIAL COMMUNICATIONS INTERFACEThe H06803 contains a full-duplex asynchronous serialcommunications interface (SCI) on chip. The controllercomprises a transmitter and a receiver which operate independ.ently or each other but in the same data format and at the samedata rate. Both transmitter and receiver communicate with theCPU via the data bus and with the outside world via pins 2, 3,and 4 of Port 2. The hardware, software, and registers are ex·plained in the following paragraphs.• Wak.Up FeatureIn a typical multi·processor application, the softwareprotocol will usually contain a destination address in the initialbyte(s) of the message. In order to permit non·selected MPU'sto ignore the remainder of the message, a wake·up feature isincluded whereby all further interrupt processing may beoptionally inhibited until the beginning of the next message.When the next message appears, the hardware re·enables (or"wakes-up") for the next message. The "wake.up" is auto·matically triggered by a string of ten consecutive I's whichindicates an idle transmit line. The software protocol mustprovide for the short idle period between any two consecutivemessages.• Programmable OptionsThe following features of the H06803 serial I/O section areprogrammable:• format - standard mark/space (NRZ)• Clock - external or internal• baud rate - one of 4 per given CPU tP2 clock frequency orexternal clock x8 input• wake.up feature - enabled or disabled• Interrupt requests - enabled or masked individually fortransmitter and receiver data registers• clock output - internal clock enabled or disabled to Port2 (Bit 2)• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial1/0 individually for transmitter and receiver.• Serial Communications HardwareThe serial communications hardware is controlled by 4registers as shown in Figure 14. The registers include:• an 8·bit control and status register• a 4·bit rate and mode control register (write only)• an 8·bit read only receive data register and• an 8·bit write only transmit data register.In addition to the four registers, the serial I/O section utilizesbit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 ofPort 2 is utilized if the internal·clock·out or external·clock·inoptions are selected.Transmit/Receive Control and Status (TRCS) Registernle TRCS register consists of an 8·bit register of which all 8bits may be read while only bits 0-4 may be written. Theregister is initialized to $20 on RES. The bits in the TRCSregister are defined as follows:Port 2Bit 7 Rate and Mode Control Register 8.t 0I I CCI I CCO I 551 1550 IS10Transmit/Receive Control and Status RegisterReceive Shift RegIsterClock 10Bit ...... ---..:.::.-.------~ ~---E2T.Bit412Transmit Data RegisterFigure 14 Serial I/O RegistersBit 0 WU "Wake·up" on Next Message - set by H06803software and cleared by hardware on receipt often consecutive 1 's or reset of RE flag. I t shouldbe noted that RE flag should be set in advance ofCPU set of WU flag.Bit 1 TE Transmit Enable - set by HD6803 to producepream ble of nine consecutive I's and to enablegating of transmitter output to Port 2, bit 4regardless of the OOR value corresponding to thisbit; when clear, serial I/O has no effect on Port 2bit4.TE set should be after at least one bit time of datatransmit rate from the set·up of transmit datarate and mode.Bit 2 TIE Transmit Interrupt Enable - when set, will permitan IRQ2 interrupt to occur when bit 5 (TORE) isset; when clear, the TORE value is masked fromthe bus.Bit 3 RE Receiver Enable - when set, gates Port 2 bit 3 toinput of receiver regardless of OOR value for thisbit; when clear, serial 1/0 has no effect on Port 2bit 3.Bit 4 RIE Receiver Interrupt Enable - when set, will permitan IRQ2 interrupt to· occur when bit 7 (RDRF) orbit 6 (ORFE) is set; when clear, the interrupt ismasked.Transmit/Receive Control and Status Register76543210~HITACHI 119

H06803,H06803-1---------------------------Bit 5 TDRE Transmit Data Register Empty - set by hardwarewhen a transfer is made from the transmit dataregister to the output shift register. The TORE bitis cleared by reading the status register. thenAn overrun is defined as a new byte received withlast byte still in Oat Register/Buffer. A framingerror has occured when the byte boundaries in bitstream are not synchronized to bit counter. IfWU-flag is set. the ORFE bit will not be set. TheORFE bit is c1eard by reading the status register,then reading the Receive Data Register. or byRES.Bit 7 RDRF Receiver Data Register Full-set by hardware whena transfer from the input shift register to thereceiver data register is made .If WU-flag is set, theRDRF bit will not be set. The RDRF bit is clearedby reading the status register, then reading theReceive Data Register. or by RES.Rate and Mode Control Register (RMCR)The Rate and Mode Control register controls the followingserial I/O variables:• Baud rateRate and Mode Control Register6 5 4 3 2 ox I CCl I CCO 551 550ADDR : $0010writing a new byte into the transmit data register,TORE is initialized to I by RES.Bit 6 ORFE Over-Run-Framing Error - set by hardware whenan overrun or framing error occurs (receive only).• format• clocking source. and• Port:! bit:! configurationThe register consists of 4 bits all of which are write-only andcleared on RES. The 4 bits in the register may be considered asa pair of 2-bit fields. The two low order bits control the bit ratefor internal clocking and the remaining tWQ bits control theformat and clock select logic. The register definition is asfollows:Bit 0 SSOBit I SSlBit 2 CCOBit 3 CClTable 5 SCI Bit Times and RatesSpeed Select - These bits select the Baud rate forthe internal clock. The four rates which may beselected are a function of the CPU q,2 clockfrequency. Table 5 lists the available Baud rates.Clock Control and Fonnat Select - this 2-bit fieldcontrols the format and clock select logic. Table 6defines the bit field.XTAL 2.4576 MHz 4.0 MHz 4.9152 MHz"SSl : SSO E 614.4 kHz 1.0 MHz 1.2288 MHz0 0 E -;. 16 26I-1s/38,400 Baud 16 I-Is/62,500 Baud 13.0I-ls/76,800 Baud0 1 E -;.128 208 I-Is/4 ,800 Baud 128I-1s/7812.5 Baud 104.2I-1s/9,600 Baud1 0 E -;. 1024 1.67 ms/600 Baud 1.024 ms/976.6 Baud 833.3 I-Isl1,200 Baud1 1 E -;. 4096 6.67 ms/150 Baud 4.096 ms/244.1 Baud 3.33 ms/300 Baud• HD6803·1 OnlyTable 6 SCI Format and Clock Source ControlCC1:CCO Format Clock Source Port 2 Bit 2 Port 2Bit 3 Port 2 Bit 4o 0 - - - .... ...0 1 NRZ Internal Not Used .. ..1 0 NRZ Internal Output· .. ..1 1 NRZ External Input .. ..• Clock output is available regardless of values for bits RE and TE.Bit 3 is used for serial input if RE = "1" in TRC5; bit 4 is used for serial output if TE = "1" in TRC5.Internally Generated ClockIf the user wishes for the serial I/O to furnish a clock. thefollowing requirements are applicable:• the values of RE and TE are immaterial.• CCI. CCO must be set to 10• the maximum clock rate will he E -;. 16.• the clock will be at Ix the hit rate and will have a risingedge at mid-hit.Externally Generated ClockIf the user wishes to provide an external clock for the serialI/O, the following requirements are applicable:• the CC I, CCO, field in the Rate and Mode Control Registermust be set to I I,• the external clock must be set to 8 times (x8) the desiredbaud rate and• the maximum external clock frequency is J.O MHz.120 ~HITACHI

--------------------------H06803,H06803-1• Serial OperationsThe serial I/O hardware should be initialized by the HD6803software prior to operation. This sequence will normally consistof;• writing the desired operation control bits to the Rate andMode Control Register and• writing the desired operational control bits in the Transmit/Receive Control and Status Register.The Transmitter Enable (TE) and Receiver Enable (RE) bitsmay be left set for dedicated operations.Transmit OperationsThe transmit operation is enabled by the TE bit in theTransmit/Receive Control and Status Register. This bit whense.t, gates the output of the serial transmit shift register to Port ~Bit 4 and takes unconditional control over the Data DirectionRegister value for Port 2, Bit 4.Following a RES the user should configure both the Rateand Mode Control Register and the Transmit/Receive Controland. Statu~ Register for desired operation. Setting the TE bitdunng thiS procedure initiates the serial output by first~ransmitting a nine-bit preamble of 1 'so Following the preamble,mtemal synchronization is established and the transmittersection is ready for operation.At this point one of two situation exist:I) if the Transmit Data Register is empty (TDRE :: 1), acontinuous string of ones will be sent indicating an idleline, or,2) if data has been loaded into the Transmit Data Register(TI?RE :: 0), the word is transferred to the output shiftregister and transmission of the data word will begin.During the transfer itself. the 0 start bit is first transmitted.Then the 8 data bits (beginning with bit 0) followed by the stopbit, are transmitted. When the Transmitter Data Register hasbeen emptied. the hardware sets the TDRE flag bit.If the HD6803 fails to respond to the flag within the propertime, (TDRE is still set when the next nomlal transfer from theparallel data register to the serial output register should occur)then a 1 will be sent (insteaq of a 0) at "Start" bit time.followed by more l's until more data is supplied to the datare~ister. No O's will be sent while TDRE remains a I.Receive OperationThe receive operation is enabled by the RE bit which gates inthe serial input through Port 2, Bit 3. The receiver sectionoperation is conditioned by the contents of the Transmit/Receive Control and Status Register and the Rate and ModeControl Register.The receiver bit interval is divided into 8 sub-intervals forinternal synchronization. In the NRZ Mode. the received bitstream is synchronized by the first 0 (space) encountered.The approximate center of each bit time is strobed duringthe next 10 bits. If the tenth bit is not a 1 (stop bit) a framingerror .is assumed, and bit ORFE is set. If the tenth bit as aI, thedata IS transferred to the Receive Data Register, and interruptflag RDRF is set. If RDRF is still set at the next tenth bit time.ORFE will be set. indicating an overrun has occurred. When theHD6803 responds to either flag (RDRF or ORFE) by readingthe status register followed by reading the Data Register. RDRF(or ORFE) will be cleared.it at power d?wn if V!2C Standby is held greater than VS88volts, as explamed preViously in the signal description for VeeStandby.so01·1 ~~ IRAM:FT~T: I X IX IX IBit 0 Not used.Bit 1 Not used.Bit 2 Not used.Bit 3 Not used.Bit 4 Not used.Bit 5 Not used.Bit 6 RAME The RAM Enable control bit allows the user theability to disable the standby RAM. This bit is setto a logic hI" by RES whicil enables the standbyRAM and can be written to one or zero under programcontrol. When the RAM is disabled. data isread from external memory.Bit 7 STSY The Standby Power bit is cleared when the stand-PWR by voltage is removed. This bit is a read/write sta·tus flag that the user can read which indicates thatthe standby RAM voltage has been applied, andthe data in the standby RAM is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD6803 is upward object code compatible with theH06800 as it implements the full HMCS6800 instruction set.The execution times of key instructions have been reduced toincrease throughout. In addition, new instructions have beenadded; these include 16·bit operations and a hardware multiply.Included in the instruction set section are the follOWing:• CPU Programming Model (Figure 15)• Addressing modes• Accumulator and memory instructions - Table 7• New instructions• Index register and stack manipulations instructions - Tahle8• Jump and branch instructions ~ Tahle 9• Condition' code register manipulation instructions - Table 10• Instructions Execution times in machine cycles - TableII• Summary of cycle by cycle operation -- Table 12· Summary of undefined instructions - Table 13• CPU Programming ModelThe programming model for the HD6803 is shown in Figure15. The double (D) accumulator is physically the same as theAccumulator A concatenated with the Accumulator B so thatany operation using accumulator D will destroy information inA and B.• RAM CONTROL REGISTERThis register, which is addressed at Soo14. gives statusinformation about the standby RAM. A 0 in the RAM enablebit (RAM E) will disable the standby RAM, thereby protecting$ HITACHI 121

H06803,H06803-1---------------------------1 1511515X 01SP 01PC 018·8il Accumulalors A and B0, 16·Bil Double Accumulalor 0Index Regi"" (XISlack Poinler (SPIProg,am Counler !PCIFigure 15 CPU Programming ModelCondition Code Regi"er (CCRIC.ry/Borrow from MS8OverllowZeroNegativeInterruptHall c.ry (From 8il31• CPU Addressing ModesThe H06803 8-bit microcomputer unit has seven addressmodes that can be used by a programmer, with the addressingmode a function of both the type of instruction and the codingwithin the instruction. A summary of the addressing modes fora particular instruction can be found in Table II along with theassociated instruction execution time that is given in machinecycles. With a clock frequency of 4 MHz, these times would bemicroseconds.Accumulator (ACCX) AddressingIn accumulator only addressing, either accumulator A oraccumulator B is specified. These are one-byte instructions.Immediate AddressingIn immediate addreSSing, the operand is contained in thesecond byte of the instruction except LOS and LDX which havethe operand in the second and third bytes of the instruction.The CPU addresses this location when it fetches the immediateinstruction for execution. These are two or three-byte instructions.122_HITACHI

----------------------------H06803,H06803-1Table 7 Accumulator & Memory InstructionsCondition Code! Addressing ModesAegisterOperations BooleanlMnemonic IMMED DIAECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0IOP - # OP - # OP - # OP - .. OP - # H I N z vicAdd ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-A t • III t tADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B t I I I t·Add Double ADDD C3 4 3 03 5 2 E3 6 2 F3 6 3 A:B+M:M+l -. A: B • • I I I IAdd Accumulators ABA I lB 2 1 A + B- A t i. I IIIiT-Add With Carry ~CA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A I I. I t I IADCB C9 2 2 09 3 2 E9 4 2+_9 4 3 'B+M+C-B t !. I til I--t---r----AND ANDA 84 2 2 94 3 2 A4 4 2 iB4 4 3 A'M-A·:. t t IA I.I :A I.ANDB C4 2~ID4 3 2 E4 4 2 iF4 4 3 B·M-B • IBit Test BIT A 85 2 2 95 3 2 A5 4 2 'B5 4 3 A·M • • t I IA I.BIT B C5 212 05 3 2 E5 4 2 T F5 4 3 B'M • ·t I Ai·Clear CLA 6F 6 2 7F 6 3 00- M • 'AS AlACLAA 4F 2 1 OO-A • • A S A ACLAB 5F 2 1 00 - B • • A S A ACompare CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3 A-M • • I I I ICMPB Cl 2 2 01 3 2 El '4 2 Fl 4 3 B-M• • I I I tCompareCBA 11 2 1 A-BAccumulators • • t I t tComplement, l's COM 63 6 2 73, 6 3 M-M • • I I A SCOMA 43 2 1 A -+ A• • t t A SCOMB 53 2 1 B -+ B • • t I A SComplement, 2's NEG 60 6 2 70 6 3 OO-M-M • • t I 1 2(Negatel NEGA 40 2 1 00 - A- A • • I t 1 2NEGB 50 2 1 OO-B-B • • I t 1 2Converts binary add of BCDDecimal Adjust, A DAA 19 2 1• • I t t 3! characters into BCD formatDecrement DEC 6A 6 2 7A 6 3 M-l-M • • t t 4 DECA 4A 2 1 A -1 - A • • I t • 4DECB 5A 2 1 B-l-B • • I I 4 •Exclusive OA EOAA 88 2 2 98 3 2 A8 4 2 B8 4 3 A@M-A • • I I A EOAB C8 2 2 08 3 2 E8 4 2 F8 4 3 B@M- B • • t t A •Increment INC 6C 6 2 7C 6 3 M+l-+M • • I t 5 •f----- -+---~-INCA 4C 2 , A + 1 - A • • t I 5 •INCB 5C 2 1 B + 1-- B • ·I I 5•Load LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-A • • t I A •AccumulatorLDAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M -B • • t I A •Load DoubleLDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1 - B, M • AAccumulator• • I I A •Multiply Unsigned MUL 3D 10 1 AxB--A: B • • • •.1 11OA, Inclusive OAAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+M-A • • t t AI.OAAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B + M- B • • I I A •Push Data PSHA 36 3 1 A -+ Msp, SP - 1 • SP• • • • · I.PSHB 37 3 1 B - Msp, SP - 1 - SP • ·• • • Pull Data PULA 32 4 1 SP + 1 - SP, Msp - A • • PULB 33 4 1 SP + 1 -+ SP, Msp - B • • • • •Aotate Left AOL 69 6 2 179 6 3:} 1.01 I I 6 IIROLA 49 2 1 I I I I I I liJ r----r---• I 1- 6 IB C b7 bOROLB 59 2 1 • • I t 6 I IAotate Right ROR 66 6 2 76 6 3• :} C{]:i II~I I 6+rRORA 46 2 1 I I I I I t t 6 t~ C b1 bORORB : 56 2 1 B• • t t 6 tThe Condition Code Register notes are listed after Table 10.(Contmu'!d)$ HITACHI 123

H06803,H06803-1----------------------------Table 7 Accumulator & Memory Instructions (Continued)Condition CodeAddressing ModesRegisterOperations I Mnemonic Boolean!IMMED. DIREcr INDEX EXTEND IMPLIED5 4 3 2 1 0Arithmetic OperationOP i

--~-'-c-----------------------------H06803,H06803-1• New InstructionsIn addition to the existing 6800 Instruction Set, the following new instructions areincorporated in the HD6803 Microcomputer.ABX Adds the 8-bit unsigned accumulator B to the 16·bit X-Register taking into accountthe possible carry out of the low order byte of the X-Register.AD DO Adds the double precision ACCD* to the double precision value M:M+I and plal."Csthe results in ACCD.ASLD Shifts all bits of ACCD one place to the left. 8it 0 is loaded wittrzero. The C bit isloaded from the most significant bit of ACCD.LDD Loads the contents of double precision memory locatIOn into the doubleaccumulator A:B. The condition codes are set according to the data.LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bitis loaded from the least significant bit to ACCD.MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator 8 to obtain a16-bit unsigned number in A:B, ACCA contains MS8 of result.PSHX The contents of the index register is pushed onto the stack at the address containedin the stack pointer. The stack pointer is decremented by 2.PULX The index register is pulled from the stack beginning at the current addresscontained in the stack pointer +1. The stack pointer is incremented by 2 in total.STD Stores the contents t:>f double accumulator A:B in memory. The contents of ACCDremain unchanged.SUBD Subtracts the contents of M:M + I from the contents of double accumulator ABand places the result in ACCD.BRN Never branches. If effect, this instruction can be considered a two byte NOP (Nooperation) requiring three cycles for execution. -CPX Internal processing modified to permit its use with any conditional branch instruction.*ACCD'is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulatoris the most significant byte.Table 8 Index Register and Stack Manipulation InstructionsPointer OperationsMnemonicAddressing Modes--,---,.---- BooleanlIMMED. DIAECT INDEX EXTND IMPLIED ArithmetiC OperatIOnOP - .. OP - #OP - .. OP -::OP - '"Compare Index Aeg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 X-M:M+1-----Decrement Index Aeg DEX 09 3 1 X -1 .... X----------- Decrement Stack Pntr DES34 3 1 SP - 1 .... SPIncrement Index Aeg INX 08 3 1 X + 1 .... XIncrement Stack Pntr INS 31 3 1 SP + 1 .... SPLoad Index Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M .... XH. (M+1) .... XLLoad Stack Pntr LOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M .... SP H . (M+1) .... SP LStore Index Aeg STX OF 4 2 EF 5 2 FF 5 3 XH .... M.XL .... (M+1)Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SP H .... 'III. SP L .... (M+ 1)Index Aeg .... Stack Pntr TXS 35 3 1 X -1 .... SP--f--Stack Pntr·" Index Aeg TSX 30 3 1 SP + 1 .... XAdd ABX 3A 3 1 B + X .... XPush Data PSHX 3C 4 1 XL .... Mw. SP - 1 .... SPXH .... M sP• SP - 1 .... SPPull Data PULX 38 5 1 SP + 1 .... SP. Msp .... XHSP + 1 .... SP. M sP.... XLCondition CodeRegister5 4 3 2_~EH• •I N Z·V CI• I• • • • • •I I I I I• .}) I• • (1) IA'.R•R•.(j)1 R •V I• -• • • • • ••- • • • - • • • • • •• • • • -\-The Condition Code Register notes are listed after Table 10.125

H06803,H06803-1-----------------__________ _Table 9 Jump and Branch InstructionsOperationsMnemonicAddressing ModesRELATIVE DIRECT INDEX EXTND IMPLIEDOP- # OP - # OP - # OP -#Branch TestCondition CodeRegister5 4 3 2 1 0OP - It H I N Z V CBranch Always BRA 20 3 2 None • • • ·• •Branch Never BRN 21 3 2 None • • Branch If Carry Clear BCC 24 3 :2 C=O • • • • •Branch If Carry Set BCS 25 3 2 C=1 • • • • •Branch If = Zero BEQ 27 3 2 Z=1 • • • •Branch If ;;. Zero BGE 2C 3 2 NV=O • • •-_. Branch__._ If > Zero _~~T__-t2E 3 2 Z + (N 0 VI = 0...._._---• • Branch If Higher BHI 22 3 2 IC+Z=O • • • • •Branch If..; Zero BlE 2F 3 2 Z + (N VI = 1---------• • • • • •Branch If lower OrBlS 23 3 2 C + Z = 1Same• • • • • •Branch If < Zero BlT 20 3 2 N

----------------------------H06803,H06803-1ABAABXADCADDADDDANDASLASLDASABCCBCSBEQBGEBGTBHIBITBLEBLSBLTBMIBNEBPLBAABANBSABVCBVSCBACLCCLICLACLVCMPCOMCPXDAADECDESDEXEOAINCINSTable 11Instruction Execution Times in Machine CycleACCX I~~:- Direct te~~~••••••2•2••••••••••••••••••••2••2••2••2•••2242••••••••2•••.,i••••••••••••2•4••••2••••353•••••••••••••••••••••••••3•5••••3••••44646•6••••••4••••••••••••••6•466•6•46•In- 1mdexedplied• 2•446466••••••4••••••••••••••6•466•6••46'.3•••••3•••••••••••••••••••222•2•••2•33••3Aelative••••••••33333•3333333363••••••••••••••INXJMPJSALOALDDLOSLOXLSRLSADMULNEGNOPOAAPSHPSHXPULPULXAOLAOAATIATSSBASBCSECSEISEVSTASTDSTSSTXSUBSUBDSWITABTAPTBATPATSTTSXTXSWAI~HITACHIACCX•••••••2••2••3•4•22••••••••••••••••••2••••••2333•••••2•••••••••2•••••••4•••••••••••53444•••••3•••••••••3•••344435••••••••••3645556••6•4••••66•••4•••455546•••••6••••3645556••6•4•Implied3•••••••310•2••4•5••1052•222••••••122222•339Aelative•••••••••••••••••••••••••••••••••••••••••127

H06803,H06803-1-----------------------------• Summary of Cycle by Cycle OperationTable ) 2 provides a detailed description of the informationpresent on the Address Bus. Data Bus, and the Read/Write line(R/W) during each cycle for each instruction.This information is useful in comparing actual with expectedresults during debug of both software and hardware as thecontrol program is executed. The information is categoriled ingroups according to addressing mode and number of cycles perinstruction. (In general. instructions with the same addressingmode and number of cycles execute in the same manner: eXceptionsare indicated in the table).Table 12 Cycle by Cycle OperationAddress Mode &InstructionsAddress BusData BusIMMEDIATEADC EORADD LDAAND ORABIT SBCCMP SUB2I1 Op Code Address 12 Op Code Address + 1 1Op CodeOperand DataLDSLOXLDD31 Op Code Address 12 Op Code Address + 1 13 Op Code Address + 2 1Op CodeOperand Data (High Order Byte)Operand Data (low Order Byte)CPXSUBDADDD41 Op Code Address 12 Op Code Address + 1 13 Op Code Address + 2 14 Address Bus F F F F 1Op CodeOperand Data (High Order Byte)Operand Data (low Order Byte)Low Byte of Restart VectorDIRECTADC EORADD LDAAND ORABIT SBCCMP SUBSTALDSLDXLDDSTSSTXSTDCPXSUBDADDDJSR334I 455IIIII1 Op Code Address 12 Op Code Address + 1 13 Address of Operand 11 Op Code Address 12 Op Code Address + 1 1I3 I Destination Address 01 I Op Code Address 12 Op Code Address + 1 13 ; Address of Operand 14 Operand Address + 1 11 Op Code Address 12 Op Code Address + 1 13 Address of Operand 04 Address of Operand + 1 01 Op Code Address 12 Op Code Address + 1 13 Operand Address 14 Operand Address + 1 15 Address Bus F F F F 11 Op Code Address 12 Op Code Address + 1 13 Subroutine Address 14 Stack Pointer 05 Stack Pointer + 1 0lOP Cod

----------------------------H06803,H06803-1Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusINDEXEDJMP 3 123---1------1-ADC EOR 4 1ADD LOA 2AND ORA 3BIT SBC 4CMP SUB---------------------- ---------STA 4 1234LOS----~5 1LOX 2LDD 3LOO 45STS 5 1STX 2STD 345ASL LSR 6 1ASR NEG 2CLR ROL 3COM ROR 4DEC TST* 5INC 6----.---- -------- ---- -------CPX 6 1SUBD 2ADDD--_.3456JSR 6 123456Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register Plus Offset 1 Operand Data-.--Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register Plus Offset 0 Operand Data --------Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register Plus Offset 1 Operand Data (High Order Byte)Index Register Plus Offset + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus FFFF 1 Low Byte of Restar,t VectorIndex Register Plus Offset 0 Operand Data (High Order Byte)Index Register Plus Offset + 1 0 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register Plus Offset 1 Current Operand DataAddress Bus F F F F 1 Low Byte of Restart VectorI-Index Register Plus Offset 0 New Operand Data--~-Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register + Offset 1 Operand Data (High Order Byte)Index Register + Offset + 1 1 Operand Data (Low Order Byte)Address Bus F F F F 1 Low Byte of Restart Vector' Op Code Address 1 Op CodeOp Code Address + 1 1 OffsetAddress Bus F F F F 1 Low Byte of Restart VectorIndex Register + Offset 1 First Subroutine Op CodeStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)• In the TST Instruction, R/W line of the sixth cycle is "'" level, and AB = FFFF, DB = Low Byte of Reset Vector.(Continued)_HITACHI 129

HD6803,HD6803-1---------------------------Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusEXTENDEDJMPADC EORADD LOAAND ORABIT SBCCMP SUBSTALOSLOXLDDSTSSTXSTDASL LSRASR NEGCLR ROLCOM RORDEC TST-INCCPXSUBDADDDJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 Op CodeOp Code Address + 1 1 Jump Address (High Order Byte)Op Code Address + 2 1 Jump Address (Low Order Byte)Op Code Address 1 OpCodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Destination Address (High Order Byte)Op Code Address + 2 1 Destination Address (Low Order Byte)Operand Destination Address 0 Data from AccumulatorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand Data (High Order Byte)Address of Operand + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 0 Operand Data (High Order Byte)Address of Operand + 1 0 Operand Data (Low Order Byte)Op Code Address 1 OpCodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Current Operand DataAddress Bus F F F F 1 Low Byte of Restart VectorAddress of Operand 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Operand Address (High Order Byte)Op Code Address + 2 1 Operand Address (Low Order Byte)Operand Address 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Address Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Subroutine (High Order Byte)Op Code Address + 2 1 Address of Subroutine (Low Order Byte)Subroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)-• In the TST instruction, R/W line of the sixth cvcle is "'" level, and AB = FFFF, DB = Low Byte of Reset Vector.(Continued)130 ~HITACHI

---------------------------H06803,H06803-1Table 12 Cycle by Cycle Operation (Continued)Address Mode &InstructionsIMPLIEDABA DAA SECASL DEC SEIASR INC SEVCBA LSR TABCLC NEG TAPCLI NOP TBACLR ROL TPACLV ROR TSTCOM SBAABXASLDLSRDDESINSINXDEXPSHAPSHBTSX_.TXSPULAPULBPSHXPULXRTSWAI--2 123 1233 1233 1233 1233 1233 1233 1234 12344 12345 123455 123459 1234Address BusData BusOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionIIiOp Code Address 1 I Op CodeOp Code Address + 1 1 i Irrelevant DataAddress Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataAddress Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionPrevious Register Contents 1 Irrelevant DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionAddress Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 0 Accumulator DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 1 Irrelevant DataOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionAddress Bus FFFF 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Op Code of Next InstructionStack Pointer 1 Irrelevant DataStack Pointer + 1 1Op Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataStack Pointer 0 Index Register (Low Order Byte)Stack Pointer - 1 0 Index Register (High Order Byte;Op Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant DataStack Pointer 1 Irrelevant DataStack Pointer + 1 1 Index Register (High Order Byte)Stack Pointer +2 1 Index Register (Low Order Byte)Op Code Address 1 OpCodeOp Code Address + 1 1 Irrelevant DataStack Pointer 1 Irrelevant DataStack Pointer + 1 1 Address of Next Instruction(High Order Byte)Stack Pointer + 2 1 Address of Next Instruction(Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 OJ? Code of Next InstructionStack Pointer 0 Return Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)(Continued)$ HITACHI 131

H06803,H06803-1-----------------------------Table 12 Cycle by Cycle Operation (Continued).,..Address Mode &CycleR/WInstructionsCycles:;:Address BusLineData BusWAI·· 5 Stack Pointer - 2 0 Index Register (Low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code RegisterMUL 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Address Bus FFFF 1 Low Byte of Restart Vector4 Address Bus F F F F 1 Low Byte of Restart Vector5 Address Bus FFFF 1 Low Byte of Restart Vector6 Address Bus FFFF 1 Low Byte of Restart Vector7 Address Bus FFFF 1 Low Byte of Restart Vector8 Address Bus FFFF 1 Low Byte of Restart Vector9 Address Bus FFFf 1 Low Byte of Restart Vector10 Address Bus FFFF 1 Low Byte of Restart Vector------.RTI 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Contents of Condo Code Reg.from Stack5 Stack Pointer + 2 1 Contents of Accumulator Bfrom Stack6 Stack Pointer + 3 1 Contents of Accumulator Afrom Stack7 Stack Pointer + 4 1 Index Register from Stack(High Order Byte)8 Stack Pointer + 5 1 Index Register from Stack(Low Order Byte)9 Stack Pointer + 6 1 Next Instruction Address fromStack (High Order Byte)'10 Stack Pointer + 7 1 Next Instruction Address fromStack (Low Order Byte)SWI 12 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 0 Return Address (Low Order Byte)4 Stack Pointer - 1 0 Return Address (High Order Byte)5 Stack Pointer - 2 0 Index Register (Low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code Register10 Stack Pointer - 7 1 I rrelevant Data11 Vector Address FFFA (Hex) 1 Address of Subroutine(High Order Byte)12 Vector Address FFFB (Hex) 1 Address of Subroutine(Low Order Byte)(Continued)•• While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than theoriginal contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAIinstruction.132 $ HITACHI

----------------------------------------------------------H06803,H06803-1RELATIVETable 12 Cycle by Cycle Operation (Continued)Address Mode &CyclesCycleR/WAddress BusInstructions # lineData BusBCC BHT BNE· 3 1 Op Code Address 1 Op CodeBCS BLE BPL 2 Op Code Address + 1 1 Branch OffsetBEQ BLS BRA 3 Address Bus F F F F 1 Low Byte of Restart VectorBGE BLT BVCBGT BMT BVSBRNBSR 6 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Br anch Offset3 Address Bus FFFF 1 Low Byte of Restart Vector4 Subroutine Starting Address 1 Op Code of Next Instruction5 Stack Pointer 0 Return Address (Low Order Byte)6 Stack Pointer - 1 0 Return Address (High Order Byte)• Summary of Undefined Instruction OperationsThe HD6803 has 36 underfined instructions. When these arecarried out, the contents of Register and Memory in MPUchange at random.When the op codes (4E. SE)are used to execute. the MPUcontinues to increase the program counter and it will not stopuntil the Reset signal enters. These op codes are used to test theLSI.Table 13 Op codes MapHD6803 MICROPROCESSOR INSTRUCTIONSOP ACC ACCCODE A BLO~INDEXTACCA orSPACCB or XIMM I DIR IINDt EXT IMM I DIR liND I E~0000 0001 0010 0011 0100 0101 0110 0111 1000110011'O'0j 1011 1100 11101111101,1110 1 2 3 4 5 6 7 S j 9 j A j B C I 0 I E I F0000 0 SBA BRA TSX NEG SUB 00001 1 ----------- ------NOP CBA BRN INS ~ CMP 1-- --0010 2 ~BHI PULA (+1) SBC 2--t---0011 3 ~. BLS PULB (+1) COM SUBD (+2)I· ADDD (+2) ~0100 4 LSRD (+1)BCC DES LSR AND 14BCS TXS BIT ' 50110 6 TAP ---- TAB BNE PSHA ROR LOA 60101 5 ASLD (+1)~---0111 7 TPA TBA BEQ PSHB ASR~STA ~ STA i 71000 S INX (+1) ~ BVC PULX (+2) ASL EOR S1001 9 DEX (+1) DAA BVS RTS (+2) ROl ADC 91010 A CLV ~BPL ABX DEC ORA A1011 B SEV ABA 8MI RTI (+7) ~ ADD ~B1100 C CLC ~. BGE PSHX (+1) INC CPX (+2) LDD (+1) ;C· -~-1101 0 SEC/BLT MUL (+7) TST BSR 1(+4)JSR (+2) k (+111 STD (+1) !D~.E CliBGT WAI (+61 - .. -- 1110JMP (-31 . LOS (+11 LOX (+11· I E1111 F SEI ~- BLE SWI (+9) CLR ; (+lil STS (+1) • (+1~ STX (+1) FBYTE/CYCLE 1/2 1/2 2/3 1/3 1/2 i 112 2/6 3/6 2/2 1 2/31 2/4 i 3/4 2/2 I 2/3 I 2/4 I 3/4[NOTES) 11 Undefined Op codes are marked with ~ .21 ( ) indicate that the number in parenthesis must be added to the cycle count for that instruction.31 The instructions shown below are all 3 bytes and are marked with ......Immediate addressing mode of SUBD, CPX, LDS, ADDD, LDD and LDX instructions, and undefined op codes(SF, CD, CFI.41 The Op codes (4E, 5E) are 1 byte/" cycles instructions, and are marked with ......~HITACHI 133

- ~%oca2%oCJ)~.-e%~(')~·SCI = TIE·TORE + RIE'(RORF + ORFE)Vector- PCNMI FFFC FFFOSWI FFFA FFF8IRQ, FFF8 FFF9ICF FFF6 FFF7OCF FFF4 FFF5TOF FFF2 FFF3SCI FFFO FFF1Non-Maskable InterruptSoftware InterruptMaskable Interrupt Request 1Input Capture InterruptOutput Compare InterruptTimer Overflow InterruptSCI Interrupt (TORE + RORF + ORFE)AFigure 16 Interrupt Flowchart

----------------------------H06803,H06803-1Address BusData BusFi9ure 17 HD6803 MPU Expanded Multiplexed Bus~HITACHI 135

HD6805S1--~----------­MCU (Microcomputer Unit)The HD680SS1 is the 8-bit Microcomputer Unit (MCU)which contains a CPU, on-chip clock, ROM, RAM, I/O andtimer. It is designed for the user who needs an economicalmicrocomputer with the proven capabilities of the HD6800-based instruction set.The following are some of the hardware and softwarehighlights of the M CU.• HARDWARE -FEATURES• 8-Bit Architecture• 64 Bytes of RAM• Memory Mapped I/O• 1100 Bytes of User ROM• Internal 8-Bit Timer with 7·Bit Prescaler• Vectored Interrupts - External and Timer• 20 TTL/CMOS Compatible '1/0 Lines; 8 Lines LEDCompatible• On-Chip Clock Circuit• Self-Check Mode• Master Reset• Low Voltage Inhibit• Complete Development System Support by Evaluationkit• 5 Vdc Single Supply• Compatible with MC6B05P2• SOFTWARE FEATURES• Similar to HD6BOO• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM, RAM and I/O• Compatible with MC6B05P2...A,Port A'JA A,1/0 A4Llnfl A,A.A,TlMER-PortARegOat.0"RegHD6805S1P• PIN ARRANGEMENTVss 1INTVeeEXTAL 4XTALNUMTIMER 7C.C,C,C,B.B,B,• BLOCK DIAGRAMAccumuilitorAIndu8 Reglst" XSConditionCod.Register CCcpu(DP·28)HD6805S1(Top View)cpuControlALUA,A.A.A.a,a.a fa.B,I.I,I, Por,I, I10 I/OIt LinesI,I,C. Po"C, CC, I/OC, Linn1100.8ROMSelf checkROM136 eHITACHI

---------------------------------------------------------------HD6805S1• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee • -0.3 - +7.0Input Voltage (EXCEPT TIMER) . -0.3 ..... +7.0V inInput Voltage (TIMER)-0.3 -+12.0Operating Temperature Topr o -+70Storage Temperature T stg - 55-+150UnitVVV°c°c• With respect to Vss (SYSTEM GNO)(NOTE)Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be underrecommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vcc·5.25V ± O.5V, Vss=GND, Ta=D-+70°C, unless otherwise noted.)Input "High" VoltageInput "High" Voltage TimerInput "Low" VoltagePower Dissipationlow Voltage RecoverLow Voltage InhibitItem Symbol Test ConditionRESINTAll OtherTimer ModeSelf -Check ModeRESV IHINT--EXTAl(Crystal Mode)VILAll OtherTIMERPoLVRI nput Leak Current INT IlL V;n=0.4V-VeeEXTAl(Crystal Mode)LVImin typ max Unit4.0 - Vee V3.0 - Vee V2.Q - Vee V2.0 - Vee V9.0 - 11.0 V-0.3 - 0.8 V-0.3 - 0.8 V-0.3 - 0.6 V-0.3 - 0.8 V- - 700 mW- - 4.75 V- 4.0 - V-20 - 20 p.A-50 - 50 p.A-1200 - 0 p.A• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GND, Ta=O - +70°C, unless otherwise noted.)Item Symbol Test ConditionClock FrequencyfelCycle Time---.tcycOscillation Frequency (External Resistor Mode) tEXT Rep=15.0kH±1%INT Pulse WidthRES Pulse WidthTIMER Pulse WidthOscillation Start·up Time (Crystal Mode)tlWLt RwLtTWLtoseCL =22pF±20%.Rs =60n max.Delay Time Reset tRHL External Cap. = 2.2 p.FInput Capacitance ! XTAlAll OtherC;n V;n=OVImin typ max Unit0.4 - 4.0 MHz1.0 - 10 p.s- 3.4 - MHztcyc + 1 -250- nstCyc+250 --+ - nst Cyc +250I - - ns- - 100 ms,laO - - ms- - 30 pF- - 10 pF$ HITACHI137

HD6805S1-------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5 25V ± 0 5V Vss = GND Ta = 0"" +70°C, unless otherWise noted;)ItemOutput "High" VoltageOutput "Low" VoltageInput "High" VoltageInput "Low" VoltageInput Leak CurrentPort APort BPortCPort A and CPort BPort A, B, CPortAPort B, CSymbolVOHVOLVIHVILIlLTest Condition min typIOH = -10~A 3.5 -IOH = -100~A 2.4 -IOH = -200~A 2.4 -IOH = -1 mA 1.5 -IOH = -100~A 2.4 -IOL = 1.6 mA - -IOL = 3.2mA - -IOL = 10mA - -2.0 --0.3 -Vin = 0.8V -500 -Vjn = 2V -300 -Vjn = 0.4V"" Vee -20 -maxUnit- V- V- V- V- V0.4 V0.4 V1.0 VVeeV0.8 V- ~A- .~A20 ~ATTL Equiv. (Port BITTL Equiv. (Port A and CIVeeTest PointViIi s3.2mATest PointIi = 1.6mAo-.----~~----~----~---.Vi2.4kSl40pF12kn30pF24 kn(NOTE)1. Load capacitance includes the floating capacitance of the probe and the jig etc.2. All diodes are 182074 or equivalent.Figure 1 Bus Timing Test Loads• SIGNAL DESCRIPTIONThe input and output signals for the MCU, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee .ndVssPower is supplied to the MCU using these two pins. VCC is+5.25 V ±O.S V. VSS is the ground connection.• INTThis pin provides the capability for asynchronously applyingan external interrupt to the MCU. Refer to INTERRUPTS foradditional information.• XTAL.Rd EXTALThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum), a resistor or an externalsignal can be connected to these pins to provide a system clockwith various stability/tost tradeoffs. Refer to INTERNAL OS­CILLATOR OPTIONS for recommendations about these inputs.• TIMERThis pin allows an external input to be used to decrement theinternal timer circuitry. Refer to TIMER for additional informationabout the timer circuitry.• RESThis pin allows resetting of the MCU at times other than theautomatic resetting capability already in the MCU. Refer toRESETS for additional information.• NUMThis pin is not for user application and should be coMectedto Vss.• Input/Output Lines (Ao .... A" Bo - B,. Co .... C])These 20 lines are arranged into tow 8-bit ports (A and 8)and one 4-bit port (C). All lines are programmable as eitherinputs or outputs under software control of the Data DirectionRegisters (DDR). Refer to INPUT/OUTPUT for additionalinformation.138 _HITACHI

-----------------------------------------------------------------HD6805S1• MEMORYThe MCU memory is configured as shown in Figure 2. Duringthe processing of an interrupt, the contents of the CPU registersare pushed onto the stack in the order shown in Figure 3. Sincethe stack pointer decrements during pushes, the low order byte(peL) of the program counter is stacked first; then the highorder three bits (PCH) are stacked. This ensures that theprogram counter is loaded correctly as the stack pointerincrements when it pulls data from the stack; A subroutine callwill cause only the program counter (PCH, PCL) contents to bepushed onto the stack.Caution: - Self Test ROM Address AreaSelf test ROM locations can not be used for a user program.If the user's program is in this location, it will be removed whenmanufacturing mask for production.000127128255256959960192319242039204020477I/O PortsTimerRAM(128 Bytes)Page ZeroROM(128 Bytes)Not UsedROM(704 Bytes)MainROM(964 Bytes)Self CheckROM(116 Bytes)InterruptVectorsROM(8 Bytes)o$00IS: $0o$07 FoF$10o$3B F$3Co$78 3$78 4$7F 7$7F 8$7F Fo12345678910636412 ~7 6 5 4 3 2Port APort B1 1 1 1IPortCNot UsedPort A DDRPort B DDRNot Used IPort C DDRNot UsedTimer Data RegTimer CTR L RegNot Used (54 Bytes)RAM (64 Bytes)St~ck-Write only registerso$000$001$002$003$004-$005-$006-$007$008$009$OOA$03F$040$07FFigure 2 MCU Memory Configuration6 5 4 3 2 0 Pulln-4 1 1 1 l ConditionCode Registern+1n-3 Accumu lator n+2n-2 Index Registern-1 1 1 1 111n+3PCH* n+4n PCL- n+5Push* For subroutine calls. only PCH and PCL are stackedFigure 3 Interrupt Stacking Order10I101 0 1 0 1 0 101PC5 4111AXSP0I Accumulator0I Index Register0Program CounterI0Stack PointerICondition Code RegisterCarry/BorrowZeroNegativeInterrupt Maskl...-______ Half CarryFigure 4 Programming Model$ HITACHI139

H o 8805S 1----------------------------------------------------------• REGISTERSThe CPU has five registers available to the programmer.They are shown in Figure 4 and are explained in the followingparqraphs.• Alcumullltor (A)The accumulator is a general purpose g·bit register used tohold operands and results of arithmetic calculations or datamanipulations.• Index R .. ister (X)The index register is an g·bit register used for the indexedaddressing mode. It contains an S·bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for lim ited calculations and datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Prognm Counter (PC)The program counter is an Il·bit register that contains theaddress of the next instruction to be executed.• StICk Pointer (SP)The stack pointer is an II·bit register that contains theaddress of the next free'location on the stack. Initially, thestack pointer is set to location $07F and is decremented as datais being pushed onto the stack and incremented as data is beingpulled from the stack. The six most significant bits of the stackpointer are permanently set to 000011. During a MCU reset orthe reset stack pointer (RSP) instruction, the stack pointer is setto location $07F. Subroutines and interrupts may be nesteddown to location $061 which allows the programmer to use uptol S levels of subroutine calls.• Condition Code Aegistw ICC)The condition code register is a S-bit register in which eachbit is used to indicate or flag the results of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Eachindividual condition code register bit is explained in thefonowing paragraphs.Half Carry (H)Used during arithmetic operations (ADD and ADC) toindicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask the timer and external interrupt (INT).If an interrupt occurs while this bit is set it is latched and will beprocessed as soon as the interrupt bit is reset.Negative IN)Used to indicate that the result of the last arithmetic, logicalor data manipulation was negative (bit 7 in result equal to alogical one).Zero (Z)Used to indicate that the result of the last arithmetic. logicalor data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the arithmeticlogic unit (ALU) occurred during the last arithmetic operation.This bit is also affected during bit test and branch instructions.shifts, and rotates.• TIMERThe MCU timer circuitry is shown in Figure 5. The 8-bitcounter, the Timer Data Register (TOR), is loaded under pro·gram control and counts down toward zero as soon as the clockinput is applied. When the timer reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register (TCR) isset. the CPU responds to this interrupt by saving the presentCPU state on the stack, fetching the timer interrupt vector fromlocations $7F8 and $7F9 and executing the interrupt routine.The timer interrupt can be masked by setting the timer inter·rupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in theCondition Code Register also prevents a time interrupt frombeing processed., The clock input to the timer can be from an external sourceapplied to the TIMER input pin or it can be the internal qn.signal. When the 4>2 signal is used as the source, it can be gatedby an input applied to the TIMER input pin allowing the user1/>,(Internal)TimerInputPinr··---.,• •I •IL I _____"•TIR; Timer Interrupt RequestTIM; Timer Interrupt MaskManufacturingMask OptionsWriteReadWriteReadFigure 5 Timer Block Diagram140 _HITACHI

---------------------------------------------------------------HD6805S1·to easily perform pulse-width measurements. The TIMER inputpin must be tied to Vee, for ungated tP2 clock input to thetimer prescaler. The source of the clock input is one of theoptions that has to be specified before manufacture of theMCV. A prescaler option can be applied to the clock input thatextends the timing interval up to a maximum of 128 countsbefore decrementing the counter (TDR). The timer continuesto count past zero, falling through to $FF from zero and thencontinuing the count. Thus, the counter (TDR) can be read atany time by monitoring the TDR. This allows a program todetermine the length of time since a timer interrupt has occurredand not disturb the counting process.At power-up or reset, the prescaler and counter are initializedwith all logical ones; the timer interrupt request bit (bit 7) iscleared, and the timer interrupt mask bit (bit 6) is set.(NOTE) If the MCV Timer is not used, the TIMER input pinmust be grounded.• SELF CHECKThe self-check capability of the MCU provides an internalcheck to determine if the part is functional.· Connect the MCUas shown in Figure 6 and monitor the output of port C bit 3 foran oscillation of approximately 3Hz .• RESETSThe MCV can be reset three ways; by initial power-up, bythe external reset input oms) and by an optional internal lowvoltage inhibit circuit, see Figure 7. All the I/O port are initializedto input mode (DDRs are cleared) during reset.During power-up, a minimum of 100 milliseconds is neededbefore allowing the trnS input to go "High".This time allows the internal crystal oscillator to stabilize.Connecting a capacitor to the ~ input, as shown in Figure 8,typically provides sufficient delay.Vee* 2.2I'F2 TNT28 RES5 XTAL4 EXTALA7 27A. 26A.25A.24A, 23A, 22A, 21Ao 20+9V 7HD6805S1TIMER(Resistor option)B7 196 NUM B. 18B, 17B. 168 Co B, 159 C, B, 1410 C, B, 1311 C, B" 12Vee = Pin 3Vss = Pin 1Figure 6 Self Check Connections• Refer to Figure 9 about c;rystal optionRESPin-------of'InternalResetFigure 7 Power Up and RES Timing·_HITACHI141

HD6805S11--------------------------------------------------------------28Figure 8 Power Up Reset Delay Circuit• INT~RNAL OSCILLATOR OPTIONSThe internal oscillator circuit is designed to require a mini-.mum of external components. A crystal, a resistor, a jumperwire, or an external signal may be used to generate a systemclock with various stability/cost tradeoff. A manufacturingmask option is required to select either the crystal oscillator orthe RC oscillator circuit. The different connection methods areshown in Figure 9. Crystal specifications are given in Figure 10.A resistor selection graph is given in Figure 11.5 XTAL5 XTALMHZ4 max c::J22PF t 20%:;+;4 EXTAL HD6805S1MCUHD6805S14 EXTAL MCUCrystalApproximately 25% AccuracyExternal: JumperVee5 XTAl5 XTAlExternalClockInput4 EXTAlHD6805S1MCURNoConnection4 EXTAlHD6805S1MCUExternal ClockCRYSTAL OPTIONSApproximately 15% AccuracyExternal ResistorRESISTOR OPTIONSFigure 9 Internal Oscillator OptionsC.XTAL~~EXTAl5.~~ 4AT - Cut Parallel Resonance CrystalC. = 7 pF max.f = 4 MHz IC. =22pFt20%)RS = 60n max.54I~ 3>uC4J:lC"~ 2LLI J1ji\ Vee = 5.25VTA = 25°C -\,\ ~~ i'-..,~~ ~Figure 10 Crystal Parameterso 5 10 1 5 20 25 30 35 40 45 50Resistance Ikn)Figure 11 Typical Resistor Selection Graph142$HI-':-ACHI

-------------------------------------------------------------HD6805S11---17F ---SPo .... DDR·sCLR INT LogicFF .... Timer7F .... Presealer7F ___ TCRStackPC,X,A,CCLoad PC FromReset: $7FE. $7FFLoad PC FromSWI :$7FC, $7FDrnT':$7FA, $7FBTIMER :$7F8, $7F9FetchInstructionYSWIExecuteInstructionFigure 12 Interrupt Processing FlowchartDataDirectionRegisterBitOutputData BitOutputStateInput toMCUFigure 13 Typical Port 1/0 Circuitry1000 03-State Pin$ HITACHI143

HD6805S1--------------------------------------------------------------• INTERRUPTSThe CPU can be interrupted three different ways: throughthe external interrupt (INT) input pin, the internal timerinterrupt request, and a software interrupt instruction (SWI).When any interrupt occurs, processing is suspended, the presentCPU state is pushed onto the stack, the interrupt bit (I) in theCondition Code Register is set, the address of the interruptroutine is obtained from the appropriate interrupt vectoraddress, and the interrupt routine is executed. The interruptservice routines normally end with a return from interrupt(RTl) instruction which allows the CPU to resume processingof the program prior to the interrupt. Table 1 provides a listingof the interrupts, their priority, and the vector address thatcontain-the starting address of the appropriate interrupt routine.A flowchart of the interrupt processing sequence is given inFigure 12.InterruptRESSWIINTTIMERTable 1 Interrupt PrioritiesPriority1234Vector Address$7FE and $7FF$7FC and $7FD$7FA and $7FB$7F8 and $7F9• INPUT/OUTPUTThere are 20 input/output pins. All pins are programmableas either inputs or outputs under software- control of the correspondingData Direction Register (DDR). When programmedas outputs, all I/O pins the latched output data is readable asinput data, regardless of the logic levels at the output pin due tooutput loading (see Figure 13). When port B is programmedfor outputs, it is capable of sinking lOrnA on each pin (VOL =IV max). All input/output lines are TTL compatible as bothinputs and outputs. Port A is CMOS compatible as outputs, andPort Band C are CMOS compatible as inputs. Figure 14 providessome examples of port connections,• BIT MANIPULATIONThe MCU has the ability to set or clear any single randomaccess lVemory or input/output bit (except the data directionregisters) with a single instruction (88ET, BCLR). Any bit inthe page zero read only memory can be tested, using the BRSETand BRCLR instructions, and the program branches as a resultof its state. This capability to work with any bit in RAM, ROMor I/O allows the user to have individual flags in RAM or tohandle single I/O bits as control lines. The example in Figure 15illustrates the usefulness of the bit manipulation and testinstructions. Assume that bit 0 of port A is connected to a zerocrossing detector circuit and that bit 1 of port A is connected tothe trigger of a TRIAC which powers the controlled hardware.This program, which uses only seven ROM locations,provides turn-on of the TRIAC within 14 microseconds of thezero crossing. The timer could also be incorporated to provideturn-on at some later time which would permit pulse-widthmodulation of the controlled power.Bo_----4r¥ l c· "'FE' IePort APort BB, ·Port A Programmed as output(s), driving CMOS and TTL Load directly.(a)Port B Programmed as output(s), driving Darlington-base directly.(b)+V+vPort B10 -mA maxB,Port C·•·C,Rt----..... -CMOS InverterPort B Programmed as output(s), driving LED(s) directly.(c)Port C Programmed as output(s), driving CMOS loads, using externalpull-Up resistors.(d)Figure 14 Typical Port Connections144 _HITACHI

---------------------------------------------------------------HD6805S1SELF 1 BRCLR 0, · PORT A, SELF 1BSET 1, PORT ABCLR 1, PORT AFigure 15 Bit Manipulation Example• ADDRESSING MODESThe CPU has ten addressing modes available for use by theprogrammer. They are explained and illustrated briefly in thefollowing paragraphs.• ImmediateRefer to Figure 16. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 17. In direct addressing, the address of theoperand is contained in the second byte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage of thisefficient memory addressing mode.• ExtendedRefer to Figure 18. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instructionsare three bytes long.• RelativeRefer. to Figure 19. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA=(pC)+2+Rel. ReI is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken Rel=O, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 of the present instruction. Theseinstructions are two bytes long.• Indexed (No Offset)Refer to Figure 20. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and their EA is the contents of the index register.• Indexed (8-bit Offset)Refer to Figure 21. The EA is calculated by adding thecontents of the byte following the opcode to the contents ofthe index register. In this mode, 511 low memory locations areaccessable. These instructions occupy two bytes.• Indexed (16-bit Offset)Refer to Figure 22. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode are threebytes long.• Bit Set/ClearRefer to Figure 23. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 24. This mode of addressing applies toinstructions which can test any bit in the first 256 locations($OO-$FF) and branch to any location relative to the PC. Thebyte to be tested is addressed by the byte following the opcode.The individual bit within that byte to be tested is addressed bythe lower three bits of the opcode. The third byte is the relativeaddress to be added to the program counter if the branch conditionis met. These instructions are three bytes long_ The value ofthe bit tested is written to the carry bit in the condition coderegister.• ImpliedRefer to Figure 25. The implied mode of addreSSing has noEA. All the information necessary to execute an instruction iscontained in the opcode. Direct operations on the accumulatorand the index register are included in this mode of addressing.In addition, control instructions such as SWI, RTI belong to thisgroup. All implied addressing instructions are one byte long.• INSTRUCTION SETThe MCV has a set of 59 basic instructions. They can bedivided into five different types: register/memory, read/modify/write, branch, bit manipulation, and control. The followingparagraphs briefly explain each type. All the instructions withina given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operand iseither the accumulator or the index register. The other operandis obtained from memory using one of the addressing modes.The jump unconditional (JMP) and jump to subroutine (JSR)instructions have no register operand. Refer to Table 2.• Read/Modity/Write InstructionsThese instructions read a memory location or a register,modify or test its contents, and write the modified value backto memory or to the register. The test for negative or zero(TST) instruction is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table3.• Branch InstructionsThe branch instructions cause a branch from the programwhen a certain condition is met. Refer to Table 4.• Bit Manipulation InstructionsThese instructions are lIsed on any bit in the first 256 bytesof the memory. One group either sets or clears. The other groupperforms the bit test and branch operations. Refer to Table 5.• Control InstructionsThe control mstructions control the MCV operations duringprogram execution. Refer to Table 6.• Alphabetical ListingThe complete instruction set is given in alphabetical order inTable 7.• Opcode MapTable 8 is an opcode map for the instructions used on theMCV.~HITACHI145

HD6805S1---------------------------------------------------------------PROG LDA #$F8 058EI§IMemoryA6iIIIII'------..f05BF F8Stack PointProg Count05COCC§IIIII ,Figure 16 Immediate Addressing ExampleCATFCB320048IIIIIII+ MemoryPROG LDA CA T 0520 B6052E 4820iIIIIIIlEAI0048 1/~Adder'" olIIA-,, 20 IIndex RegIStack PointIProg Count052FCCIII~IIFigure 17 Direct Addressing Example146 ~HITACHI

------------------------------------------------------------------HD6805S1MemoryI, ,PROG LOA CAT~0000II~~040A 06040B E5 JA40Index RegStack PointIIIIProg CountCAT FCB 6406E5 40040CCCFigure 18 Extended Addressing Example,IMemory~II0000PROG BEQ PROG2 04A7 27 i-------l04A8 1804C1EAAStack PointIndex Reg~I ,,Figure 19Relative Addressing Example~HITACHI147

HD6805S1---------------------------------------------------------------MemoryATABL FCC t Lit 00B8 4C494CIndex RegB8PROG LOA XI05F4~§IIStack PointProg Count05F5CCFigure 20 Indexed (No Offset) Addressing ExampleTABL FCB #BF 0089FCB #86 008AFCB #OB 008BPROG LOA TAB L. X 075B075CMelory,IIIIIBF86OBFCB #CF 008CCFI ,IIIE689I,008C/I'lEAtAdderI'"II,AJICFIIndex RegI 03IStack PointIProg Count0750ICCI§I , I,Figure 21Indexed (S·Bit Offset) Addressing Example148 ~HITACHI

---------------------------------------------------------------HD6805S1MeJoryIII§§IPROG LOA TAB L. X 069206930706947EITABL FCB #BF 077EBFFCB #86 077F 86FCB #OB 0780DBFCB #CF 0781CFiIIIlEAI 0780IfAdder/ ~IJIIA.J--.DBI--. rIndex Reg02 1Stack PointIIProg Count0695ICCI IFigure 22 Indexed (16-Bit Offset) Addressing ExampleMemoryPORTB EQU0001 BFAIndex RegPROG BeLR 6. PORT B 058F 10I--------t0590 01Stack PointProg Count0591II~IIICCFigure 23 Bit Set/Clear Addressing Example~HITACHI149

HD680551-------------------------------PORT C EQU 2 0002 FOAIndex RegStack Point..... ------40575 02PROG BRClR 2. PORT C. PROG 2 0574 050576 r--~l;-;D:;--;-l----.Prog Count0594CCCFigure 24 Bit Test and Branch Addressing ExampleIIIIMemoryPROGTAX~IID~A§IIAProg CountE5Index RegE5IIII05B8cc§Figure 25 Implied Addressing Example150~HITACHI

-----------------------------------------------------------------HD6805S1I_~"kTable 2Register/Memory InstructionsAddressing Modesf---------Indexed ~ Indexed IndexedFunction Immediate Direct I Extended(No Offset) I (8·8it Offset) (16·8it Offset)Op # It Op # # Op # It Op It ,. I Op It # Op # #Code 8ytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code 8ytes Cycles Code Bytes CyclesLoad A from Memory LOA A6 2 2 B6 2 4 C6 3. 5 F6 1 j 4 E6 2 5 06 3 6Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 1-4 EE 2 5 DE 3 6Store A in Memory STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7Add M~mory to A ADD AB 2 2 BB 2 4 C8 3 5 FB 1 4 EB 2 5 DB 3 6Add Memory andCarry to AAOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6Subtract Memdry fromA with BorrowS8C A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6Exclusive OR Memorywith AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory with A(Logical Compare)EOR A8 2 2 88 2 4 C8 3CMP Al 2 2 Bl 2 4 Cl 3CPX A3 2 2 B3 2 4 C3 3--I-5 F8 1 4 E8 2 5 08 3 65 Fl 1 4 El 2 5 01 3 65 F3 1 4 E3 2 5 03 3 6BIT AS 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6Jump Unconditional JMP - - - 8C 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5Jump to Subroutine JSR - - - BO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9Table 3Read/Modify/Write InstructionsAddressing ModesFunction Mnemonic Implied (AI Implied (XI DirectIndexed(No Offset)Indexed(8-Bit Offset)Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIncrement INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7Decrement DEC 4A 1 4 SA 1 4 3A 2 6 7A 1 6 6A 2 7Clear CLR 4F 1 4 SF 1 4 3F 2 6 7F 1 6 6F 2 7Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7Negate(2's Complement)NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7Logical Shift Left LSL 4B 1 4 58 1 4 38 2 6 78 1 6 68 2 7Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Test for Negative orZeroTST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7~HITACHI 151

HD6805S1----------------------------------------------------------------Table 4 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch IF Higher BHI 22 2 4Branch I F lower or Same BlS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch IF lower) (BlO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch I F Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch I F Plus BPl 2A 2 4Branch I F Minus BMI 2B 2 4Branch I F Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch I F Interrupt Line is low Bil 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AD 2 8Table 5 Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch I F Bit n is set BRSET n (n=O ..... 7) - - - 2 0 n 3 10Branch I F Bit n is clear BRClR n (n=O ..... 7) - - - 01+2 0 n 3 10Set Bit n BSET n (n=O ..... 7) 10+2 0 n 2 7 - - -Clear bit n BClR n (n=O ..... 7) 11+2 0 n 2 7 - - -FunctionTable 6 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit ClC 98 1 2Set Interrupt Mask· Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2152 ~HITACHI

-----------------------------------------------------------------HD6805S1Table 7 Instruction SetAddressing ModesCondition CodeMnemonicIndexedImme- Ex- Re-Indexed Indexed Bit I BitImpliedDirect(Nodiatetended lative(8 Bits) (16 Bits)Set/ . Test & H I N Z COffset)Clear I BranchADC x x x x x x 1\ 1\ 1\ 1\ADD x x x x x x 1\ • 1\ 1\ 1\AND x x x x x xI1\ 1\ •ASL x x x x ! 1\ 1\ 1\ASR x x x x! 1\ 1\ 1\BCC x i iBCLR x BCS x BEQ x BHCC x BHCS x BHI x BHS x BIH x BIL x • • BIT x x x x x x 1\ 1\ BLO x BLS x BMC x BMI x BMS x• • BNE x I • • BPL x BRA x BRN x •BRCLR x• • • • 1\BRSET x 1\BSET x BSR x •CLC x • aCLI x a • • CLR x x x x a 1 •CMP x x x x x x 1\ 1\ 1\COM x x x x 1\ 1\ 1CPX x x x x x x 1\ 1\ 1\DEC x x x x 1\ 1\ EaR x x x x x x 1\ 1\ INC x x x x 1\ 1\ JMP x x x x x JSR x x x x x • • LOA x x x x x x 1\ 1\ LOX x x x x x x • • 1\ 1\ •Condition Code Symbols:H Half Carry (From Bit 31 C Carry BorrowI Interrupt Mask 1\ Test and Set if True, Cleared Otherwise(to be continued)N Negative (Sign Bit) Not Affected .Z Zero~HITACHI153

HD6B05S1-----------------------------------------------------------------MnemonicImpliedAddressing ModesImme- Ex- Re-D~rectdiatetended lativeTable 7 Instruction SetCondition CodeIndexedBit Bit(NoIndexed Indexed(8 Bits) (16 Bits)Set/ Test & H I N Z COffset) Clear BranchLSL x x x x /\ /\ /\LSR x x x x 0 /\ /\NEG x x x x /\ /\ /\NOP x • • ORA x x x x x x /\ /\ •ROL x x x x /\ /\ /\ROR x x x x /\ /\ /\RSP x • • • • •RTI x ? ? ? ? ?RTS x • • •SBC x x x x x x /\ /\ /\SEC x • 1SEI x 1 • • STA x x x x x /\ /\ STX x x x x x /\ /\ •SUB x x x x x x • /\ /\ /\SWI x 1 TAX x • • TST x x x x /\ /\ TXA x• • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry/BorrowI I nterrupt Mask /\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack154 ~HITACHI

-----------------------------------------------------------------HD6805S1Table 8Opcode MapBit Manipulation Branch Read/Modify NVrite Control Register IMemoryTest & Setl Rei OIRI A I X I ,X1 I ,XC IMP IMP IMM I OIR I EXT I ,X2 I ,X1Branch Clear0 1 2 3 I 4 I 5 I 6 : 7 8 9 A I B 1 C ! 0 I E0 BRSETO BSETO BRA NEG Rn- - SUB1 BRClRO BClRO BRN - RTS- - CMP2 BRSET1 BSET1 BHI - - - SBC3 BRClR1 BClA1 BlS COM SWI- - CPX4 BRSET2 BSET2 BCC lSA - - AND5 BAClA2 BClR2 BCS - - - BIT6 BASET3 BSET3 BNE AOA - - lOA7 BRClA3 BClR3 BEQ ASR - TAX - I8 BRSET4 BSET4 BHCC lSl/ASl - ClC EOR9 BRClA4 BClR4 BHCS ROl - SEC AOCA BRSET5 BSET5 BPl DEC - CLI ORAB BAClA5 ~ClA5 BMI - - SEI ADDSTA(+1)C BRSET6 BSET6 BMC INC - RSP - I JMP(-ll0 BRClR6 BClR6 BMS TST - NOP BSA-I JSR(-3)E BASET7 BSET7 Bil - - - lOXF BAClA7 BClA7 BIH ClR - TXA - I STX(+l1(NOTE)3/10 2/7 2/4 2/6 I 1/4 I 1/4 J 2/7 11/6 1/- 112 2/2 I 2/4 I 3/5 I 3/6 I 2/51. Undefined opcodes are marked with "_".2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).Mnemonics followed by a "-" require a different number of cycles as follows:RTI 9RTS 6SWI 11BSR 83. ( indicate that the number in parenthesis must be added to the cycle count for that instruction.I,xo1 FI 1/4+- HIGH0123456789ABC0EFloW~HITACHI155

HD6805S6------·-------­MCU (Microcomputer Unit)-PRELIMINARY-The HD680SS6 is the 8·bit Microcomputer Unit (MCU)which contains a CPU, on·chip clock, ROM, RAM, I/O andHD6805S6Ptimer. It is designed for the user who needs an economicalmicrocomputer with the proven capabilities of the HD6800-based instruction set.The following are some of the hardware and softwarehighlights of the M CU.• HARDWARE FEATURES• 8-Bit Architecture• 64 Bytes of RAM• Memory Mapped I/O• 1804 Bytes of User ROM• Internal 8-Bit Timer with 7·Bit Prescaler• 20 TTL/CMOS Compatible I/O Lines; • PIN ARRANGEMENT8 Lines LED Compatible• On·Chip Clock Circuit• Self-Check Mode• Master Reset• Low Voltage Inhibit• Complete Development System Support by Evaluation kit• 5 Vdc Single Supply• Compatible with MC6805P6• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM. RAM and I/O• Compatible with MC6805P6TIMERPortAR ..c,C.B.B,B,• BLOCK DIAGRAMCondition~5 Regilt ... CCSStackPOinterSPP'09'_mCounter3 ··H ...... PCHP,ogr.mCounter"l_" PClcPu(DP·28)(Top View)cpuControlAlUA.B,B.B.B.B.8.8,8, Po,.8, 88, ItOa, lines8,8,C. Po,tC, CC, ItOc) lute.1804)1 8ROM"1')(,1Sel' checll.ROM156 $ HITACHI

HD6805S6• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee • -0.3 - +7.0Input Voltage (EXCEPT TIMER) , -0.3-+7.0YinInput Voltage (TIMER)-0.3-+12.0Operating Temperature Top/" o -+70Storage Temperature Tstg - 55 - +150UnitVVV°c°c• With respect to Vss (SYSTEM GND)(NOTE)Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be underrecommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vcc·5.25V ± O.5V, Vss=GNO, Ta=o-+70°C, unless otherwise noted.)Item Symbol Test ConditionRESInput "High" VoltageINTAll OtherVIHInput "High" Voltage TimerTimer ModeSelf-Check ModeRESInput "Low" VoltageINTEXTAL(Crystal Mode)VILAll OtherPower DissipationPoLow Voltage ReooverLVRLow Voltage InhibitLVITIMERI nput Leak Current INT IlL Vin=0.4V-V eeEXTAL(Crystal Mode)min typ max Unit4.0 - Vee V3.0 - Vee V2.0 - Vee V2.0 - Vee V9.0 - 11.0 V-0.3 - 0.8 V-0.3 - 0.8 V-0.3 - 0.6 V-0.3 - 0.8 V- - 700 mW- - 4.75 V- 4.0 - V-20 - 20 IJ.A-50 - 50 IJ.A-1200 - 0 IJ.A• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GNO, Ta=O - +70°C, unless otherwise noted.)Item Symbol T est ConditionClock FrequencyfelCycle TimeteyeOscillation Frequency (External Resistor Mode) f EXT Rep=15.0kn±1%INT Pulse WidthRES Pulse WidthTIMER Pulse WidthOscillation Start-up Time (Crystal Mode)tlWLtRWLtTWLtoseCL =22pF±20%,Rs=60n max.Delay Time Reset tRHL External Cap. = 2.2 IJ.FInput CapacitanceIIXTALAll OtherCinVin=OVmin typ max Unit0.4 - 4.0 MHz1.0 - 10 IJ.S- 3.4 - MHzteyc+250- - nst cSc+2 0- - nstcyc+250- - ns- - 100 ms100 - - ms- - 35 pF- - 10 pF_HITACHI157

HD6805S6• PORT ELECTRICAL CHARACTERISTICS (Vee = 5 25V ± 0.5V, Vss = GND, Ta = 0"'" +700C , unless otherwise noted)Item Symbol Test Condition min typIOH = -101lA 3.5 -Port AIOH = -1001lA 2.4 -Output "High" Voltage VOH IOH = -200 IJA 2.4 -Port BIOH = -1 rnA 1.5 -'Port C IOH = -10PIlA 2.4 Port A and C IOl = 1.6mA - -Output "Low" VoltageVOL IOl = 3.2mA - -Port BIOl = 10 mA - -Input "High" Voltage VIH 2.0 -Port A, B, CInput "Low" VoltageVil -0.3 -Yin = 0.8V -500 -PortAInput Leak CurrentIII Yin = 2V -300 -Port B, C Yin = 0.4V"" Vee - 20 -maxUnit- V- V- V- V- V0.4 V0.4 V1.0 VVeeV0.8 V- IlA- IJA20 IJATTL Equiv. (Port B) TTL Equiv. (Port A and C)V.ccTest Point1.2knTest Pointli= 1.6mA2.4kn40pF 30 pF 24 knVi(NOTE) 1. load capacitance includes the floating capacitance of the probe and the jig etc.2. All diodes are 182074 or equivalent.Figure 1 Bus Timing Test Loads• SIGNAL DESCRIPTION - TIMERThe input and output signals for the MCU, shown in PINARRANGEMENT, are described in the following paragraphs.- VCC and VSSPower is supplied to the MCU using these two pins. VCC is+5.25 V ± 0.5 V. VSS is the ground connection.-INTThis pin provides the capability for asynchronously applyingan external interrupt to the MCU. Refer to INTERRUPTS foradditional information.• XTAL and EXTALTl,ese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum), a resistor or an externalsignal can be connected to these pins to provide a system clockwith various stability/cost tradeoffs. Refer to INTERNALOSCILLATOR OPTIONS for recommendations about theseinputs.This pin allows an external input to be used to decrementthe internal timer circuitry. Refer to TIMER for additionalinformation about the timer circuitry.e RESThis pin allows resetting of the MCU at times other than theautomatic resetting capability already in the MCU. Refer toRESETS for additional information.eNUMThis pin is' not for user application and should be connectedto VSS .e Input/Output Lines (Ao '" A7, Bo '" B7, Co '" C3)These 20 lines are arranged into two 8-bit ports (A and B)and one 4-bit port (C). All lines are programmable as eitherinputs or outputs under software control of the data directionregisters. Refer to INPUT/OUTPUT for additional information.158 ~HITACHI

HD6805S6• MEMORYThe MCU memory is configured as shown in Figure 2. Duringthe processing of an interrupt, the contents of the CPU registersare pushed onto the stack in the order shown in Figure 3. Sincethe stack pointer decrements during pushes, the low order byte(PCL) of the program counter is stacked first; then the highorder three bits (PCH) are stacked. This ensures that theprogram counter is loaded correctly as the stack pointerincrements when it pulls data from the stack: A subroutine callwill cause only the program counter (pCH, PCL) contents to bepushed onto the stack.Caution: - Self Test ROM Address AreaSelf test ROM locations can not be used for a user program.If the user's program is in this location, it will be removed whenmanufacturing mask for production.0001271282552567I/O PortsTimerRAM(128 Bytes)Page ZeroROM(128 Bytes)MainROM(1668 Bytes)o$0 00$0 7F801\$0 FF$1 000123456787 6 5 4 3 2 0Port A $000Port B $0011 1 1 1 I Port C $002Not Used $003Port A DDR $004*Port BOOR $005*Not Used 1 Port C DDR $006*Not Used $007Timer Data Reg $00819231924203920402047Self CheckROM(116 Bytes)InterruptVectorsROM(8 Bytes)$7 83$7 84$7 F7$7 F8$7 FF9063612~Timer CTR L Reg $009Not Used (54 Bytes)$OQA$03FRAM (64 Bytes) $040Stack (31 Bytes Maximum).1'$07F*Write only registersFigure 2 MCU Memory Configurationn-46 5 4 3 2 0 PullCondition1 1 1\ Code Registern+1n-3 Accumulator n+2n-2 Index Register n+3'1-1 1 1 1 111PCH* n+4n PCL* n+510 8 7I PCH101 0 1 0 1 0 1015 4111PCLAXSP0I Accumulator0J Index Register0Program CounterI0Stack PointerIPush* For subroutine calls, only PCH and PCL are stacked.Condition Code RegisterCarry/BorrowFigure 3 Interrupt Stacking OrderZero'----- ~ NegativeInterrupt MaskHalf CarryFigure 4 Programming Model~HITACHI159

HD6805S6---------------------------------------------------------------• REGISTERSThe CPU has five registers available to the programmer.They are shown in Figure 4 and are explained in the followingparagraphs.• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of aritlunetic calculations or datamanipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddressing mode. It contains an 8-bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for limited calculations and datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is an II-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is an II-bit register that contains theaddress of the next free location on the stack. Initially, thestack pointer is set to location $07F and is decremented as datais being pushed onto the stack and incremented as data is beingpulled from the stack. The six most significant bits of the stackpointer are permanently set to 000011. During a MCU reset orthe reset stack pointer (RSP) instruction, the stack pointer is setto location $07F. Subroutines and interrupts may be nesteddown to location $061 which allows the programmer to use upto 15 levels of subroutine calls.• Condition Code Register (CC)The condition code register is a 5-bit register in which eachbit is used to indicate or flag the results of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Eachindividual condition code register bit is explained in thefollowing paragraphs.Half Carry (H)Used during arithmetic operations (ADD and ADC) toindicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask the timer and external interrupt (INT).If an interrupt occurs while this bit is set it is latched and will beprocessed as soon as the interrupt bit is reset.Negative (N)Used to indicate that the result of the last arithmetic, logicalor data manipulation was negative (bit 7 in result equal to alogical one).Zero (Z)Used to indicate that the result of the last aritlunetic, logicalor data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the aritluneticlogic unit (ALU) occurred during the last aritlunetic operation.This bit is also affected during bit test and branch instructions,shifts, and rotates.• TIMERThe MCU timer circuitry is shown in Figure 5. The 8-bitcounter, the Timer Data Register (TOR), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the timer reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register (TCR), isset. The CPU responds to this interrupt by saving the presentCPU state on the stack, fetching the timer interrupt vector fromlocations $7F8 and $7F9 and executing the interrupt routine.The timer interrupt can be maksed by setting the timer interruptmask bit (bit 6) in the TCR. The interrupt bit (I bit) in theCondition Code Register also prevents a timer interrupt frombeing processed.The clock tnput to the timer can be from an external sourceapplied to the TIMER input pin or it can be the internal 2signal. When the 2 signal is used as the source, it can be gatedby an input applied to the TIMER input pin allowing the userrP2(Internal)TimerInputPinr-----.,IIIIIIL I _____.IITI R; Timer Interrupt RequestTIM; Timer Interrupt MaskManufacturingMask OptionsWriteReadWriteReadFigure 5 Timer Block Diagram160 ~HITACHI

---------------------------------------------------------------HD6805S6to easily perform pulse-width measurements. The TIMER inputpin must be tied to Vee, for ungated tP2 clock input to thetimer prescaler. The source of the clock input is one of theoptions that has to be specified before manufacture of theMeV. A prescaler option can be applied to the clock input thatextends the timing interval up to a maximum of 128 countsbefore decrementing the counter (TOR). The timer continuesto count past zero, falling through to $FF from zero, and thencontinuing the count. Thus, the counter can be read at anytime by reading the TOR. This allows a program to determinethe length of time since a timer interrupt has occurred andnot disturb the counting process.At power-up or reset, the prescaler and counter are initializedwith all logical ones; the timer interrupt request bit (bit 7) iscleared, and the timer interrupt mask bit (bit 6) is set.(NOTE) If the MeV Timer is not used, the TIMER input pinmust be grounded.• SELF CHECKThe self-check capability of the MeU provides an internalcheck to determine if the part is functional. Connect the MCVas shown in Figure 6 and monitor the output of port C bit 3for an oscillation of approximately 3Hz.• RESETSThe MCV can be reset three ways: by initial power-up, bythe external reset input (RES) and by an optional internal lowvoltage detect circuit, see Figure 7. All the I/O port are initializedto Input mode (DOR's are cleared) during RESET.During power-up, a minimum of 100 milliseconds is neededbefore allowing the RES input to go "High".This time allows the internal crystal oscillator to stabilize.Connecting a capacitor to the RES input, as shown in Figure 8,typically provides sufficient delay.2 iNTA, 27Vee'* 2.2I'F28 RES5 XTAL4 EXTALA. 26As 25A.24A, 23A, 22A, 21C 3Ao 20+9V TIMER HD6805~6(Resistor option)"11Bo 12B, 196 NUMB. 18Bs 17B. 168 CoB3 159 C,B, 1410 C,B, 13Vee = Pin 3Vss = Pin 1Figure 6 Self Check Connections• Refer to Figure 9 about crystal optionREsPin-------.f'InternalReset------------------~Figure 7 Power Up and RES Timing~HITACHI161

HD6805S6-------------------------------------------------------------Part ofHD6805S6MCURES28• INTERNAL OSCILLATOR OPTIONSThe internal oscillator circuit is designed to require a minimumof external components. A crystal, a resistor, a jumperwire, or an external signal may be used to generate a systemclock with various stability/cost tradeoff. A manufacturingmask option is required to select either the crystal oscillatoror the RC oscillator circuit. The different connection methodsare shown in Figure 9. Crystal specifications are given in Figure10. A resistor selection graph is given in Figure 11.Figure 8 Power Up Reset Delay Circuit5 XTAL5XTAL4~:XZ c::J22PF±20%=;::t;4 EXTALHD6805S6MCU4EXTALHD6805S6MCUApproximatelV 25% AccuracyExternal: Jumper5 XTAL5 XTALExternalClockInput4 EXTALHD6805S6MCURNoConnection4 EXTAL HD~~~5S6External ClockCRYSTAL OPTIONSApproximately 15% AccuracyExternal ResistorRESISTOR OPTIONSFigure 9 Internal Oscillator Options5C.AT - Cut Parallel Resonance CrystalCo = 7 pF max.f = 4 MHz (e. =22pF±20%1Rs = 60n max.EXTAL4N:r~~I:Q)~0-fu..432\11-\~Vee = 5~25V_TA = 25 C\ ~"- ~" ~ '-Figure 10 Crystal Parameters162~HITACHIo 5 10 1 5 20 25 30 35 40 45 50Resistance (knlFigure 11 Typical Resistor Selection Graph

-------------------------------------------------------------HD6805S61-1$7F -SPo -DDR'sCLR 1 NT Logic$FF -Timer$7F _ Prescaler$7F _ TCRStackPC,X,A,CCLoad PC FromReset: $7FE, $7FFTIMERLoad PC FromSW I: $7FC, $7FDINT: $7FA, $7FBTIMER: $7F8, $7F9FetchInstructionYSWIExecuteInstructionFigure 12 Interrupt Processing FlowchartFigure 13 Typical Port I/O CircuitryDataDirectionRegisterBit1oOutputData BitoxOutputStateo3-StateInput toMCUoPin~HITACHI163

HD6805S6---------------------------------------------------------------• INTERRUPTSThe CPU can be interrupted three different ways: throughthe external interrupt (iN'i') input pin, the internal timerinterrupt request, and a software interrupt instruction (SWI).When any interrupt occurs, processing is suspended, the presentCPU state is pushed onto the stack, the interrupt bit (I) in theCondition Code Register is set, the address of the interruptroutine is obtained from the appropriate interrupt vectoraddress, and the interrupt routine is executed. The interruptservice routines normally end with a return from interrupt(RTI) instruction which allows the CPU to resume processingof the program prior to the interrupt. Table 1 provides a listingof the interrupts, their priority, and the vector address thatcontain-the starting address of the appropriate interrupt routine.A flowchart of the interrupt processing sequence is given inFigure 12.InterruptRESSWIINTTIMERTable 1 Interrupt PrioritiesPriority1234Vector Address$7FE and $7FF$7FC and $7FD$7FA and $7FB$7F8 and $7F9• INPUT/OUTPUTThere are 20 input/output pins. All pins are programmableas either inputs or outputs under software control of the correspondingdata direction register (DDR). When programmed asoutputs, the latched output data is readable as input data,regardless of the logic levels at the output pin due to outputloading (see Figure 13). When port B is programmed for outputs,it is capable of sinking IO rnA on each pin (VOL = IVmax). All input/output lines are TTL compatible as both inputsand outputs. Port A are CMOS compatible as outputs, andPort Band C are CMOS compatible as inputs. Figure 14 providessome examples of port connections.• BIT MANIPULATIONThe MCV has the ability to set or clear any single randomaccess memory or input/output bit (except the data directionregisters) with a single instruction (BSET, BCLR). Any bit inthe page zero read only memory can be tested, using the BRSETand BRCLR instructions, and the program branches as a resultof its state. This capability to work with any bit in RAM, ROMor I/O allows the user to have individual flags in RAM or tohandle single I/O bits as control lines. The example in Figure 15illustrates the usefulness of the bit manipulation and testinstructions. Assume that bit 0 of port A is connected to a zerocrossing detector circuit and that bit 1 of port A is connected tothe trigger of a TRIAC which powers the controlled hardware.This program, which uses only seven ROM locations,provides turn-on of the TRIAC within 14 microseconds of thezero crossing. The timer could also be incorporated to provideturn-on at some later time which would permit pulse-widthmodulation of the controlled power.AoPort AA, ·Port BB,Port A ?rogrammed as output(s), driving CMOS and TTL Load directly,(a)Port B Programmed as output(s), driving Darlington base directly.(b)+VR+VRPort B10 -mA maxB,Port C·C,1----.... -.. CMOS InverterPort B Programmed as output(s), driving LED(s)' directly_(e)Port C Programmed as output(s), driving CMOS loads, using externalpull-Up resistors.(d)Figure 14 Typical Port Connections164 ~HITACHI

-----------------------------------------------------------------HD6805S6··SELF 1 BRCLR 0, PORT A, SELF 1BSET 1, PORT ABClR 1, PORT AFigure 15 Bit Manipulation Example• ADDRESSING MODESThe CPU has ten addressing modes available for use by theprogrammer. They are explained and illustrated briefly in thefollowing paragraphs.• ImmediateRefer to Figure 16. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 17. In direct addressing, the address of theoperand is contained in the second byte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage of thisefficient memory addressing mode.• ExtendedRefer to Figure 18. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instructionsare three bytes long.• RelativeRefer to Figure 19. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA=(pC)+2+Rel. ReI is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken Rel=O, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 of the present instruction. Theseinstructions are two bytes long.• Indexed (No Offset)Refer to Figure 20. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and'their EA is the contents of the index register.• Indexed (8-bit Offset)Refer to Figure 21. The EA is calculated by adding thecontents of the byte following the opcode to the contents ofthe index register. In this mode, 511 low memory locations areacce~sable. These instructions occupy two bytes.• Indexed (16-bit Offset)Refer to Figure 22. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode are threebytes long.• Bit Set/ClearRefer to Figure 23. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 24. This mode of addressing applies toinstructions which can test any bit in the first 256 locations($OO-$FF) and branch to any location relative to the PC. Thebyte to be tested is addressed by the byte following the opcode.The individual bit within that byte to be tested is addressed bythe lower three bits of the opcode. The third byte is the relativeaddress to be added to the program counter if the branch conditionis met. These instructions are three bytes long. The value ofthe bit tested is written to the carry bit in the condition coderegister.• ImpliedRefer to Figure 25. The implied mode of addressing has noEA. All the information necessary to execute an instruction iscontained in the opcode. Direct operations on the accumulatorand the index register are included in this mode of addressing.In addition, control instructions such as SWI, RTI belong to thisgroup. All implied addressing instructions are one byte long.• INSTRUCTION SETThe MCU has a set of 59 basic instructions. They can bedivided into five different types: register/memory, read/modify/write, branch, bit manipulation, and control. The followingparagraphs briefly explain each type. All the instructions withina given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operand iseither the accumulator or the index register. The other operandis obtained from memory' using one of the addressing modes.The jump unconditional (JMP) and jump to subroutine (JSR)instructions have no register operand. Refer to Table 2.• Read/Modify/Write InstructionsThese instructions read a memory location or a register,modify or test its contents, and write the modified value backto memory or to the register. The test for negative or zero(TST) instruction is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table3.• Branch InstructionsThe branch instructions cause a branch from the programwhen a certain condition is met. Refer to Table 4.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 256 bytesof the memory. One group either sets or clears. The other groupperforms the bit test and branch operations. Refer to Table 5.• Control InstructionsThe control instructions control the MCU operations duringprogram execution. Refer to Table 6.• Alphabetical ListingThe complete instruction set is given in alphabetical order inTable 7.• Opcode MapTable 8 is an opcode map for the instructions used on theMCU.~HITACHI 165

HD6805S6------------------------------------------------------------------MemoryI~IPROG LOA #$F8 05BE A6I------t05BF F8IIStack PointProg Count05COCCI~IIIIIFigure 16 Immediate Addressing ExampleMelory,i•, I I ,L/'lEA004BJAdderCAT FCB 32 OO4B 20 JoPROG LOA CAT 0520 B6052E4BI~• I, I, ., :, ,I~IA-,20IIndex RegI IIStack PointI IIProg Count052FICCFigure 17 Direct Addressing Example166 ~HITACHI

---------------------------------------------------------------HD6805S6IMemoryiIIIPROG LOA CAT~0000040A~oo~06040B ES JA40Index RegStack PointCAT FCB 64I•I•06ES 40Prog Count040CCCFigure 18 Extended Addressing ExampleMemory§IPROG BEQ PROG2 04A 7 271---------104A8 18iII0000AStack PointIndex Reg§I,I,Figure 19 Relative Addressing Example~HITACHI167

HD6805S6----------------------------------------------------________ _MemoryTABL FCC t LIt 00B8 4C49PROG LOA XI05F4~IA4CIndex RegB8Stack PointProg Count05F5CC§I,Figure 20 Indexed (No Offset) Addressing ExampleTABL FeB #BF 0089MeloryiII, ,iBFFCB #86 008A 86FCB #OB 008BDBFCB #CF 008CCFIIIIPROG LOA TABL. X 075B075CE689III/lEA008CtAdderI~III_JIACF1Index Regr 03IStack PointIProg Count0750ICCI@II, ,Figure 21Indexed (S-Bit Offset) Addressing Example168 ~HITACHI

-----------------------------------------------------------------HD6805S6MeloryiiiI~IIAdder/ ~~~IIPROG LOA TABL. X 0692~069307I06947EIIITABL FCB #BF 077EBFFCB #86 077F86FCB #OB 0780DBFCB #CF 0781CFlEAI0780IAJIDBJIndex RegJI02IStack PointIIProg Count0695ICCIIFigure 22 Indexed (16-Bit Offset) Addressing ExampleMemoryPORT BEQU0001 BF0000AIndex RegPROG BClR 6. PORT B 058F 10I-------t0590 01Stack Point§@• IiIIProg Count0591CCFigure 23 Bit Set/Clear Addressing Example~HITACHI169

HD6805S6---------------------------------------------------------------PORT C EQU 2 0002 FOAIndex RegStack PointPROG BRCLR 2. PORT C. PROG 2 0574 051-------10575 02 000005761---;1~D~-14--...,Prog Count0594CCCFigure 24 Bit Test and Branch Addressing ExampleiIIIMemoryiPROGTAX~IIIIO~A8AE5Index RegE5Prog Count0588IIiICC§Figure 25 Implied Addressing Example170$ HITACHI

----------------------------------------------------------------HD6805S6Table 2 Register/Memory InstructionsFunction Mnemonic Immediate Direct ExtendedAddressing ModesIndexed Indexed Indexed(No Offset) (8·Bit Offset) (16·Bit Offset)Op # # Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesLoad A from Memory LOA A6 2 2 B6 2 4 C6 3_ 5 F6 1 4 E6 2 5 D6 3 6Load X from Memory LDX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6Store A in Memory STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6Add Memory andCarry to AADC A9 2 2 B9 2 4 C9 35 F9 1 4 E9 2 5 D9 3 6Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6Subtract Memory fromA with BorrowSBC A2 2 2 B2 2 4 C2 35 F2 1 4 E2 2 5 D2 3 6AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 D4 3 6OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6Exclusive OR Memorywith AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory with A(Logical Compare)EOR A8 2 2 B8 2 4 C8 3·CMP A1 2 2 B1 2 4 C1 3CPX A3 2 2 B3 2 4 C3 3BIT A5 2 2 B5 2 4 C5 35 F8 1 4 E8 2 5 D8 3 65 F1 1 4 E1 2 5 D1 3 65 F3 1 4 E3 2 5 D3 3 65 F5 1 4 E5 2 5 D5 3 6Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5Jump to Subroutine JSR - - - ,BD 2 7 CD 3 8 FD 1 7 ED 2 8 DD 3 9Table 3 Read/Modify/Write InstructionsAddressing ModesFunction Mnemonic Implied (A) Implied (X) DirectIndexed(No Offset)Indexed(8·Bit Offset)Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIncrement INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7Negate(2's Complement)NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Test for Negative orZeroTST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7~HITACHI 171

HD6805S6--------------------------------------------------------____ ___Table 4 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch I F Higher BHI 22 2 4Branch I F lower or Same BlS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch IF lower) (BlO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch IF Equal BEQ 27 2 4Branch I F Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch I F Plus BPl 2A 2 4Branch IF Minus BMI 2B 2 4Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch IF Interrupt line is low Bil 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AO 2 8Table 5 Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set BRSET n (n=O ..... 7) - - - 20n 3 10Branch I F Bit n is clear BRClR n (n=O ..... 7) - - - 01+2 0 n 3 10Set Bit n BSET n (n=O ..... 7) 10+2 0 n 2 7 - - -Clear bit n BClR n (n=O ..... 7) 11+2 0 n 2 7 - - -FunctionTable 6 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit ClC 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2172 $ HITACHI

-------------------------------------------------------------HD6805S6Table 7 I nstruction SetMnemonicImpliedDirectADC x xADD x xAND x xASL x xASR x xBCCBCLRBCSBEQBHCCBHCSBHIBHSBIHBILBIT x xBLOBLSBMCBMIBMSBNEBPLBRABRNBRCLRBRSETBSETBSRCLC xCLI xCLR x xCMP x xCOM x xCPX x xDEC x xEOR x xINC x xJMPxJSRxLDA x xLDX x xCondition Code Symbols:H Half Carry (From Bit 3)I Interrupt MaskN Negative (Sign Bit)Z ZeroxxxxxxxxxxxImmediateExtendedRelativexxxxxxxxxxxxxxxxxxxAddressing ModesIndexedIndexed Indexed(No(8 Bits) (16 Bits)Offset)x x xx x xx x xx xx xx x xx xx x xx xx x xx xx x xx xx x xx x xx x xx x xBitSet/ClearC Carry Borrow1\ Test and Set if True, Cleared OtherwiseNot Affected~HITACHIxxCondition CodeBitTest & H I N Z CBranch/\ 1\ 1\ 1\/\ • 1\ 1\ 1\• 1\ 1\ •1\ 1\ 1\• 1\ 1\ 1\• • • • 1\ 1\ • •x• • • • 1\x 1\• •• 00 • • 0 1 •1\ 1\ 1\1\ 1\ 11\ 1\ 1\1\ 1\ 1\ 1\ 1\ 1\ • • 1\ 1\ • • 1\ 1\ •(to be continued)173

HD6805S6---------------------------------------------------------------Table 7 Instruction SetMnemonicLSLLSRNEGNOPORAROLRORRSPRTIRTSSBCSECSEISTASTXSUBSWITAXTSTTXAImpliedxxxxxxxxxxxxxxxImmediateCondition Code Symbols:H Half Carry (From Bit 3)I Interrupt MaskN Negative (Sign Bit)Z ZeroxxxAddressing ModesEx- R ----, IndexedDirect e- (Notended lative Offset)x x xx x xx x xIndexed Indexed(8 Bits) (16 Bits)x x x x xx x xx x xx x x x xx x x x xx x x x xx x x x xx x xBitSet!ClearC Carry/Borrow/\ Test and Set if True, Cleared Otherwise• Not Affected? Load CC Register From StackBitTest &BranchCondition Code/\· . /\H I N Z C/\ /\• • 0/\/\/\ /\• • • • •.. /\/\/\• • • • •? ? ? ? ?• ••••· . /\/\ /\• • • • 1· . /\• 1 •••/\ /\• 1 • • •• • • • •• • • • •174~HITACHI

---------------------------------------------------------------HD6805S6Table 8Opcode MapBit Manipulation Branch Read/Modify!Write Control Register /MemoryTest &BranchSet/ClearRei DIR1 A J X I ,Xl I ,XO IMP IMP IMM I DIR I EXT I ,X2 I )

HD6805U1MCU (Microcomputer Unit)The HD6805Ul is the 8-bit Microcomputer Unit (MCU)which contains a CPU, on·chip clock, ROM, RAM, I/O andtimer. It is designed for the user who needs an economicalmicrocomputer with the proven capabilities of the HD6800·based instruction set.The fonowing are some of the hardware and software high·lights of the MCU.HD6805U1P• HARDWARE FEATURES• 8-Bit Architecture• 96 Bytes of RAM• Memory Mapped I/O• 2056 Bytes of User ROM• Internal 8-Bit Timer with 7-Bit Prescaler• Vectored Interrupts - External and Timer• 24 I/O Ports + 8 Input Port(8 Lines LED Compatible, 7 Bits Comparator Inputs),• On·Chip Clock Circuit• Self·Check Mode• Master Reset• Low Voltage Inhibit• Complete Development System Support by Evaluation Kit• 5 Vdc Single Supply• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM, RAM and I/OCompatible Instruction Set with MC6805P2• BLOCK DIAGRAMTIMER• PIN ARRANGEMENTc,C3c.CsC,C7o(DP·40)HD6805U1CPUControl0,Oso.POrt D •••A 0.,Ret R~SCond.tlonCOd.ReVISIt' CCProgr.mCounter"Hie"" peHPr09,.mCounllf"Low" pelCPuOIt. Port0., CR.g R~c,C,C 2 Pol'1C, Cg: LI,~~C,C,(Top View)0,0,0, Port0, °D. InpUt0, LIn"O.O,IVTH176eHITACHI

--------------------------.,r·----------------------------------HD6805Ul• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee * -0.3- +7.0Input Voltage (EXCEPT TIMER)-0.3- +7.0Vin *Input Voltage (TIMER)-0.3 -+12.0Operating Temperature T opr o -+70Storage Temperature T stll - 55 - +150UnitVVV°c°c* With respect to Vss (SYSTEM GNDI(NOTE IPermanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be underrecommended operating conditions. If these conditions are exceeded, it could affect reliability of lSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vcc·5.25V ± 0.5V, Vss=GNO, Ta"o-+70°C, unless otherwise noted.)Item Symbol Test ConditionRESInput "High" VoltageINTAll OtherVIHInput "High" Voltage TimerTimer ModeSelf·Check ModeRESInput "Low" VoltageINTVILEXTAL(Crystal Mode)All OtherPower DissipationPoLow Voltage RecoverLVRLow Voltage InhibitLVITIMERI nput Leak Current INT IlL V in =0.4V-V eeEXT ALtCrystal Mode)min typ max Unit4.0 - Vee V3.0 - Vee V2.0 - Vee V2.0 - Vee V9.0 - 11.0 V-0.3 - 0.8 V-0.3 - 0.8 V-0.3 - 0.6 V-0.3 - 0.8 V- - 700 mW- - 4.75 V- 4.0 - V-20 - 20 IJ.A-50 - 50 IJ.A-1200 - 0 IJ.A• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GNO, Ta=O - +10°C, unless otherwise noted.)Item Symbol Test ConditionClock FrequencyfelCycle TimeteycOscillation Frequency (External Resistor Mode) f EXT Rep=15.0kSH1%TNT Pulse WidthRES Pulse WidthTIMER Pulse WidthOscillation Start·up Time (Crystal Mode)t lWLtRWLt TWLtoseCL=22pF±20%,Rs=60n max.Delay Time Reset tRHL External Cap. = 2.2 IJ.FInput CapacitanceiIXTALAll OtherCinVin=OVmin typ max Unit0.4 - 4.0 MHz1.0 - 10 IJ.s- 3.4 - MHzt eye+250- - nst cvc +250-I - nst cvc +250-i - ns- - 100 ms100~ms- - 35 pF- - 10 pF~HITACHI177

HD6805U1---------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ± 0.5V, Vss = GNO, Ta = 0"" +70°C, unless otherwise noted.)ItemOutput "High" Voltage·Output "Low" VoltageInput "High" VoltageInput "Low" VoltageInput Leak CurrentInput "High" VoltageInput "Low" VoltageThreshold Voltage..* Port 0 as digital Input** Port 0 as analog inputPort APort ePort CPort A and CPort ePort A, e, C,and 0*Port APort e, C,and 0Port 0**(Do"" 0 6 )Port 0**(OJl .... 0 6 )Port 0**(0,)SymbolVOHVOLVIHVILIlLVIHVILVTHTest Condition min typ maxIOH = -10pA 3.5 - -IOH = -l00pA 2.4 - -IOH = -200 pA 2.4 - -IOH = -1 mA 1.5 - -IOH = -100pA 2.4 - -IOL = 1.6mA - - O.~IOL = 3.2 mA - - 0.4IOL = 10mA - - 1.02.0 - Vee-0.3 - 0.8Vin = 0.8V -500 - -Vin = 2V -300 - -Vin = 0.4V"" Vee - 20 - 20- VTH+0.2 -- VTwO.2 -0 - 0.8xVceUnitVVVVVVVVVVpApApAVVVTTL Equiv. (Port e)VeeTTL Equiv. (Port A and C)VeeTest PointIi = 3.2 rnA1.2knTest PointIi = 1.6 rnA2.4kHVi40pF 12 kn 30 pF 24 kn(NOTE)1. Load capacitance includes the floating capacitance of the probe and the jig etc.2. All diodes are 1520748 or equivalent.• SIGNAL DESCRIPTIONThe input and output signals for the MCV, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee and VssPower is supplied to the MCV using these two pins. Veeis +5 .25V ±O.5V. V 55 is the ground connection.• INTThis pin provides the capability for asynchronously applyingan external interrupt to the MCV. Refer to INTERRUPTS foradditional information.• XTAL and EXTALThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum), a resistor or an externalsignal can be connected to these pins to provide a system clockwith various stability/cost tradeoffs. Refer to INTERNAL OS-Figure 1 Bus Timing Test Loads178 ~HITACHICILLATOR OPTIONS for recommendations about these inputs.• TIMERThis pin allows an external input to be used to decrementthe internal timer circuitry. Refer to TIMER for additionalinformation about the timer circuitry.• RESThis pin allows resetting of the MCV at times other thanthe automatic resetting capability already in the MCV. Referto RESETS for additional information.• NUMThis pin is not for user application and should be connectedto VSS.

---------------------------------------------------------------HD6805U1• Input/Output Lines (Ao ..., A, • Bo ..., B,. Co ..., C,)These 24 lines are arranged into three 8·bit ports (A, Bande). All lines are programmable as either inputs or outputs undersoftware control of the Data Direction Register (DDR). Refer toINPUT/OUTPUT for additional information.• Input Lines (Do ..., 0,)These are 8·bit input lines, which has two functions. Firstly,these are TTL compatible inputs, in location $003. The otherfunction is 7 bits comparator, in location $007. Refer to INPUTfor more detail.• MEMORYThe MeU memory is configured as shown in Figure 2. Duringthe processing of an interrupt, the contents of the CPU regi·sters are pushed onto the stack in the order shown in Figure 3.Since the stack pointer decrements during pushes, the low orderbyte (PCL) of the program counter is stacked fust; then thehigh order four bits (PCH) are stacked. This ensures that theprogram counter is loaded correctly as the stack pointer in·crements when it pulls data from the stack. A subroutine callwill cause only the program counter (pCH, peL) contents tobe pushed onto the stack.Caution: - Self Test ROM Address AreaSelf test ROM locations can not be used for a user program.If the user's program is in this location, it will be removed whenmanufacturing mask for production.000127128255256110 Ports TimerRAM (128 Bytes)ROM(128 Bytes)$0 00$07K$OF F$1 000123456Port APort BPort CPort 0 (digital)Port A DDRPort BOORPort C DDR$000$001$002$003"$004'$005'$OOS'Not Used7Port 0 (analog)$007"20472048$7F F$8 0089Timer Data Reg.Timer CTRL Reg.$008$0090$OOANot Used 122 Bytes)ROM(1920 Bytes)112 ~RAM (96 Bytes)Stt Ck$OIF$020$07F39673968408740884095Self·TestInterrupt Vectors$F7 F$F 80$FF 7$FF 8$FF• Write only registers." Read only registerFigure 2 MCU Memory ConfigurationPush6 5 4Pull° n-4 Condition1 111 Code Registern+1n-3 Accumulator n+2n-2 Index Register n+3n-1 1 1 111 PCH" n+4PCl" n+5• For subroutine calls, only PCH and PCl are stacked.Figure 3 Interrupt Stacking Order11L-_____ A ____...J 1 Accumulator'-_____ x_" ___........ 1 Index Register'-________ P_C ______--II Program Counter11 5 4 °LoI0...lI_o .....I-...II_1...11 ___ sP __.... 1 Stack Pointerl_o .... l_o .... l_o ....°°°Condition Code RegisterCarry/BorrowZeroNegativeInterrupt MaskFigure 4 Programming ModelHalf Carry~HITACHI179

HD6805Ul-----------------------------------------------------------------• REGISTERSThe CPU has five registers available to the programmer.They are shown in Figure 4 and are explained in the followingparagraphs.• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datarna nipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddr~ssing mode. It contains an 8-bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for limited calculations and datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is a 12-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 12-bit register that contains the addressof the next free location on the stack. Initially, the stack pointeris set to location $07F and is decremented as data is beingpushed onto the stack and incremented as data is being pulledfrom the stack. The six most significant bits of the stack pointerare permanently set to 0000011. During an MCU reset or thereset stack pointer (RSP) instruction, the stack pointer is setto location $07F. Subroutines and interrupts may be nesteddown to location $061 which allows the programmer to use upto 15 levels of subroutine calls.• Condition Code Register (CC)The condition code register is a 5-bit register in which eachbit is used to indicate or nag the r~sults of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained in the followingparagraphs.Half Carry (H)Used during arithmetic operations (ADD and ADC) toindicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask the timer and external interrupt (iNT).If an interrupt occurs while this bit is set it is latched and will beprocessed as soon as the interrupt bit is reset.Negatiye (N)Used to indicate that the result of the last arithmetic, logicalor data manipulation was negative (bit 7 in result equal to alogical one).Zero (Z)Used to indicate that the result of the last arithmetic, logicalor data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the arithmeticlogic unit (ALU) occurred during the last arithmetic operation.This bit is also affected during bit test and branch instructions,shifts, and rotates.• TIMERThe MCU timer circuitry is shown in Figure 5. The 8-bitcounter, the. Timer Data Register (TOR), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the timer reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register (TCR) isset. The CPU responds to this interrupt by saving the presentCPU state on the stack, fetching the timer interrupt vector fromlocations $FF8 and $FF9 and executing the interrupt routine.The timer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the TCR. The interrupt bit (I bit) in theCondition Code Register also prevents a time interrupt frombeing processed.The clock input to the timer can be from an external sourceapplied to the TIMER input pin or it can be the internal 1/>2signal. When the 1/>2 signal is used as the source, it can be gatedby an input applied to the TIMER input pin allowing the userto easily perform pUlse-width measurements. The TIMER inputpin must be tied to Vee, for ungated 1/>2 clock input to thetimer prescaier. The source of the clock input is one of theoptions that has to be specified before manufacture of the,(Internal)TIR;TIM;Timer Interrupt RequestTimer Interrupt MaskTimerInputPin,.-----,• IIIII1. I _____.1IManufacturingMask OptionsWriteRead Write ReadFigure 5 Timer Block Diagram180 ~HITACHI

---------------------------------------------------------------HD6805UlMCU. A prescaler option can be applied to the clock input thatextends the timing interval up to a maximum of 128 countsbefore decrementing the counter (TOR). The timer continuesto count past zero, falling through to $FF from zero and thencontinuing the count. Thus, the counter (TOR) can be read atany time by reading the TOR. This allows a program to determinethe length of time since a timer interrupt has occurredand not disturb the counting process.The TDR is 8-bit Read/Write Register in location $008.At power-up or reset, the TOR and the prescaler are initializedwith all logical ones.The Timer Interrupt Request bit (bit 7 of the TCR) is setby hardware when timer count reaches zero, and is cleared byprogram or by hardware reset. The bit 6 of the TCR is writableby program. Both of those bits can be read by CPU.(NOTE) If the MCU Timer is not used, the TIMER input pinmust be grounded.• SELF CHECKThe self-check capability of the MCU provides an internalcheck to determine if the part is functional. Connect the MCUas shown in Figure 6 and monitor the output of port C bit 3 foran oscillation of approximately 3Hz.• RESETSThe MCU can be reset three ways; by initial power-up, bythe external reset input (RES) and by an optional internallow voltage inhibit circuit, see Figure 7. All the I/O port areinitialized to input mode (OORs are cleared) during reset.During power-up, a minimum of 100 milliseconds is neededbefore allowing the RES input to go "High".This time allows the internal crystal oscillator to stabilize.Connecting a capacitor to the RES input, as shown in Figure 8,typically provides su fficien t delay.v-L.T 2 . 21lF2.. INT2 RESCXTALEXTALA,A. 39As4038A4rE-A, 36A, 35A, 34An~+9VHD6805U1 *8 TIMER (Resistor option)rB,~NUM B. 31cc B, 30B. 291~,!1 ~ 9 Co B-,~~3pn ~b 10C. B, Z713fo ~ U "C, B, 261~!P. ~ 10.12 C, Bn 25vv\0'10kn 13AC.lokn v 14~AACs10kn v 15c.J\&vl°Ak~ 16 C,vv vVcc=Pin4Vss = Pin 1Figure 6 Self Check Connections• R fer to F, gure 9about crystal optionRES Pin --------4'InternalReset---------~Figure 7 Power Up and RES Timing~HITACHI181

HD6805U1---------------------------------------------------------------Part ofHD6805U1MCU'2• INTERNAL OSCILLATOR OPTIONSThe internal oscillator circuit is designed to require a mini·mum of external components. A crystal, a resistor, a jumperwire, or an external signal may be used to generate a systemclock with various stability/cost tradeoff. A manufacturingmask option is required to select either the crystal oscillator orthe RC oscillator circuit. The different connection methods areshown in Figure 9. Crystal specifications are given in Figure 10.A resistor selection graph is given in Figure 11.Figure 8 Power Up Reset Delay Circuit6 XTAL4~a~Z c:J 5 EXTAL HD6805U1MCU22PF±20%T6 XTALHD6805U15 EXTAL MCUApproximately 25% AccuracyExternal: JumperVee6 XTAL6 XTALExternalClockInput5 EXTALHD6805U1MCURNoConnection5 EXTALHD6805U1MCUExternal ClockCRYSTAL OPTIONSApproximately 15% AccuracyExternal ResistorRESISTOR OPTIONSFigure 9 Internal Oscillator OptionsC ,XTAL~~EXTAL6 ~~ 5AT - Cut Parallel Resonance CrystalC Il= 7 pF max.f = 4 MHzRs = 60n max.Figure 10 Crystal Parameters54~~ 3~~~u:,4.I -'-f\ Vee = 5.25VTA = 25°C -\\.\"'-'" ~ '-..~ ~1o 5 10 15 20 25 30 35 40 45 50Resistance (kH)Figure 11 Typical Resistor Selection Graph182$ HITACHI

-----------------------------------------------------------------HD6805U11-17F -SPo -DDR'sCLR I NT LogicFF - Timer7F --+ Prescaler7F --+ TCRyStackPC,X,A,CCYTIMERLoad PC FromReset :$FFE, $FFFLoad PC FromSWI :$FFC, $FFDiNT:$FFA, $FFBTIMER :$FF8,$FF9FetchInstructionYSWIExecuteInstructionFigure 12 Interrupt Processing FlowchartDataDirectionRegisterBitOutputData BitOutputStateInput toMCUFigure 13 Typical Port I/O Circuitry1000 03·StatePin~HITACHI183

HD6805U1---------------------------------------------------------------• INTERRUPTSThe CPU can be interrupted three different ways: throughthe external interrupt (INT) input pin, the internal timer interruptrequest. and a software interrupt instruction (SWI). Whenany interrupt occurs, processing is suspended, the present CPUstate is pushed onto the stack, the interrupt bit (I) in the ConditionCode Register is set, the address of the interrupt routine isobtained from the appropriate interrupt vector address, and theinterrupt routine is executed. The interrupt service routinesnormally end with a return from interrupt (RTI) instructionwhich allows the CPU to resume processing of the programprior to the interrupt. Table 1 provides a listing of the interrupts,their priority, and the vector address that contain thestarting address of the appropriate interrupt routine.A flowchart of the interrupt processing sequence is givenin Fig. 12.Table 1 Interrupt PrioritiesInterrupt Priority Vector AddressRES 1 $FFE and $FFFSWI 2 $FFC and $FFDTNT 3 $FFA and $FFBTIMER 4 $FF8 and $FF9• INPUT/OUTPUTThere are 24 input/output pins. All pins are programmableas either inputs or outputs under software control of the correspondingData Direction Register (DDR). When programmedas outputs, the latched output data is readable as input data,regardless of the logic levels at the output pin due to outputloading (see Fig. 13). When Port B is programmed for outputs,it is capable of sinking lOrnA on each pin (VOL = IV max).All input/output lines are TTL compatible as both inputs andoutputs. Port A is CMOS compatible as outputs, and Port BandC lines are CMOS compatible as inputs. Figure 14 provides someexamples of port connections.• INPUTPort D can be used as either 8 TTL compatible inputs or 1threshold input and 7 analog inputs pins. Fig. 15 (a) shows theconstruction of port D. The Port D register at location $003stores TTL compatible inputs, and those in location $007 storethe result of comparison Do to D6 inputs with D7 thresholdinput. Port D has not only the conventional function as inputsbut also voltage-comparison function. Applying the latter, caneasily check that 7 analog input electric potential max. exceedsthe limit with the construction shown in Fig. 15 (b). Also, usingone output pin of MCU, after external capacity is dischargedat the preset state, charge the CR circuit of long enough timeconstant, apply the charging curve to the D7 pin. The constructiondescribed above is shown in Fig. 15 (c). The comparedresult of Do to D6 is regularly monitored, which gives theanalog input electric potential applied to Do to D6 pins frominverted time. This method enables 7 inputs to be convertedfrom analog to digital. Furthermore, combination of two functionsgives 3 level voltages from Do to D6. Fig. 15 (d) providesthe example when VTH is set to 3.SV.• BIT MANIPULATIONThe MCU has the ability to set or clear any single randomaccess memory or input/output bit (except the data directionregisters) with a single instruction (BSET, BCLR). Any bit inthe page zero read only memory can be tested, using the BRSETand BRCLR instructions, and the program branches as a resultof its state. This capability to work with any bit in RAM, ROMor I/O allows the user to have individual flags in RAM or tohandle single I/O bits as control lines. The example in Figure 16illustrates the usefulness of the bit manipulation and testPort APort B·B7Port A Programmed as output(sl.driving CMOS and TTL Load directly.(a)Port B Programmed as output(s),driving Darlington base directly.(b)+vPort B10 -mA maxB7RPortC+VRCo1----........ CMOS Inverter· C7Port B Programmed as output(S),driving LED(s) directly.(e)Port C Programmed as output(s), driving CMOS loads, usingexternal pull-up(d)Figure 14 Typical Port Connections184 ~HITACHI

-----------------------------------------------------------------HD6805U1instructions. Assume that bit 0 of port A is connected to a zerocrossing detector circuit and that bit 1 of port A is connected tothe trigger of a TRIAC which power the controlled hardware.This program, which uses only seven ROM locations, providesturn-on of the TRIAC within 14 microseconds of the zerocrossing. The timer could also be incorporated to provide turnonat some later time which would permit pulse·width modulationof the controlled power.$003 ReadInternal Bus(BitO - BitS)+Internal Bus(Bit 7)$003 Read(a) The logic configuration of Port DInput Port (D7)r---D,Reference LevelPortCCoD,Analog Input SD,PortD)PortDD.I--=----Analog Input 6DoAnalog Input 0Do1--=--- Analog Input 0(b) Seven analog inputs and a reference level input of Port D(c) Application to AID convertorD,VTH (= 3.5V)PortDD,D.~3 Levels Input S3 Levels Input 0InputVoltageOV -O.8V2.0V - 3.3V3.7V - Vee($003) ($007)0 01 01 1(d) Application to 3 levels inputFigure 15 Configuration and Application of Port 0$ HITACHI 185

HD6805U1-----------------------------------------------------------------SELF 1 BRClR 0, · PORT A, SELF 1BSET 1, PORT ABClR 1, PORT AFigure 16 Bit Manipulation · Example• ADDRESSING MODESThe CPU has ten addressing modes available for use by theprogrammer. They are explained and .illustrated briefly in thefollowing paragraphs.• ImmediateRefer to Figure 17. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure ] 8. In direct addressing, the address of theoperand is contained in the second byte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage of thisefficient memory addressing mode.• ExtendedRefer to Figure 19. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instructionsare three bytes long.• RelativeRefer to Figure 20. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA=(pC)+2+Rel. Rei is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken Rel=O, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 of the present instruction. Theseinstructions are two bytes long.• Indexed (No Offset)Refer to Figure 21. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and their EA is the contents of the index register.• Indexed (S-bit Offset)Refer to Figure 22. The EA is calculated by adding thecontents of the byte following the opcode to the contents ofthe index register. In this mode, 511 low memory locations areaccessable. These instructions occupy two bytes.• Indexed (16-bit Offset)Refer to Figure 23. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode are threebytes long.• Bit Set/ClearRefer to Figure 24. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 25. This mode of addressing applies toinstructions which can test any bit in the first 256 locations($OO-$FF) and branch to any location relative to the PC. Thebyte to be tested is addressed by the byte following the opcode.The individual bit within that byte to be tested is addressed bythe lower three bits of the opcode. The third byte is the relativeaddress to be added to the program counter if the branch conditionis met. These instructions are three bytes long. The value ofthe bit tested is written to the carry bit in the condition coderegister.• ImpliedRefer to Figure 26. The implied mode of addressing has noEA. All the information necessary to execute an instruction iscontained in the opcode. Direct operations on the accumulatorand the index register are included in this mode of addressing.In addition, control instructions such as SWI, RTI belong to thisgroup. All implied addressing instructions are one byte long.• INSTRUCTION SETThe MCV has a set of S9 basic instructions. They can bedivided into five different types: register/memory, read/modify/write, branch, bit manipulation, and control. The followingparagraphs briefly explain each type. All the instructions withina given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operand iseither the accumulator or the index register. The other operandis obtained from memory using one of the addressing modes.The jump unconditional (JMP) and jump to subroutine (JSR)instructions have no register operand. Refer to Table 2.• Read/Modity!Write InstructionsThese instructions read a memory location or a register,modify or test its contents, and write the modified value backto memory or to the register. The test for negative or zero(TST) instruction is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table3.• Branch InstructionsThe branch instructions cause a branch from the programwhen it certain condition is met. Refer to Table 4.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 2S6 bytesof the memory. One group either sets or clears. The other groupperforms the bit test and branch operations. Refer to Table 5.• Control InstructionsThe control instructions control the Mev operations duringprogram execution. Refer to Table 6.• Alphabetical listingThe complete instruction set is given in alphabetical order inTable 7.• Opcode MapTable 8 is an opcode map for the instructions used on theMCV.186 $ HITACHI

-----------------------------------------------------------------HD6805UlMemoryaIIPROG LOA #$F8 058E A6t-------i058F F8IIArIndexStack PointProg Count05COCCea'l.. ____...I~IIIIItFigure 17 Immediate Addressing ExampleJEAMemoryI 0048,iI I, tI AdderI ,/.'"CAT FeB 32 0048 20 ootoPROG LOA CAT 0520 86052E 48I~, I, IIII :•IFigure 18 Direct Addressing ExampleIAI1 20Index RegIStack Point1I I IIProg Count052FICCI~HITACHI187

HD6805U1---------------------------------------------------------------Memory,I§0000PROG LOA CATCAT FCB 64=~1-------'IIII06E5 40t-------1A40Index RegStack PointProg Count040CCCFigure 19 Extended Addressing Example,IMemory~IIPROG BEQ PROG2 04A 7 27.-------~04A8 180000AStack PointIndex Reg~II, ,Figure 20 Relative Addressing Example188 $ HITACHI

---------------------------------------------------------------HD6805U1MemoryTABL FCC t Lit 00B8 4C49A4CIndex Reg88PROG LOA XI05F4~§IStack PointProg Count05F5CCFigure 21Indexed (No Offset) Addressing ExampleTABL FCB #SF 0089FCB #86 008AFCB #OB 0088FCB #CF 008CPROG LOA TABL. X 075B075CiIIiIiJMemorySF86DBCFE689iiiiIIlEAI 008C 1f/Adder[~I,.I-,A_IStack PointICFIndex RegII 03IIProg Count0750ICC§J,Figure 22 Indexed (S-Bit Offset) Addressing Example~HITACHI189

HD6805Ul-----------------------------------------------------------------MemoryiI§ADBPROGLOATABL.x::EBIndex Reg02Stack Point06M ~ /-------'Prog Count0695 ...IICCTABL FCB #BF 077E BFFCB #86 077F 86FCB #OB 07BO ~--~O~B--_t-----------------'FCB #CF 0781 CFFigure 23 Indexed (16·Bit Offset) Addressing ExampleMemoryPORT BEQU0001 BFI0000AIndex Reg100590 01§IIStack PointProg Count0591CCIII,Figure 24 Bit Set/Clear Addressing Example190~HITACHI

HD6805U 1PORT C eau 2FOAI -----~Index RegStack POintPROG BRCLR 2. PORT C. PROG 205 Prog Count02 0000 059410 CC§IIFigure 25 B' It T est and Branch Add ressmg . ExampleEAMemoryIII§APROGTAXIIO~A~IIProg Count________ ~05~BB~ ______ JICCII~IIIIII-!------.:Figure 26 I mplied Addressing E xample$ HITACHI191

HD6805U1-----------------------------------------------------------------Table 2 Register/Memory InstructionsFunction Mnemonic Immediate DirectExtendedAddressing ModesIndexed Indexed Indexed(No Offset) (8-Bit Offset) (16-Bit Offset)Op # # Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles 'Code Bytes Cycles Code Bytes CyclesLoad A from Memory LOA A6 2 2 B6 2 4 C6 3_ 5 F6 1 4 E6 2 5 06 3 6Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6Store A in Memory STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7-- Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6Add Memory and~:!toAAOC A9 2 2 89 2 4 C9 35 F9 1 4 E9 2 5 09 3 6Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6Subtract Memory fromA with BorrowSBC A2 2 2 82 2 4 C2 35 F2 1 4 E2 2 5 02 3 6AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6Exclusive OR Memorywith AArith",etic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory with A(Logical Compare)EOR A8 2 2 B8 2 4 C8 3CMP Al 2 2 Bl 2 4 Cl 3CPX A3 2 2 B3 2 4 C3 3BIT A5 2 2 B5 2 4 C5 35 F8 1 4 E8 2 5 08 3 65 Fl 1 4 El 2 5 01 3 65 F3 1 4 E3 2 5 03 3 65 F5 1 4 E5 2 5 05 3 6Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5Jump to Subroutine JSR - - - BD 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9Table 3 Read/ModifylWrite InstructionsAddressing ModesFunction Mnemonic Implied (A) Implied (X) DirectIndexed(No Offset)Indexed(8-Bit Offset)Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIncrement INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7Negate(2'5 Complement)NEG 40 1 4I50 1 4 30 2 6 70 1 6 60 2 7Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Test for Negative orZeroTST 40 i 1 4 50 1 4 3D 2 6 70 1 6 60 2 7192 ~HITACHI

---------------------------------------------------------------HD6805U1Table 4 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch I F Higher BHI 22 2 4Branch I F lower or Same BlS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch IF lower) (BlO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch I F Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch I F Plus BPl 2A 2 4Branch I F Minus BMI 2B 2 4Branch I F Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch IF Interrupt Line is low Bil 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AD 2 8Table 5 Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set BRSET n (n=O ..... 7) - - - 2 n 0 3 10Branch IF Bit n is clear BRClR n (n=O ..... 7) - - - 01+2-n 3 10Set Bit n BSET n (n=O ..... 7) 10+2·n 2 7 - - -Clear bit n BClR n (n=O ..... 7) 11+2·n 2 7 - - -FunctionTable 6 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit CL.C 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2~HITACHI 193

HD6805U1----------------------------------------------------------__ ___Table 7 Instruction SetAddressing ModesCondition CodeMnemonicIndexed Bit BitImme- Ex- Re-Indexed IndexedImpliedDirect(Nodiatetended lative(8 Bits) (16 Bits)Setl Test & H I N Z COffset) Clear BranchADC x x x x x x /\ /\ /\ /\ADD x x x x x x /\ • /\ /\ /\AND x x x x x x /\ /\ •ASl x x x x /\ /\ /\ASR x x x x /\ /\ /\BCC x BClR x BCS x BEQ x• • • • •BHCC x• • • • •BHCS x• • • • •BHI x• • • • •BHS x• • • • •BIH x • • • • •Bil x• • • • •BIT x x x x x x• • /\ /\ •BlO x• • • • •BlS x• • • • •BMC x• • • • •BMI x----------BMS x• • • • •BNE x• • • • •BPl x• • • • •BRA x• • • • •BRN x• • • ~ •BRClR x• • • • /\BRSET x /\BSET x BSR x •ClC x • 0CLI x 0 • • ClR x x x x 0 1 •CMP x x x x x x /\ /\ /\COM x x x x /\ /\ 1CPX x x x x x x /\ /\ /\DEC x x x x • • /\ /\ •EOR x x x x x x /\ /\ INC x x x x /\ /\ JMP x x x x x• • • • •JSR x x x x x • • LOA x x x x x x /\ /\ lOX x x x x x x• • /\ /\ •Condition Code Symbols:H Half Carry (From Bit 3) C Carry BorrowI Interrupt Mask /\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero194 ~HITACHI(to be continued)

-----------------------------------------------------------------HD6805U1MnemonicImpliedAddressing ModesImme- Ex- Re-Directdiatetended lativeTable 7 Instruction SetCondition CodeIndexedBit Bit(NoIndexed Indexed(8 Bits) (16 Bits)Set/ Test & H I N Z COffset) Clear BranchLSL x x x x 1\ 1\ 1\LSR x x x x 0 1\ 1\NEG x x x x 1\ 1\ 1\NOP x • • ORA x x x x x x 1\ 1\ •ROL x x x x 1\ 1\ 1\ROR x x x x 1\ 1\ 1\RSP x• • • • •RTI x ? ? ? ? ?RTS x• • • • •SBC x x x x x x 1\ 1\ 1\SEC x • 1SEI x 1 • • STA x x x x x 1\ 1\ STX x x x x x 1\ 1\ •SUB x x x x x x • 1\ 1\ 1\SWI x 1 TAX x • • TST x x x x 1\ 1\ TXA x • • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry!BorrowI I nterrupt Mask 1\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack~HITACHI 195

HD6805U1----------------------~--------------------________________ ___Table 8Opcode MapBit Manipulation Branch Read/Modify /Write Control Register /MemoryTest &BranchSet/ClearRei OIRI A I X I .X1 I .XO IMP IMP IMM I OIR I EXT I .x2 I .x10 1 2 3 I 4 I 5 I 6 I 7 8 9 A I B I C I 0 I E0 BRSETO BSETO BRA NEG RTI- - SUB1 BRClRO BClRO BRN - RTS· - CMP2 BRSET1 BSET1 BHI - - - SBC3 BRClR1 BClR1 BlS COM SWI· - CPX4 BRSET2 BSET2 BCC lSA - - AND5 BAClA2 BClA2 BCS - - - BIT6 BASET3 BSET3 BNE ROA - - lOA7 BAClA3 BClA3 BEQ ASR - TAX - I STA(+1)8 BASET4 BSET4 BHCC lSl/ASl - ClC EOA9 BAClA4 BClA4 BHCS AOl - SEC AOC- A BASET5 BSET5 BPl DEC - CLI OAAB BAClA5 BClA5 BMI - - SEI ADD----=-1---C BASET6 BSET6 BMC INC - ASP - IJMP(-1)0 BAClA6 BClA6 BMS TST - NOP BSA·I JSA(-3)E BASET7 BSET7 Bil - - - lOXF BAClA7 BClA7 BIH ClA - TXA - I STX(+1)3/10 2/7 2/4 2/6 I 1/4 I 1/4 I 2/7 I 1/6 1/- 1/2 2/2 I 2/4 I 3/5 I 3/6 J 2/5(NOTE) 1. Undefined opcodes are marked with "-".2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).Mnemonics followed by a "." require a different number of cycles as follows:ATI 9ATS 6SWI 113. (BSA 8indicate that the number in parenthesis must be added to the cycle count for that instruction.l·xOI FJ 1/4+- HIGH0123456789ABC0EFloW196 $ HITACHI

HD6805V1-------------­MCU (Microcomputer Unit)The H06805Vl is the 8-bit Microcomputer Unit (MCU)which contains a CPU. on-chip clock. ROM. RAM. I/O andtimer. It is designed for the user who needs an economicalmicrocomputer with the proven capabilities of the H06800-based instruction set.The foUowing are some of the hardware and software highlightsof the MCU.HD6805V1P• HARDWARE FEATURES• 8-Bit Architecture• 96 Bytes of RAM• Memory Mapped I/O• 3848 Bytes of User ROM• Internal 8-Bit Timer with 7·Bit Prescaler• Vectored Interrupts - External and Timer• 24 I/O Ports + 8 Input Port(8 Lines LED Compatible; 7 Bits Comparator Inputs)• On-Ghip Clock Circuit• Self·Check Mode.• Master Reset• Low Voltage Inhibit• Complete Development System Support by Evaluation Kit• 5 Vdc Single Supply• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Appl~ to ROM, RAM and I/O• Compatible Instruction Set with MC6805P2• BLOCK DIAGRAM• PIN ARRANGEMENTRESINfXTALc.c,c,C.C.C.C,0(DP·40)HD6805VlA,A.A.A.A,A,A.AoB,B.B,B,B,BoA.A.Port AIA A.110 A.Lines A.A.A,P~1RegDataOirReg.IndexRegisterConditionCode~ RegisterStackPointerProgramCounter.. High PCHCPuB.B.8s PortB. B8_ I/O8. LinesB.B,C.c.c~ PortC. Cc. 1/0C. LinesC.C,o.D.d.(Top View)0,0,g;01 PortD. 0o. Inputo. LinesD.O,/VTH$ HITACHI197

HD6805V11---------------------------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vcc * -0.3 - +7.0Input Voltage (EXCEPT TIMER)-0.3- +7.0Yin *Input Voltage (TIMER)-0.3-+12.0-_ ..Operating Temperature I T opro -+70Storage Temperature T stg - 55- +150UnitVVVDCDC• With respect to Vss (SYSTEM GNOI(NOTE)Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be underrecommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (VCC·S.25V ± O.SV, VSS·GND, Ta=G-+70DC, unless otherwise noted.)Input "High" VoltageInput "High" Voltage TimerInput "Low" VoltagePower DissipationLow Voltage RecoverLow Voltage InhibitItem Symbol Test ConditionRESINTAll OtherTimer ModeSelf-Check ModeRESINTEXT AL(Crystal Mode)All OtherTIMERVIHVILPoLVRInput Leak Current INT IlL Vin=0.4V-V eeEXTAL(Crystal Mode)LVImin typ max Unit4.0 - Vee V3.0 - Vee V2.0 - Vee V2.0 - Vee V9.0 - 11.0 V-0.3 - 0.8 V-0.3 - 0.8 V-0.3 - 0.6 V-0.3 - 0.8 V- - 700 mW- - 4.75 V- 4.0 - V-20 - 20 IlA-50 - 50 IlA-1200 - 0 IlA• AC CHARACTERISTICS (Vcc=5.25V ± O.SV, Vss=GND, Ta=O - +70°C, unless otherwise noted.)Item Symbol Test ConditionClock FrequencyfCICycle TimetCYCOscillation Frequency (External Resistor Mode) fEXT Rcp=15.0kU±1%INT Pulse WidthRES Pu Ise WidthTIMER Pulse WidthOscillation Start-up Time (Crystal Mode)-tlWLtRWLtTWLtoseCL = 22pF±20%.Rs=60n max.Delay Time Reset tRHL External Cap. = 2.21lFInput Capacitance I XTALI All OtherC inVin=OVmin typ max Unit0.4 - 4.0 MHz1.0 - 10 IlS- 3.4 - MHzt Cyc +250- - nstcsc +2 0- I - nst Cyc+250- - ns- - 100 ms100 - - ms- - 35 pF- - 10 pF198 _HITACHI

---------------------------------------------------------------HD6805V1• PORT ELECTRICAL CHARACTERISTICS (Vee = S 2SV ± O.SV Vss = GNO, Ta = 0'" +70°C, unless otherwise noted.)ItemOutput "High" VoltageOutput "Low" VoltageInput "High" VoltageInput "Low" VoltageInput Leak CurrentInput "High" VoltageInput "Low" VoltageThreshold Voltage..* Port 0 as dIgItal Input** Port 0 as analog inputPort APort BPort CPort A and C------Port BPort A, B, C,and 0*Port APort B; C,and 0Port 0**(Do'" 0 6 )Port 0**(Do'" 0 6 )Port 0**(0,)SymbolVOHVOLV'HV'LI'LV'HV'LVTHTest Condition min typ maxIOH = -lOIlA 3.S - -IOH = -lOOIlA 2.4 - -IOH = -200 IlA 2.4 - -IOH = -1 rnA loS - -IOH = -lOOIlA 2.4 - -r------!2 L = 1.6 rnA - - 0.4r_~Qb_:}.2 rnA - - 0.4IOL = lOrnA - - 1.02.0 - Vee-0.3 - 0.8Yin = 0.8V -SOO - -f----Yin = 2V -300 - -Yin = 0.4V '" Vee - 20 - 20- VTH+O.2 -- VTH-0.2 -0 - 0.8xVeeUnitVVVVVVVVVVIlAIlAIlAVVVTTL Equiv. (Port B)TTL Equiv. (port A and C)VeeTest PointIi = 3.2 mA1.2k!1TesT PointIi = 1.6 mA2.4kHVi40pF 12 kH 30 pF 24 kHVi(NOTE)1. Load capacitance includes the floating capacitance of tt.a probe and the jig etc.2. All diodes are lS20746 or equivalent.Figure 1 Bus Timing Test Loads• SIGNAL DESCRIPTIONThe input and output signals for the MCV, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee and VssPower is supplied to the MCU using these two pins. Veeis +S.2SV ±O.5V. Vss is the ground connection.• INTThis pin provides the capability for asynchronously applyingan external interrupt to the MCV. Refer to INTERRUPTS foradditional information.• XT Al and EXT AlThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum), a resistor or an externalsignal can be connected to these pins to provide a system clockwith various stability/cost tradeoffs. Refer to INTERNAL OS­CILLATOR OPTIONS for recommendations about these inputs.• TIMERThis pin allows an external input to be used to decrementthe internal timer circuitry. Refer to TIMER for additionalinformation about the timer circuitry.• RESThis pin allows resetting of the MCU at times other thanthe automatic resetting capability already in the MCV. Referto RESETS for additional information.• NUMThis pin is not for user application and should be connectedto Vss.~"UTACHI 199

HD6805V11----------------------------------------------------------____ _• Input/Output Lines (Ao ,.., A,. Bo ,.., B,. Co ,.., C,)These 24 lines are arranged into three 8-bit ports (A, BandC). All lines are programmable as either inputs or outputs undersoftware con trol of the Data Direction Register (DDR). Refer toINPUT/OUTPUT for additional information.• Input lines (Do"" 0,)These are 8-bit input lines, which has two functions. Firstly,these are TTL compatible inputs, in location $003. The otherfunction is 7 bits comparator in location $007. Refer to INPUTfor more detail.000I/O Ports TimerRAM (128 Bytes)1271--__________ -i12B39673968ROM(3840 Bytes)o$000Self-test40873140883RAM (96 Bytes)InterruptVectorsStc~r(8 Bytes)12 ~• Write only registers4095 $FFF •• Read only registerFigure 2 MCU Memory Configuration6 5 4 2n-4 1 1 1\ConditionCode RegIsteroPull01234567890• MEMORYThe MCU memory is configured as shown in Figure 2. Duringthe processing of an interrupt, the contents of the CPU registersare pushed onto the stack in the order shown in Figure 3.Since the stack pointer decrements during pushes, the low orderbyte (PCL) of the program counter is stacked rust; then thehigh order four bits (PCH) are stacked. This ensures that theprogram counter is loaded correctly as the stack pointer incrementswhen it pulls data from the stack. A subroutine callwill cause only the program counter (PCH. PCL) contents tobe pushed onto the stack.Cau tion: - Self Test ROM Address AreaSelf test ROM locations can not be used for a user program.If the user's program is in this location, it will be removed whenmanufacturing mask for production.765432 0Port A$000Port BPort CPort 0 (digital)Port A DDRPort BOORPort C DDRPort 0 (anall)g)Timer Data Reg.Timer CTRL Reg.Not Used (22 Bytes)7 o'-____ A ____ -J 1Accumulatorn+lo,-________ X .... 1 Index Registern-3 Accumulator n+211 on-2 Index Register n+3 PCn-1 1 1 1 11PCW n~411 5 4o1~'--~ 0 1010101 ....._"'--~.....&_"'--_____ 0 1 111 SP ..... I Stack PointerPCL' n+5$001$002$003""$004"$005"$006'$007""$008$009$OOA$01F$020$07F~_--___________ ....JI Program Counter200Push• For subroutine calls, only PCH and PCL are stacked.Figure 3 Interrupt Stacking Order~HITACHIFigure 4 Programming ModelCondition Code RegisterCarry /BorrowZeroNegativeInterrupt MaskHalf Carry

----------------------------------------------------------------HD6805V1• REGISTERSThe CPU has five registers available to the programmer.They are shown in Figure 4 and are explained in the followingparagraphs.• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datamanipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddressing mode. It contains an 8-bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for limited calculations and datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is a 12-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 12-bit register that contains the addressof the next free location on the stack. Initially, the stack pointeris set to location $07F and is decremented as data is beingpushed onto the stack and incremented as data is being pulledfrom the stack. The six most significant bits of the stack pointerare permanently set to 0000011. During an MCU reset or thereset stack pointer (RSP) instruction, the stack pointer is setto location $07F. Subroutines and interrupts may be nesteddown to location $061 which allows the programmer to use upto IS levels of subroutine calls.• Condition Code Register (CC)The condition code register is a 5-bit register in which eachbit is used to indicate or flag the r~sults of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained in the followingparagraphs.Half Carry (H)Used during arithmetic operations (ADD and AOC) toindicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask the timer and external interrupt (INT).If an interrupt occurs while this bit is set it is latched and will beprocessed as soon as the interrupt bit is reset.Negative (N)Used to indicate that the result of the last arithmetic, logicalor data manipulation was negative (bit 7 in result equal to alogical one).Zero (Z)Used to indicate that the result of the last arithmetic. logicalor data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the arithmeticlogic unit (ALU) occurred during the last arithmetic operation.This bit is also affected during bit test and branch instructions,shifts, and rotates.• TIMERThe MCU timer circuitry is shown in Figure 5. The 8-bitcounter, the Timer Data Register (TOR), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the timer reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register (TCR) isset. The CPU responds to this interrupt by saving the presentCPU state on the stack, fetching the timer interrupt vector fromlocations $FF8 and $FF9 and executing the interrupt routine.The timer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the TCR. The interrupt bit (I bit) in theCondition Code Register also prevents a timer interrupt frombeing processed.The clock input to the timer can be from an external sourceapplied to the TIMER input pin or it can be the internal qnsignal. When the 1/>2 signal is used as the source, it can be gatedby an input applied to the TIMER input pin allowing theuser to easily perform pulse-width measurements. The TIMERinput pin must be tied to Vee, for ungated 1/>2 clock input tothe timer prescaler. The source of the clock input is one of theoptions that has to be specified before manufacture of theMCU. A prescaler option can be applied to the clock input thatextends the timing interval up to a maximum of 128 counts(/>2(Internal!TimerInputPin.,.-----.,.• IIII L _____.JITIR; Timer Interrupt RequestTIM; Timer Interrupt MaskManufacturingMask OptionsWriteReadFigure 5 Timer Block Diagram~HITACHI 201

HD6805V1---------------------------------------------------------------before decrementing the counter (TDR). The timer continuesto count past zero, falling through to $FF from zero and thencontinuing the count. Thus, the counter (TDR) can be read atany time by reading the TDR. This allows a program to determinethe length of time since a timer interrupt has occurredand not disturb the counting process.The TDR is 8-bit Read/Write Register in location $008.At power-up or reset, the TDR and the prescaler are initializedwith all logical ones.The Timer Interrupt Request bit (bit 7 of the TCR) is set byhardware when timer count reaches zero, and is cleared by programor by hardware reset. The bit 6 of the TCR is writable byprogram. Both of those bits can be read by CPU.(NOTE) If the MCU Timer is not used, the TIMER input pinmust be grounded.• SELF CHECKThe self-check capability of the MeU provides an internalcheck to determine if the part is functional. Connect the MCUas shown in Figure 6 and monitor the output of port C bit 3 foran oscillation of approximately 3Hz.• RESETSThe MCU can be reset three ways; by initial power-up, bythe external reset input (RES) and by an optional internallow voltage inhibit circuit, see Figure 7. All the I/O port areinitialized to input mode (DDRs are cleared) during reset.During power-up, a minimum of 100 milliseconds is neededbefore allowing th.e RES input to go "High".This time allows the internal crystal oscillator to stabilize.Connecting a capacitor to the RES input, as shown in Figure 8,typically provides sufficient delay.T 2 . 2 1'F2- INT2 RESCXTALEXTALA, 40A. 39As 38A.~A, 36A, 35A, 34An~HD6805V1.+9V 8 TIMER (Resistor option)rB,~NUM B. 31V CC B, 30B • 29. P"O~l It:. 9 Co B,~33011 ~J. ". i.. 010 C, B, 27.p,.,ort r.:. ~" C, B, 26J..32},:i \!!: ~ 12 C,Bn 25vv ~10kO 13c.{ok'ov.A.A."14 C,j0,tc0v 15c.1°.l~16vvvC,V cc : Pin 4vss : P,n 1Figure 6 Self Check ConnectionsRe f e rt 0 F, gure 9 about crystal option~PinIntllrn.1Rll$l!t----------------~202Figure 7 Power Up and RES Timing~HITACHI

--------------------~--------------------------------------------HD6805VlPart ofHD6805V1MCU2• INTERNAL OSCILLATOR OPTIONSThe internal oscillator circuit is designed to require a minimumof external components. A crystal, a resistor, a jumperwire, or an external signal may be used to generate a systemclock with various stability/cost tradeoff. A manufacturingmask option is required to select either the crystal oscillator orthe RC oscillator circuit. The different connection methods areshown in Figure 9. Crystal specifications are given in Figure 10.A resistor selection graph is given in Figure II.Figure 8 Power Up Reset Delay Circuit6 XTAL6 XTAL4 MHz c:::Jmax5 EXTALHD6805V1MCU5 EXTALHD6805V1MCUCrystalApproximately 25% AccuracyExternal: JumperVee6 XTAL6 XTAL~' v',/'\,,----tExternalClockInput5 EXTALHD6805V1MCURNoConnection5 EXTALHD6805V1MCUExternal ClockCRYSTAL OPTIONSApproximately 15% AccuracyExternal ResistorRESISTOR OPTIONSFigure 9 Internal Oscillator OptionsXTAL~' ~ EXTAL6 C- KS ~ 5C,oIAT - Cut Parallel Resonance CrystalC" = 7 pF max.1= 4 MHzRS = 60 H max.II~f'"~u.5432,j~\,I JVee = 5.25VTA = 25°C -\ "'-~~............~ ,Figure 10 Crystal Parameterso 5 10 1 5 20 25 30 35 40 45 50Resistance Ikn)Figure 11 Typical Resistor Selection Graph~HITACHI 203

HD6805V1------------------------------------------------------------1 - I7F -SPo -DDR'sCLR INT LogicFF - Timer7 F _ Pre scaler7F _ TCRStackPC,X,A,CCYTIMERLoad PC FromReset :$FFE, $FFFLoad PC FromSWI :$FFC, $FFDJ1iJT:$FFA, $FFBTIMER :$FF8,$F F9FetchInstructionYSWIExecuteInstructionFigure 12 Interrupt Processing FlowchartFigure 13 Typical Port I/O CircuitryDataDirectionRegisterBit1oOutputData BitoOutputStateo3·StateInput toMCUoPin204~HITACHI

-----------------------------------------------------------------HD6805V1• INTERRUPTSThe CPU can be interrupted three different ways: throughthe external interrupt (INT) input pin, the internal timer interruptrequest_ and a software interrupt instruction (SWI). Whenany interrupt occurs, processing is suspended, the present CPUstate is pushed onto the stack, the interrupt bit (I) in the ConditionCode Register is set, the address of the interrupt routine isobtained from the appropriate interrupt vector address, and theinterrupt routine is executed. The interrupt service routinesnormally end with a return from interrupt (RTI) instructionwhich allows the CPU to resume processing of the programprior to the interrupt. Table 1 provides a listing of the interrupts,their priority, and the vector address that contain thestarting address of the appropriate interrupt routine.A flowchart of the interrupt processing sequence is givenin Fig. 12.Table 1 Interrupt PrioritiesInterrupt Priority Vector Address~ 1- $FFE and $FFFSWI 2 $FFC and $FFDmT 3 $FFA and $FFBTIMER 4 $FFB and $FF9• INPUT/OUTPUTThere are 24 input/output pins. All pins are programmableas either inputs or outputs under software control of the cor·responding Data Direction Register (DOR). When programmedas outputs, the latched output data is readable as input data,regardless of the logic levels at the output pin due to outputloading (see Fig. 13). When Port B is programmed for outputsit is capable of sinking lOrnA on each pin (VOL = 1 V max).All input/output lines are TTL compatible as both inputs andoutputs. Port A is CMOS compatible as outputs, and Port BandC lines are CMOS compatible as inpu ts. Figure 14 provides someexamples of port connections.• INPUTPort 0 can be used ,as either 8 TTL compatible inputs or 1threshold input and 7 analog inputs pins. Fig. 15 (a) shows theconstruction of port O. The Port 0 register at location $003stores TTL compatible inputs, and those in location $007 storethe result of comparison Do to 06 inputs with 07 thresholdinput. Port 0 has not only the conventional function as inputsbut also voltage-comparison function. Applying the latter, caneasily check that 7 analog input electric potential max. exceedsthe limit with the construction shown in Fig. 15 (b). Also, usingone output pin of MCU, after external capacity is dischargedat the preset state, charge the CR circuit of long enough timeconstant, apply the charging curve to the 07 pin. The constructiondescribed above is shown in Fig. 15 (c). The comparedresult of Do to 06 is regularly monitored, which gives theanalog input electric potential' applied to Do to 06 pins frominverted time. This method enables 7 inputs to be convertedfrom analog to digital. Furthermore, combination of two func.tions gives 3 level voltages from Do to 06. Fig. 15 (d) providesthe example when VTH is set to 3.5V.• BIT MANIPULATIONThe MCU has the ability to set or clear any single randomaccess memory or input/output bit (except the data directionregisters) with a single instruction (BSET, BCLR). Any bit inthe page zero read only memory can be tested, using the BRSETand BRCLR instructions, and the program branches as a resultof its state. This capability to work with any bit in RAM, ROMor I/O allows the user to have individual flags in RAM or tohandle single I/O bits as control lines. The example in Figure 16illustrates the usefulness of the bit manipulation and testPort AAo·mA '·inLI LoadA, ·Port BPort A Programmed as outputls), driving CMOS and TTL Load directly.la)Port B Programmed as output Is). driving Darlington base directly.Ib)+v+VPort B·•8, ·10mA - maxPort C t----.... - CMOS InverterC 7RPort B Programmed as output Is), driving LEDls) directly.Ic)Port C Programmed as outputls), driving CMOS loads, using external pull·upresistors.Id)Figure 14 Typical Port Connections$ HITACHI 205.

HD6805V1----------------------------------------------------------------instructions. Assume that bit 0 of port A is connected to a zerocrossing detector circuit and that bit 1 of port A is connected tothe trigger of a TRIAC which power the controlled hardware.This program, which uses only seven ROM locations, pro-vides tum-on of the TRIAC within 14 microseconds of the zerocrossing. The timer could also be incorporated to provide tumonat some later time which would permit pulse-width modUlationofthe controlled power.$003 RaadInternal Bus(BitO - Bit6)+Internal Bus(Bit 7)$003 Read(a) The logic configuration of Port 0Input Port (0 7 )PortC1-- 0 "",-, --- Reference Level1- 0 .;..' ---- Analog Input 60,PortoPorto0,\--";""'--Analog Input 61- 0 ...;;.° __ Analog Input 0DoI-~--- Analog Input 0(b) Seven analog inputs and a reference level input of Port 0(c) Application to AID convertorPort0Q,0,~VTH (= 3.5V)3 Levels Input 6Input ($003) ($007)VoltageOV -0.8V 0 02.0V - 3.3V 1 03.7V - Vee 1 1Do3 Levels Input 0(d) Application to 3 levels inputFigure 15 Configuration and Application of Port 0206 ~HITACHI

---------------------------------------------------------------HD6805V1SELF 1 BRClR 0, · PORT A, SELF 1BSET 1, PORT ABelR 1, PORT AFigure 16 Bit Manipulation · Example• ADDRESSING MODESThe CPU has ten addressing modes available for use by theprogrammer. They are explained and illustrated briefly in thefollowing paragraphs.• ImmediateRefer to Figure 17. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 18. In direct addressing, the address of theoperand is contained in the second byte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage of thisefficient memory addressing mode.• ExtendedRefer to Figure 19. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instruc·tions are three bytes long.• RelativeRefer to Figure 20. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA=(pC)+2+Rel. Rei is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken Rel=O, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 of the present instruction. Theseinstructions are two bytes long.• Indexed (No Offset)Refer to Figure 21. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and their EA is the contents of the index register.• Indexed (8-bit Offset)Refer to Figure 22. The EA is calculated by adding thecontents of the byte following the opcode to the contents ofthe index register. In this mode, 5 II low memory locations areaccessable. These instructions occupy two bytes.• Indexed (16-bit Offset)Refer to Figure 23. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode are threebytes long.• Bit Set/ClearRefer to Figure 24. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 25. This mode of addressing applies toinstructions which can test any bit in the first 256 locations($OO·$FF) and branch to any location relative to the Pc. Thebyte to be tested is addressed by the byte following the opcode.The individual bit within that byte to be tested is addressed bythe lower three bits of the opcode. The third byte is the relativeaddress to be added to the program counter if the branch condi·tion is met. These instructions are three bytes long. The value ofthe bit tested is written to the carry bit in the condition coderegister.• ImpliedRefer to Figure 26. The implied mode of addressing has noEA. All the information necessary to execute an instruction iscontained in the opcode. Direct operations on the accumulatorand the index register are included in this mode of addressing.In addition, control instructions such as SWI, RTI belong to thisgroup. All implied addressing instructions are one byte long.• INSTRUCTION SETThe MCV has a set of 59 basic instructions. They can bedivided into five different types: register/memory, read/modify/write, branch, bit manipulation, and control. The followingparagraphs briefly explain each type. All the instructions withina given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operand iseither the accumulator or the index register. The other operandis obtained from memory using one of the addressing modes.The jump unconditional (JMP) and jump to subroutine (JSR)instructions have no register operand. Refer to Table 2.• Read/ModitvlWrite InstructionsThese instructions read a memory location or a register,modify or test its contents, and write the modified value backto memory or to the register. The test for negative or zero(TST) instruction is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table3.• Branch InstructionsThe branch instructions cause a branch from the programwhen a certain condition is met. Refer to Table 4.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 256 bytesof the memory. One group either sets or clears. The other groupperforms the bit test and branch operations. Refer to Table 5.• Control InstructionsThe control instructions control the MCU operations duringprogram execution. Refer to Table 6.• Alphabetical ListingThe complete instruction set is given in alphabetical order inTable 7.• OpcodeMapTable 8 is an opcode map for the instructions used on theMCV.~HITACHI 207

HD6805V1---------------------------------------------------------------MemoryiIIII8IIIPROG LOA #$F8 :::1 : 1AIndLStack PointProg Count05COCCFa§I•I•IFigure 17 Immediate Addressing ExampleCAT FC8 320048I•IIII+ Memory20PROG LOA CA T 0520 86052E 48iI•IIIIlEAr 0048 1/'~Adder~~IIA20~ IIndex RegIIStack PointProg Count052FCCIII~IIIIFigure 18 Direct Addressing Example208~HITACHI

-----------------------------------------------------------------HD6805V1PROG LOA CATMemory,• •~0000~~O4OA 06040B E5 JStack Point• •• • Prog CountCAT FCB 64 O6E5 40 040CACC40Index RegFigure 19 Extended Addressing ExampleMemory, i@•2704A8 180000AI.Stack PointIndex Reg§I , I,Figure 20 Relative Addressing Example~HITACHI 209

HD6805V1-------------------------------------------------------------MemorvATABL FCC t Lit OOBB 4C 4C49 Index RegB8PROG LOA XI I Stack Point~F4~§Prog Count05F5CCFigure 21Indexed (No Offset) Addressing ExampleTABL FeB #BF 0089Melorvi iIItIIBFlEAIOO8C IAdder/ ~FeB #86 OO8A 86 ~ AFeB #OB oo8BDBJICFIFCB #CF 008CCFIndex RegPROG LOA TABl. X 075B075CIi I I 03IIE689§IIIStack PointI I IIProg Count0750ICCFigure 22 Indexed (S·Bit Offset) Addressing Example210 ~HITACHI

-----------------------------------------------------------------HD6805VlMemoryiIPROGlOA§TABL. X:: EBADBIndex Reg-02Stack Point06M~t----~ProgCount0695IICCTABlFCBFCBFCBFCB#BF OnE BF#86 OnF 86#OB 0780 DB#CF 0781 CFFigure 23 Indexed (16·Bit Offset) Addressing ExampleMemoryPORT BEau 0001 BFI0000AIndex RegPROG BelR 6. PORT B 058F 10.------t0590 01Stack PointProg Count0591II~IIICCFigure 24 Bit Set/Clear Addressing Example$ HITACHI211

H D6805V 1 -~-PORT C EQU 2AIndex RegStack PointPROG BRCLR2. PORT C. PROG 2Prog Count0594CC§IIFigure 25 B· It T est and Branch Add ressmg . ExamplePROGTAXI§IIIIMemorv05BA~IIIIII~IIIII _____ -J.EAFigure 261m p I· led Addressing E xampleA05BBCC212~HITACHI

-----------------------------------------------------------------HD6805V1Table 2 Register/Memory InstructionsAddressing Modes--Indexed IndexedIndexedFunction Mnemonic Immediate Direct Extended(No Offset) (8·Bit Offset) (16·8it Offset)Op # # Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code 8ytes Cycles Code Bytes Cycles Code 8ytes Cycles Code Bytes CyclesL08d A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6L08d X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6Store A in Memory STA - - - 87 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7Add MOImory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6Add Memory andCarry to AAOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6Subtract Memory fromA with Borrowsec A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6Exclusive OR Memorywith AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory with A(Logical Compare)E06 A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6CMP Al 2 2 Bl 2 4 Cl 3 5 Fl 1 4 El 2 5 01 3 6CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6Jump Unconditional JMP - - - BC 2 ,3 CC 3 4 FC 1 3 EC 2 4 DC 3 5Jump to Subroutine JSR - - - SO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9Table 3 Read/Modify/Write InstructionsAddressing ModesFunction Mne!Tlonic Implied (A) Implied (X) DirectIndexed(No Offset)Indexed(8·Bit Offset)Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIncrement INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7Negate(2'5 Complement)NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Test for Negative orZeroTST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7~HITACHI 213

-----.---~- .--.---~HD6805V1---------------------------------------------------------------Table 4 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch IF Higher BHI 22 2 4Branch IF Lower or Same BLS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch IF Carry Set BCS 25 2 4(Branch IF Lower) (BLO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch IF Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch I F Plus BPL 2A 2 4Branch IF Minus BMI 2B 2 4Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch IF Interrupt line is Low BIL 2E 2 4__ ~~~~!~Inte~rup~ line is High BIH 2F 2 4Branch to Subroutine BSR AO 2 8Table 5 Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set BRSET n (n=O ..... 7) - - - 2-n----------------3 10Branch I F Bit n is clear BRCLR n (n=O ..... 7) - - - .o1+2-n 3 10Set Bit n BSET n (n=O ..... 7) 10+2-n 2 7 - - --------"--- -----~---Clear bit n BCLR n (n=O ..... 7) 11+2-n 2 7 - - -FunctionTable 6 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X-----------TAX 97 1 2Transfer X to A-----TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit CLC 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit Cli 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9--------------- --Reset Stack Pointer RSP 9C 1 2No·Operation NOP 90 1 2214 ~HITACHI

---------------------------------------------------------------HD6805V1Table 7 Instruction SetAddressing ModesCondition CodeMnemonicIndexedBit BitImme- Ex- Re-Indexed IndexedImplied Direct (No Setl Test & H I N I z Cdiate tended lative(8 Bits) (16 Bits)Offset)Clear Branch IADC x x x x x x 1\ /\ /\ /\ADD x x x x x x 1\ • /\ /\ /\AND x x x x x x /\ /\ •ASl x x x x /\ /\ /\ASR x x x x /\ /\ /\BCC x BClR x• BCS x BEQ x BHCC x BHCS x BHI x BHS x-------BIH x----• Bil x----- ----e---• • BIT x x x x x x• /\ /\ BlO x BlS x• • • BMC x• I BMI x-------~. -- ---- -- • BMS x BNE x BPl x BRA x BRN x •BRClR x• • • • /\BRSET x /\BSET x BSR x• •ClC x• • 0CLI x• 0 • • ClR x x x x• 0 1 •CMP x x x x x x /\ /\ /\COM x x x x• /\ /\ 1CPX x x x x x x• /\ /\ /\DEC x x x x /\ /\ EaR x x x x x x--• /\ /\ INC x x x x /\ /\ JMP x x x x x• JSR x x x x x• • • lDA x x x x x x /\ /\ lDX x x x x x x• • /\ /\ •Condition Code Symbols:H Half Carry (From Bit 31 C Carry BorrowI Interrupt Mask /\ Test and Set if True, Cleared Otherwise(to be continued)N Negative (Sign Bitl • Not AffectedZ Zero~HITACHI215

HD6805V1---------------------------------------------------------------Table 7 Instruction SetAddressing ModesCondition CodeR -----, IndexedBit BitMnemonic ImpliedImmediateDirect Ex- e- (No Indexed IndexedSetl Test & H I N Z Ctended lative Offset) (8 Bits) (16 Bits)Clear BranchLSL x x x x • • /\ /\ /\LSR x x x x • • 0 /\ /\NEG x x x x • • /\ /\ /\NOP x • • • • •ORA x x x x x x • • /\ /\ •RO L x x x x • • 1\ /\ /\--------~-------~----r_-----+_----~----_4~----_+------+_------+_----r_----_+--_r--~_+--_r---ROR x x x x • • /\ /\ /\RSP x • • • • •RTI x ? ? ? ? ?RTS x • • • • •SBC x x x x x x ·. /\ /\ /\SEC x • • • • 1SEI x • 1 • • •STA x x x x xSTX x x x x xSUB x x x x x x · . /\ /\ /\SWI x • 1 • • •TAX x• • • • •TST x x x xTXA x • • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry/BorrowI Interrupt Mask 1\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack216 ~HITACHI

-----------------------------------------------------------------HD6805VlTable 8Opcode MapBit Manipulation Branch Read/Modify /Write Control Register /MemoryTest & SetlRei OIRI A I X I ,X1 I ,XO IMP IMP IMM I OIRBranch ClearI EXT I ,X2 I )

HD6805T2-------------­MCU (Microcomputer Unit with PLL Logic)-ADVANCE INFORMATION-The HD680ST2 is the 8·bit Microcomputer Unit (MCU)which contains a CPU, on.chip clock, ROM, RAM, lID, Timerand the PLL Logic for an RF synthesizer. It is designed for theuser who needs an economical microcomputer with the provencapabilities of the HD6800·based instruction set.The following are some of the hardware and software high.lights of the MCU.• HARDWARE FEATURES• 8·Bit Arthitecture• 64 Bytes of RAM• Memory Mapped I/O• 2508 8ytes of User ROM• Internal 8·Bit Timer with 7·Bit Prescaler• Timer Start/Stop and Source Select• Vectored Interrupts - External and Timer• 19 TTL/CMOS Compatible I/O Lines; 8 Lines are LED com·patible• On-Chip Clock Circuit• Self·Check Mode• Master Reset• Low Voltage Inhibit• 14·Bit Binary Variable Divider• 10·Stage Mask·Programmable Reference Divider• Three·State Phase and Frequency Comparator• Suitable for TV Frequency Synthesizers• 5" Vdc Single Supply• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM, RAM and I/O• Compatible with MC6805T2A,A,POrt ~!A A.,1(0 AsL.lneI A.A·HD6805T2P• PIN ARRANGEMENTc,c,finB.B,B,• BLOCK DIAGRAM(DP·28)(Top View)A.B,B.B,B.B,B,B,Pon BJB B.I/O B.lines I!B,218 $ HITACHI

HD6805W1MCU (Microcomputer Unit)The H0680SWI is an 8-bit microcomputer unit (MCU)which contains a CPU, on-chip clock, ROM, RAM, standbyRAM, an A/D Converter, I/O and two timers. It is a member ofthe H06805 family which is designed for user who needs aneconomical microcomputer with proven capabilities of theHD6800-based instruction set.The following are some of the hardware and software highlightsof the MCU.HD6805W1P-PRELIMINARY-• HARDWARE FEATURES• 8-Bit Architecture• 96 Bytes of RAM(8 bytes are standby RAM functions)• Memory Mapped I/O• 3848 Bytes of User ROM• Internal 8-Bit Timer (Timer 1) with 7-Bit Prescaler• Internal8-Bit Programmable Timer (Timer 2) • PIN ARRANGEMENT• Interl'upts - 2 External and 4 Timers• 23 TTL/CMOS compatible I/O Lines; 8 Lines DirectlyDrive LEOs.• On-Chip 8-Bit, 4-Channel A/D Converter• On-Chip Clock Circuit• Self-Check Mode• Master Reset• Low Voltage Inhibit• Complete Development System Support by Evaluation Kit• 5 Vdc Single Supply• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM, RAM and I/O• Compatible with MC6805P2, HD6805S1 and HD6805V1VssRAME/RESINT,VeeEXTALXTALNUMTIMERCoC,C.C,C.IC/C.OC/C.INT. 100ANo/D,AN,/D.AN./D,AN,/D.(DP-40)HD6805Wl(Top View)A,A.A.A.A.A.A,AoB,B.B.B.B.B.B,BoAVeeAVssVRH/D.Vee Standby~HITACHI219

HD6805W1---------------------------------------------------------------• BLOCK DIAGRAMTIMER78Port BI/O lines(OC)(lC)Port AI/O LinesTlMER-27 Presealer 2Prescaler Control8 Register 2Timer Dataa Register 2Timera Status Register 2Output Comparea RegisterInput Capture8 RegisterTimer Control8 Register 2~-~-...,AoAi!! cA2 0As '&' '~I»A. a: .~ ...« o!!AsA. 0 "'IIa.. oa:A.!! ,s.aaAccumulatorIndex RegisterAxCondition CodeS Register CCStack Point6 SPProgram Counter4 "High" PCHProgram Countera "low" PClCPUCPU ControlAlU(RAME) Vee Standbyc0'ij~'SoIIa:~! coco·!!1ii2'oa: 0a..ca~:~ ~ 'ra:o!!0ta·!!1ii2'oa: 0a..BoB.B.BsB.BsPort CI/O LinesCoC.c.CsC.Cs (lC)C. (OC)Port 0Input LinesDo (INT.)D. (ANo)O2 (AN.)0, (AN.)D. (AN,)Os (VRH)ADC LinesAVeeAVSS(VRH)(ANo)(ANd(AN2)(AN,)A/D ControlStatus RegisteraaAID ResultRegister(NOTE)The contents of ( ) items can be changed by software,220$ HITACHI

-----------------------------------------------------------------HD6805W1• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee -0.3 - +7.0Input Voltage (EXCEPT TIMER) -0.3 - +7.0V inInput Voltage (TIMER)-0.3 - +12.0Operating Temperature T opr o -+70Storage Temperature T stg -55 - +150UnitVVV°c°c(NOTE)This device has an input protection circuit for high quiescent voltage and field, however, be careful notto impress a high input voltage than the insulation maximum value to the high input impedance circuit.To insure normal operation, the following are recommended for Vin and V out :VSS ~ (Vin or Vout) ~ Vee• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta = O-+70°C, unless otherwise noted.)Item Symbol Test Condition minRES 4.0Input "High" Voltage INTI ,INT2 3.0Input "High" Voltage TimerAll Others V IH 2.0Timer Mode 2.0Self-Check Mode 9.0RES -0.3Input "Low" VoltageINTI ,INT2-0.3V ILAll Others-0.3(except EXTAL)Power Dissipation Po -Low Voltage Recover LVR -Low Voltage Inhibit LVI -TIMER -20Input Leak Current INTI,INT2 IlL Vin=0.4V-Vee -50EXTAL(Crystal Mode) -1200Nonoperation Mode V SBB 4.0Standby VoltageOperation Mode VSB 4.75Standby Current Nonoperation Mode ISBB VSBB=4.0V -typ max Unit- Vee V- Vee V- Vee V- Vee V- 11.0 V- 0.8 V- 0.8 V- 0.8 V- 750 mW- 4.75 V4.0 - V- 20 p.A- 50 p.A- 0 p.A- VeeV- Vee- 3 mA• AC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta::: O-+70°C, unless otherwise noted.)Item Symbol Test Condition minClock Frequency fel 0.4Cycle Time teye 1.0Oscillation Frequency (External Resistor Mode) fexT Rep =15.0kU±1% -TNil Pulse WidthRES Pulse WidthTIMER Pulse WidthOscillation Start-up Time (Crystal Mode)tlWLtRWLtTwLtoset eye+250t eye+250teye+250CL =22pF±20%Rs=60U max.-Delay Time Reset tRHL External Cap. = 2.2 p.F 100I nput CapacitanceI XTAL, VRH/Ds --I All Others Cin Vin=OV~HITACHItyp max Unit- 4.0 MHz- 10 p.s3.4 - MHz- - ns- - ns- - ns- 100 ms- - ms- 35 pF- 10 pF221

HD6805Wl---------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±O.5V. Vss = GND. Ta = 0'" +70°C. unless otherwise noted.)Output "High" VoltageItem Symbol Test Condition min typ max UnitPort APort BIOH =-10J.LA 3.5- - VIOH = -looJ.LA 2.4 - - VV OH IOH = -200 J.LA 2.4 - - V----IOH = ·1 mA 1.5 - - VPort C IOH=-l00J.LA 2.4 - - VPorts A and C IOL = 1.6 mA - - 0.5 VOutput "Low" Voltage VOL IOL = 3.2 rnA - - 0.5 VPort BIOL = 10 mA - - 1.0 VInput "High" Voltage Ports A. B. C V IH 2.0 - Vee VInput "Low" Voltage and D V IL -0.3 - 0.8 VPort AYin = 0.8V -500 - - J.LA---------------._--Input Leak Current IlL Yin = 2V -300 - - J.LA--.-1--------~-. ._- ---- ----.-----Ports B. C and D Yin = 0.4V-Vee -20 - 20 J.LA• AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V. Vss = AVSS = GMD. Ta = 0 - +70°C. unlessotherwise noted.)Item Symbol Test Condition min typ max UnitAnalog Power SupplyVoltageAVec 4.75 5.25 5.75 VAnalog Input Voltage AV in 0 - V RH VReference VoltageAnalog Multiplexer InputCapacitanceV RH4.75V ~ Vee ~ 5.25V 4.0 - Vee V5.25V < V ee ~ 5.75V 4.0 - 5.25 V- - 7.5 pFResolution Power - 8 - BitConversion Time at 4MHz 76 76 76 tCYCI nput Channels 4 4 4 ChannelAbsolute Accuracy Ta = 25°C - - ±1.5 LSBOff-channel Leak CurrentOff-channel Leak CurrentAV in = 5.0V. AVec =4.75V. Ta= 25°C.On-channel AV in =OVAV in = OV. AVec = 4.75V. Ta = 25°C.On-channel AV in =5V- 10 100 nA-100 -10 - nA222 ~HITACHI

---------------------------------------------------------------HD6805W1TTL Equiv. (Port B) TTL Equiv. (Ports A, C and D)VeeVeeTest PointIi = 3.2mA1.4knTest Point2.4kHVi40 pF 12 kn 30 pFVi(NOTE)1. Load capacitance includes the floating capacitance of the probe and the jig etc.2. All diodes are 152074(9 or equivalent.Figure 1 Bus Timing Test Loads• SIGNAL DESCRIPTIONThe input and output signals for the MCU, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee and VssVoltage is supplied to the MCV using these two pins. Vee is5 .25V ±O.5V. V 55 is the ground connection.• INT J /INT2This pin provides the capability for asynchronously applyingan external interrupt to the MCU. Refer to INTERRUPTSfor additional information.• XTAL and EXTALThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum), a resistor or an externalsignal can be connected to these pins to provide a system clockwith various stability/cost tradeoffs. Refer to INTERNAL OS­CILLATOR OPTIONS for recommendations about these inputs.• TIMERThis pin allows an external input to be used to count for theinternal timer circuitry. Refer to TIMER 1 and TIMER 2 foradditional information about the timer circuitry.• Vee StandbyVee Standby provides power to the standby portion of theRAM and the STBY PWR and RAME bits of the RAM ControlRegister. Voltage requirements depend on whether the MCUis in a powerup or powerdown state. In the powerup state, thepower supply should provide Vee and must reach V SB beforeRES reaches 4.0V. During powerdown, Vee standby mustremain above VSBB (min) to sustain the standby RAM andSTBY PWR bit. While in powerdown operation, the standbycurrent will not exceed ISBB'It is typical to power both Vee and Vee Standby from thesame source during normal operation. A diode must be usedbetween them to prevent supplying power to Vee duringpowerdown operation shown Figure 2.To sustain the standby RAM during powerdown, the followingsoftware or hardware are needed.(I) SoftwareWhen clearing the RAM Enable bit (RAME) which is bit 6of the RAM Control Register at location $OOIF, the RAMis disabled.Vee Standby must remain above V SSB (min).(2) HardwareWhen RAME pin is "Low" before powerdown, the RAM isdisabled. Vee Standby must remain above VSBS (min).• RESThis pin allows resetting of the MCV at times other than theautomatic resetting capability already in the MCV. Refer toRESETS for additional information.• NUMThis pin is not for user application and should be connectedto VSS.• I/O Lines (Ao ..... A 7 , 8 0 ..... 8 7 , Co ..... C 6 )There 23 lines are arranged into three ports (A, B and C). Alllines are programmable as either inputs or outputs under softwarecontrol of the Data Direction Register (DDR). Refer toINPUT/OUTPUT for additional information.• Input Lines (Do ..... Os)These are TTL compatible input lines, in location $003.These also allow analog inputs to be used for an AID converter.Refer to INPUT for additional information.Figure 2 Battery Backup for Vee Standby• RAMEThis pin is used for the external control of the RAM. Whenit is "Low" before powerdown, the RAM is disabled. If VeeStandby remains above V SBB (min), the standby RAM issustained.~HITACHI 223

HD6805W1,---------------------------------------------------------------• AVecThis pin is used for the power supply of the AID converter.When high accuracy is required, a different power source fromV cc is impressed asAVec = 5.25 ± O.SVConnect to Vee for all other cases.• ANo - AN3These pins allow analog inputs to be used for an AID converter.These inputs are switched by the internal multiplexerand selected by bit 0 and 1 of the AID Control Status Register(ADCSR: $OOE).• VAH and AVssThe input teJminal reference voltage for the AID converter is"High" (VRH) or "Low" (AVss). AVss is fixed at OV.• Input Capture (lC)This pin is used for input of Timer 2 control, in this case,Port C 5 should be configured as input. Refer to TIMER 2for more details.• Output Compare IOC)This pin is used for output of Timer 2 when the OutputCompare Register is matched with the Timer Data Register2. In this case, Port C6 should be configured as an output.Refer to TIMER 2 for more details.• MEMORYThe MCV memory is configured as shown in Figure 3. Duringthe interrupt processing, the contents of the CPU registers are .pushed onto the stack in the order shown in Figure 4. Sincethe stack pointer decrements during pushes. the low order byte(PCl) of the program counter is stacked first; then the highorder three bits (PCH) are stacked. This ensures that the programcounter is loaded correctly as the stack pointer incrementswhen it pulls data from the stack. A subroutine call will causeonly the program counter (PCH. PCl) contents to be pushedonto the stack.Caution: - Self Test ROM Address AreaSelf test ROM locations can not be used for a user program.If the user's program is in this location, it will be removed whenmanufacturing mask for production.000soooI/OPor1STuner031 SOIF032 S020RAM196 81127 S07F128 S080Port ASOOOPort BSIlO IPoneSIlO2Pon 0SIlO3"Por1 A OOR ~.Pall 8 OOASIlOS'POtl C DOR$006'SIlO 7Timer Oal.Reg.l $008ROM13834 81Timer CTAL Rig 1 $009~neousRf!9. __ SOOA1----.------SIlO81--___ ._____-lSllOC1-______________ $000AID CTAL Slllus ReqSODEAID Result RegSOOF ••I-____________ ~SOIO1-_____________ ~SOl1~----.. ------__1S012f----. _________ ~SOI31-___________ __1$01.1-_________ SOlS:~~-------~ :::~Soli· .... ROM 112081.0811-_______ ~ ,FFI.082 .FF2In"""1)1 Vector.~-----------_ S0161-___________ __1$0171-__________ __1$018Prne.I" CTRL Reg, 2 $019Tim., Stilus Reg, 2Tlrner CTRL Reg 2Tuner 011. R.g. 2Output Comp.f. RevS01A-·SOl BSOleS010\1-_...:.,:;::np.:.:.U'..::C",:::.:,.:.:.u":.;.R;:::I9~__..... S01E· •~-~R=AM~C=O~""..::OI~R~.g---~:~____ S~.:d~Y ~~~I~ ~~~ ____ 1O~71028RAM 196 81S'I OCk ~'--_____-..I.__.....I107F.0000'--_______ ~.FFF·W,II,R ..··R,adRII·•• 'SI-"dby RAM UMI htll 8 by, .. o' RAMFigure 3 MCU Memorv Structure224 ~HITACHI

-----------------------------------------------------------------HD6805W1Pu shn-45 4 0 Pull, , ,1ConditionCode Registern +'n-3 Accumu lator n+2n-2Inde~ Register n+3n-' , , , , '1PCH" n+4PCL" n+5" For subroutine calls, only PCH and PCL are stackedFigure 4 Interrupt Stacking Order• REGISTERSThe CPU has five registers available to the programmer,as shown in Figure 5 and explained below."PC6 5"10101010101,1SPAX0I0I0I0IAccumulatorInde~ RegisterProgram CounterStack PointerCondition Code RegisterCarry!BorrowZeroFigure 5 Programming ModelNegativeInterrupt MaskHalf Carry• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datamanipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddressing mode and contains an 8-bit address that may beadded to an offset value to create an effective address. Theindex register can also be used for limited calculations or datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed. the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is a 12-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a l2-bit register that contains the addressof the next free location on the stack. Initially. the stack pointeris set to location $07F and is decremented as data is beingpushed onto the stack and incremented while data is beingpulled from the stack. The six most significant bits of the stackpointer are permanently set to 00000 I. During an MeU resetor reset stack pointer (RSP) instruction. the stack pointer isset to location $07F. Subroutines and interrupts may be nesteddown to location $041 which allows the programmer to use upto 31 levels of subroutine calls.• Condition Code Register (CC)The condition code register is a 5-bit register in which eachbit is used to indicate or flag the results of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained below.Half Carry (H)The half carry bit is used during arithmetic operations (ADDor ADC) to indicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask everything. If an interrupt occurswhile this bit is set. it is latched and will be processed as soon asthe interrupt bit is reset.Negative (N)The negative bit is used to indicate that the result of the lastarithmetic. logical or data manipulation was negative (bit 7 ina result equal to a logical one).Zero (Z)Zero is used to indicate that the result of the last arithmetic.logical or data manipulation was zero.Carry/Borrow (C)Carry/borrow is used to indicate that a carry or burrow outof the arithmetic logic unit (ALU) occurred during the lastarithmetic operation. This bit is also affected during bit test andbranch instructions. shifts and rotates.• TIMER 1The MCU timer circuitry is shown in Figure 6. The 8-bitcounter, Timer Data Register I (TOR 1), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the TORI reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register I (TCRI)is set. The CPU responds to this interrupt by saving the presentCPU state in the stack, fetching the timer I interrupt vectorfrom locations $FF8 and $FF9 and executing the interruptroutine. The timer I interrupt can be masked by setting thetimer interrupt mask bit (bit 6) in the TCRI. The interruptbit (I bit) in the Condition Code Register also prevents a timer Iinterrupt from being processed.The clock input to the timer I can be from an externalsource applied to the TIMER input pin or it can be the internalcf>z signal. When cf>z is used as the source, it can be gated by aninput applied to the TIMER input pin allowing the user toeasily perform pulse-Width measurements. The timer I continuesto count past zero, falling through to $FF from zeroand then continuing the count. Thus, the counter (TDRI)can be read at any time by reading the TDRI. This allows a~HITACHI 225

HD6805W11---------------------------------------------------------------program to determine the length of time since a timer interrupthas occurred and not disturb the counting process.At power-up or reset, the prescaler and the counter (TORI)are initialized with all logical ones; the timer 1 interrupt requestbit (bit 7) is cleared and the timer 1 interrupt mask bit (bit 6)is set. In order to release the timer 1 interrupt, bit 7 of theTCRI must be cleared by software.(NOTE) If the MCV Timer 1 and Timer 2 are not used, theTIMER input pin must be grounded.(lnternel Clock)~2--+--L..J3TimeOutWriteReadFigure 6 Timer Clock• Timer Control Register 1 (TCR1: $(09)The Timer Control Register 1 (TCRI) can control selectionof clock input source and prescaler dividing ratio and timerinterrupt.Timer Control Register 1 (TCR 1: $009)76543210I TIFITIMI151 1 150 VlM521M511Msoi. L Prescaler Dividing Ratio~.. Clock Input SourceTimer Interrupt Mask'-----------Timer Interrupt Request FlagAs shown in Table I, the selection of the clock input sourceis ISO. and lSI in the TCRl (bit 4 and bit 5) and 3 kinds ofinput are selectable. At reset, internal clock q,2 controlled bythe TIMER input (bit 4=1 , bit5=O) is selected.The prescaler dividing ratio is selected by MSO, MSI, andMS2 in the TCRI (bit 0, bit I, bit 2) as shown in Table 2. Thedividing ratio is selectable from eight ways (+1, +2, +4, +8,+16, +32, +64, +128). At reset, +1 mode is selected. The prescaleris initialized by writing in the TDRI.Timer 1 interrupt mask bit (TIM) allows the Timer 1 into226 _HITACHIinterrupt at "0" and masks at "1". Timer 1 interrupt causesTimer 1 interrupt request bit (TIF) to be set. TIF must becleared by software.Table 1 Selection of Clock I nput SourceTCRlBit 5 Bit 40011Clock Input Source0 Internal Clock q,'J *1 q,2 Controlled by TIMER Input0--1 Event Input From TIMER• The TIMER input pin must be tied to Vee. for uncontrolled tP2clock input.Table 2 Selection of Prescaler Dividing RatioTCRlBit 2 Bit 1 BitOPrescaler Dividing Ratio0 0 0 +10 0 1 +20 1 Q +40 1 1 +81 0 0 +161 0 1 +321 1 0 +641 1 1 + 128

---------------------------------------------------------------HD6805W1• TIMER 2The HD680SWI includes an 8-bit programmable timer(Timer 2) which can not only measure the input waveform butalso generate the output waveform. The pulse width for bothinput and output waveform can be varied from several microsecondsto several seconds.(NOTE) If the MCV Timer I and Timer 2 are not used, theTIMER input pin must be grounded.Timer 2 hardware consists of the followings.• an 8-bit control register 2• an 8-bit status register 2• an 8-bit timer data register 2• an 8-bit output compare register• an 8-bit input capture register• as-bit prescaler control register 2• a 7-bit pre scaler 2A block diagram of the timer 2 is shown in Figure 7.Output Compare Register(OCR: $010)88 bit RegisterL.... _____....J Read/WriteInput Capture Register (lCR: $01E)8 bit Register 8 ReadTimer Control Register 2(TCR2: $018)ICIOCI TOIInternal Interrupts Request·SignalFigure 7 Block Diagram of Timer 2• Timer Data Register 2 (TDR2: $01C)The main part of the Timer 2 is the 8-bit Timer Data Register2 (TDR2) as free-running counter, which is driven by internalclock 2 or the TIMER input and increments the value. Thevalues in the counter is always readable by software.The Timer Data Register 2 is Read/Write register and iscleared at reset.• Output Compare Register (OCR: $01 D)The Output Compare Register (OCR) is an 8-bit Read/Write register used to control an output waveform. The contentsof this register are always compared with those of the TDR2.When these two contents conform to each other, the flag (OCF)in the Timer Status Register 2 (TCR 2) is set and the value ofthe output level bit (OLVL) in the TCR2 is transferred to PortC6 (OC).If Port C6 's Data Direction Register (DDR) is "1" (ou tpu t),this value will appear at Port C6 (OC). Then the values of OCFand OLVL can be changed for the next compare. The OCR isset to $FF at reset.• Input Capture Register OCR: $01E)The Input Capture Register (lCR) is an 8-bit Read-only registerused to store the value of the TDR2 when Port Cs (IC)input transition occurs as defined by the input edge bit (IEDG)of the TCR2.In order to apply Port Cs (lC) input to the edge detectcircuit, the DDR of Port Cs should be cleared ("0"). *To ensure an input capture under all condition, Port Cs (IC)input pulse width should be 2 Enable-cycles at least.*The edge detect circuit always senses Port Cs (IC) even if theDDR is set with Port Cs output.~HITACHI 227

HD6805W1---------------------------------------------------------------• Timer Control Register 2 (TCR2: $01B)The Timer Control Register 2 (TCR2) consii>ts of an 5-bitregister of which all bits can be read and written.Timer Control Register 2 (TCR2: $01B)6543210I/1ZlZI ICIM I OCIM I TOIM IIEDG I OLVL IBit 0 OLVL Output LevelThis bit will appear at Port C6 when the value in the TDR2equals the value in the OCR, if the DDR of Port C6 is set. It iscleared by reset.Bit 1 IEDG Input EdgeThis bit determines which level transition of Port Cs (IC)input will trigger a data store to ICR from the TDR2. When thisfunction is used, it is necessary to clear DDR of Port Cs . WhenIEDG = 0, the negative edge triggers ("High" to "Low" transition).When IEDG = 1, the positive edge triggers ("Low" to"High" transition). It is cleared by reset.Bit 2 TOIM Timer Overflow Interrupt MaskWhen this bit is cleared, internal interrupt (TOI) is enabledby TOF interrupt but when set, interrupt is inhibited.Bit 3 OCIM Output Compare Interrupt MaskWhen this bit is cleared, internal interrupt (OCI) by OCFinterrupt occurs. When set, interrupt is inhibited.Bit 4 lelM Input Capture Interrupt MaskWhen this bit is cleared, internal interrupt (lCI) by ICFinterrupt occurs. When set, interrupt is inhibited.• Timer Status Register 2 (TSR2: $01A)The Timer Status Register 2 (TSR2) is an 8-bit read-onlyregister which indicates that;(I) A proper level transition has been detected on the inputpin with a subsequent transfer of the TDR2 value to theICR (ICF).(2) A match has been found between the TDR2 and the OCR(OCF).(3) The TDR2 is zero (TOF).Each of the event can generate 3 kinds of internal interruptrequest and is controlled by an individual inhibit bits in theTCR2. If the I bit in the Condition Code Register is cleared,priority vectors are generated in response to clearing eachinterrupt ma~k bit. Each bit is described below.Timer Status Register 2 (TSR2: SOlA)765432 0ICFI OCF I TOF LZIZIZI/1ZlBit 6 OC F Output Compare FlagThis read-only bit is set when a match is found between theOCR and the TDR2. It is cleared by reading the TSR2 and thenwriting to the OCR.Bit 7 ICF Input Capture FlagThis read-only bit is set to indicate a proper level transitionand cleared by reading the TSR2 and then reading the TCR2.User can write into port C6 by software.Accordingly, after port C6 has output by hardware and isimmediately write into by software, simultaneous cyclic pulsecontrol with a short width is easy.• Prescaler Control Register 2 (PCR2: $019)The selection of clock input source and prescaler dividingratio are performed by the Prescaler Control Register 2 (PCR2).Prescaler Control Register 2 (PCR2: $019)6 5 4 3 2 o1ZI MS2 MS1 MSOIZIZIIS1 ISOPrescaler Dividing Ratio1--_______ Clock Input SourceThe selection of clock input source is performed in threedifferent ways by bit 4 and bit 5 of the PCR2, as shown inTable 3. At reset, internal clock CP2 controlled by the TIMERinput (bit 4 = I, bit 5 = 0) is selected.The prescaler dividing ratio is selected by three bits in thePCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratiocan be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64, +128).At reset, +1 (bit 0 = bit 1 = bit 2 = 0) is selected.When writing into the PCR2, or when writing into the TDR2,prescaier is initialized to $FF.Table 3 Selection of Clock Input SourcePCR2Bit 5 Bit4Clock Input Source0 0 Internal Clock CP2 *0 1 CP2 Controlled by TIMER Input1 01 1 Event Input from TIMER• The TIMER input pin must be tied to Vee. for uncontrolled (/>,clock input.Bit 5 TOF Timer Overflow FlagThis read-only bit is set when the TDR2 contains $00.It is cleared by reading the TSR2 followed by reading of theTDR2.228 _HITACHI

---------------------------------------------------------------HD6805W1Table 4 Selection of Prescaler Dividing RatioPCR2Bit 2 Bit 1 BitOPrescaler Dividing Ratio0 0 0 + 10 0 1 +20 1 0 +40 1 1 +81 0 0 + 161 0 1 +321 1 0 +641 1 1 + 128• SELF CHECKThe MCV self check easily determines whether the LSIfunctions normally or not. When the MCV is connected asshown in Fig. 8, the outputs of port C3 (LED) flicker in normaloperation.• RESETSThe MCV can be reset three ways; by initial power-up, bythe external reset input (RES) and by an optional internal lowvoltage detect circuit, see Figure 9. All the I/O ports are initializedto input mode (DDRs are cleared) during reset.During power-up, a minimum 100 milliseconds is neededbefore allowing the RES input to go "High". This time allowsthe internal crystal oscillator to stabilize. Connecting a capacitorto the RES input, as shown in Figure 10, typically providessu fficien t delay.CAUTIONThe flag of the TSR2 will be sometimes cleared when manipulatingor testing the TSR2 by Read/Modify/Write instructionshown in Table 5. Don't use these instructions for read/write/test operation of the TSR2 flags.Table 5 Read/Modify/Write InstructionMnemonic Op Code # Bytes # CyclesINC3C26DEC3A26CLR3F26COM 3326NEG 3026ROL 3926ROR 3626LSL 3826LSR 3426ASR 3726ASL 3826TST3D263 INT A7 40'--A. 392 RES As 38....L7fT 2.2IJ F 6A4rE--XTAL A, 36A, 356EXTAL A, 3422pFr Ao~HD6805W1+9V 8 TIMERr(Crystal option)B7~NUM B. 31v cc B, 30B. 2933012.A. A Af.::j 9 C" B.,~330Sr.AA "-~ ~ 10 C, B, 27~¥sr r.:; ~11 C, B, 26132,,1 ~vvvVc c =Pin 4Vss = Pin 13;~?3.30n330n.~12 C, B" 25\!:!I C. Cs c. Vee Standby 2113 14 151VeeFigure 8 Self Check Connections2RESPin-------rInternalReset------------------~Part ofHD6805W1MCUFigure 9 Power Up and Reset TimingFigure 10 Power Up Reset Delay Circuit~HITACHI 229

HD6805W11-------------------------------------------------------------• INTERNAL OSCILLATOR OPTIONSThe internal oscillator circuit is designed to require a minimumof external components. A crystal (AT cut, 4 MHz max),a resistor, a jumper wire or an external signal may be used togenerate a system clock with various stability/cost tradeoffs.A manufacturing mask option is required to select either thecrystal oscillator or the RC oscillator circuit. Four differentconnection methods are shown in Figure 11. Crystal specificationsare given in Figure 12. A resistor selection graph isshown in Figure 13. EXTAL may be driven with a duty cycleof 50% with XTAL connected to ground.6 XTAL4m M a H x Z c:J 5 EXTALHD6805W1MCU6 XTALHD6805W15 EXTAL MCU22PF±20%=if.CrystalApproximately 25% AccuracyExternal JumperExternalClockInput6 XTALHD6805W1MCUVee~V,\I,\,.----IRNoConnection6 XTALExternal ClockApproximately 15% AccuracyExternal ResistorCRYSTAL OPTIONSRESISTOR OPTIONSFigure 11Internal Oscillator OptionsC.XTAL~~EXTAL• - ~~ 5AT - Cut Parallel Resonance CrystalCo = 7 pF max.f = 4 MHz IC. =22pF±20%)Rs z 60n max.Figure 12 Crystal Parameters54X~ 3>(Jii':)C7~u.2,I J.1\ Vee = 5.25VTa = 25°C -\1\'\'" f''" I'..... ~""o 5 10 15 20 25 30 35 40 45 50Resistance IknlFigure 13 Typical Resistor Selection Graph230 ~HITACHI

---------------------------------------------------------------HD6805Wl• INTERRUPTSThe MCU can be interrupted in seven different ways: throughexternal interrupt input pin (INTI and 1NT2), internal timerinterrupt request (Timer 1, ICI, OCI and OFI) and a softwareinterrupt instruction (SWI). 002 and Timer 1 are generated bythe same vector address. When interrupt occurs, processingof the program is suspended, the present CPU state is pushedonto the stack in the order sho-.yn in Figure 4. The interruptmask bit (I) of the Condition Code Register is set and the externalroutine priority address is achieved from the special externalvector address. After that, the external interruptroutine is executed. The interrupt serVice routines normallyend with a return from interrupt (RTf) instruction which allowsthe CPU to resume processing of the program prior to the interrupt.The priority interrupts are shown in Table 6 with thevector address that contains the starting address of the appropriateinterrupt routine. The interrupt sequence is shown asa flowchart in Figure 14.InterruptRESSWIINTITIMERI/INT2ICIOCIOFITable 6 Interrupt PrioritiesPriorityVector Address1 $FFE,$FFF2 $FFC,$FFD3 $FFA,$FFB4 $FF8,$FF95 $FF6. $FF76 $FF4.$FF57 $FF2,$FF3Cleary TIMER 1yICi1~17F~SPO~DDR'sCLR INT LogiC7F~MRFetch InstructionyOCIFF ~TDRlOO~TDR27 F ~ Prescaler 17 F ~ Prescaler 250~TCRllC~TCR2yOO~TSR210~PCR2Stack PC, X, CC, AExecute InstructionLoad PC FromSWI: $FFC, $FFDINT.: $FFA, $FFBTIMER. : $FF8, $FF9INT2 : $FF8, $FF9ICI: $FF6. $FF7OCI: $FF4. $FF5OFI: $FF2. $FF3Figure 14 Interrupt Flowchart~HITACHI231

HD6805W11--------------------------------------------------------~-----• Miscellaneous Register (MR: SOOA)The vector address generated by the external interrupt(1NT2) is the same as that of TIMERl as shown in Table 6.The Miscellaneous Register (MR) controls the 1NT2 interrupt.Bit 7 (IRF) of the MR is used as an INT2 interrupt requestflag. INT2 interrupt occurs at the 1NT2 negative edge, and IRFis set. 1NT2 interrupt or not can be proved by checking IRFby software in the interrupt routine of the vector address($FF8, $FF9). IRF should be reset by software (BCLR' in·struction).Bit 6 (1M) of the MR is an 1NT2 interrupt mask bit. Whenm is set, 1NT2 interrupt is disabled. 002 interrupt is alsodisabled by bit (I) of the Condition Code Register (CC) likeother interrupts.Miscellaneous Register (MR: SOOA)6 5 4 3 2 0IRF 1M VlZVL2V1ZI~----- INTa Interrupt Mask~--------INTa Interrupt Request FlagIRF is available for both read and write. However, IRF isnot writable by software. Therefore, IN'i2 interrupt cannot berequested by software. At reset, IRF is cleared and 1M is set.• INPUT IOUTPUTThere are 23 input/output pins. All pins (port A, B, and C)are programmable as either inputs or outputs under softwarecontrol of the corresponding Data Direction Register (DDR).The port I/O programming is accomplished by writing thecorresponding bit in the port DDR to a logic "l" for ou tpt ora logic "0" for input. On reset, all the DDRs are initializedto a logic "0" state to put the ports in the input mode. The portoutput registers are not initialized on reset but may be writtento before setting the DDR bits to avoid undefined levels.When programmed as outputs, the latched output data isreadable as input data, regardless of the logic levels at theoutput pin due to output loading; see Figure IS. When port Bis programmed for outputs, it is capable of sinking 10 rnA andsourcing 1 rnA on each pin.All input/output lines are TIL compatible as both inputsand outputs. Ports Band C are CMOS compatible as inputs.Port A is CMOS compatible as outputs. Figure 16 provides someexamples of port connections.Port C5 and C6 are also used for Timer 2.When Port C5 is used as Timer 2 Input Capture (IC), PortC5 's DDR should be cleared (Port C5 as input) and bit 4 (ICIM)in the Timer Control Register 2 (TCR2) should be cleared too.The Input Capture Register (ICR) stores the TDR2 when aPort C5 input transition occurs as defined by bit 1 (IDEG) ofthe TCR2.When Port C6 is used as Timer 2 Output Compare (OC),Port C6 's DDR should be set (Port C6 as output). When theOutput Compare Register (OCR) matches the TDR2, bit 0(OLVL) in the TCR2 is set and OLVL will appear at Port C6.Port C6 is writable by software. But the writing by software isunavailable when a match between the TDR2 and the OCR isfound at the same time.• INPUTPort D is usable as either TTL compatible inputs or a 4·channel input for an A/D converter. Figure 17 shows port Dlogic configuration.The Port D register at location $003 stores TTL compatibleinputs. When using as analog inputs for an A/D converter, referto A/D CONVERTER.Figure 15 Typical Port I/O CircuitryDataDirection Output Output Input toRegister Data Bit State MCUBit0 0 010 3·State Pin232 $ HITACHI

-----------------------------------------------------------------HD6805W1A.Port AA, ·Port BB,Port A Programmed as output(s), driving CMOS and TTL load directly.(a)Port B Programmed as output(s), driving Darlington base directly.(b)+v+vRPort BB,lOmA - maxPortCC. ·CMOS InverterPort B Programmed as output(s), driving LEO(s) directly.(c)Port C Programmed as output(s), driving CMOS loads, using externalpull-up resistors.(d)Figure 16 Typical Port Connections• AID CONVERTERThe HD6805WI has an internal 8-bit AID converter. TheAID converter, shown in Figure 18, includes 4 analog inputs(ANo to AN3), the Result Register (ADRR) and the ControlStatus Register (AOCSR).CAUTIONThe MCU has circuitry to protect the inputs against damagedue to high static voltages or electric field; however, the designof the input circuitry for the AID converter, ANo '" AN3, V RHand AVec, does not offer the same level of protection. Precautionsshould be taken to avoid applications of any voltagehigher than maximum-rated voltage or handled in any environmentproducing high-static voltages.$003 ReadInternal Bus.-...... ____ Port 0D. to OsDIA4~G>o~-0Analog Input

HD6805W11---------------------------------------------------------------• Analog Input (ANo to AN3)Analog inputs ANo to AN3 accept analog voltages of OVto 5V. The resolution is 8-bit (256 divisions) with a conversiontime of 76 I.ls at 1 MHz. Analog conversion starts selectinganalog inputs by bit 0 and bit 1 of the ADCSR analog input.Since the CPU is not required during conversion, other userprograms can be executed.ADCSRBit 1 Bit 0Table 7 Analog Input SelectionAnalog Input Signal0 0 ANo0 1 ANI1 0 AN21 1 AN3• AID Control Status Register (ADCSR: $OOE)The Control Status Register (ADCSR) is used to select ananalog input pin and confirm A/D conversion termination. Ananalog input pin is selected by bit 0 and bit 1 as shown in Table7.AID conversion begins when the data is written rnto bit 0and bit 1 of the ADCSR. When A/D conversion ends, bit 7(CEND) is set. Bit 7 is reset after the ADRR is read. Evenif bit 7 is set, A/D conversion execution still continues. To endthe A/D conversion, the A/D Result Register (ADRR) storesthe most current value. During A/D conversion execution, newdata is written into the ADCSR selecting the input channel andthe A/D conversion execution at that time is suspended. CENDis reset and new A/D conversion begins.• AID Result Register (ADRR: $OOF)When the AID conversion ends, the result is set in the A/DResult Register ($OOF). When CEND of the ADCSR is set,converted result is obtained by reading the ADRR. Furthermore,CEND is cleared.• ST ANDBV RAMThe portion from $020 to $027 of the RAM can be usedfor the standby RAM.When using the standby RAM, Vee Standby should remainabove V SBB(min) during powerdown. Consequently, power isprovided only to the standby RAM and STBY PWR bit of theRAM Control Register. 8 byte RAM is sustained with smallpower dissipation. The RAM including the standby RAM iscontrolled by the RAM Control Register (RCR) or RAME pin.~~:::;-;;;;;;-srr-~..JC...JRAM CTRLReg. (SOlFI• RAM Control Register (RCR: $01F)This register at location $01 F gives the status informationabout the RAM. When RAM Enable bit (RAME) is "0", theRAM is disabled. When Vee Standby is greater than V SBB,Standby Power bit (STBY PWR) is set and the standby RAM issustained during powerdown.$OlFSTBYPWA IRAM Control Register6 5 4 3 2 0AAME IBit 6 RAM EnableRAME bit is set or cleared by either software or hardware.When the MCU is reset, RAME bit is set and the RAM isenabled. If RAME bit is cleared, the user can neither read norwrite the RAM.When the RAM is disabled (logic "0"), the RAM address isinvalid.Bit 7 Standby bitSTBY PWR bit is cleared whenever Vee standby decreasesbelow VSB B (min). This bit is a read/write status bit that theuser can read. When this bit is set, it indicates that the standbypower is applied and data in the standby RAM is valid.• RAME SignalRAME bit in the RCR can be cleared when RAME pin goes"Low" by hardware (RAM is disabled). To make standby modeby hardware, set RAME pin "Low" during Vee Standbyremains above VSBB (min) artd powerdown sequence should beas shown in Fig. 20.When RAME pin gets "Low" in the powerup state, RAMEbit of the RCR is cleared and the RAM is disabled. Duringpowerdown, RAME bit is sustained by Vee Standby. WhenRAME pin gets "High" in the powerup state, RAME bit of theRCR is set and the RAM is enabled.RAME pin can be used to control the RAM externally withoutsoftware.VeeRAME pinRAM Enob" RAMO~~,t\ Vee OFF /rRAM(96BI~ ___-IS07FFigure 19 Standby RAM234 ~HITACHIFigure 20 RAM Control Signal (RAME)• BIT MANIPULATIONThe MeV has the ability to set or clear any single RAM orinput/output port (except the data direction registers) with asingie instruction (BSET and BCLR). Any bit in the page zeroread only memory can be tested by using the BRSET and

---------------------------------------------------------------HD6805WlBRCLR instructions, and the program branches as a result ofits state. This capability to work with any bit in RAM, ROM orI/O allows the user to have individual flags in RAM or to handlesingle I/O bits as control lines. The example in Figure 21 showsthe usefulness of the bit manipulation and test instructions.Assume that bit 0 of port A is connected to a zero crossingdetector circuit and that bit 1 of port A is connected to thetrigger of a TRIAC which powers the controlled hardware.This program, which uses only seven bytes of ROM providestum-on of the TRIAC within 14 microseconds of the zerocrossing. The timer is also incorporated to provide tum-on atsome later time which permits pulse-width modulation of thecontrolled power.•SELF 1Figure 21·BRClRO, PORTA, SELF 1BSET " PORTABClR " PORTA·Bit Manipulation Example• ADDRESSING MODESThe MCV has ten addressing modes available for use by theprogrammer. These modes are explained and illustrated brieflyin the following paragraphs.• ImmediateRefer to Figure 22. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 23. In direct addressing, the address of theoperand is contained in the secondbyte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage ofthis efficient memory addressing mode.• ExtendedRefer to Figure 24. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instructionsare three bytes long.• RelativeRefer to Figure 25. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA = (PC) +2 + ReI. ReI is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken, ReI = 0, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 bytes of the present instruction.These instructions are two bytes long.• Indexed (No Offset)Refer to Figure 26. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and their EA is the contents of the index register.• Indexed (8-bit Offset)Refer to Figure 27. The EA is calculated by adding the contentsof the byte following the opcode to the contents of theindex register. In this mode, 511 low memory locations areaccessable. These instructions occupy two bytes.• Indexed (16-bit Offset)Refer to Figure 28. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the eittire memory space may beaccessed. Instructions which use this addressing mode arethree bytes long.• Bit Set/ClearRefer to Figure 29. This mode of addreSSing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 30. This mode of addressing applies toinstructions which can test any bit in the rust 256 locations($00 through $FF) and branch to any location relative to thePC. The byte to be tested is addressed by the byte followingthe opcode. The individual bit within that byte to be testedis addressed by the lower three bits of the opcode. The thirdbyte is the relative address to be added to the program counterif the branch condition is met. These instructions are threebytes long. The value of the bit to be tested is written to thecarry bit in the condition code register.• ImpliedRefer to Figure 31. The implied mode of addressing hasno EA. All of the information necessary to execute an instructionis contained in the opcode. Direct operations on theaccumulator and the index register are included in this modeof addressing. In addition, control instructions such as SWIand RTl belong to this group. All implied addressing instructionsare one byte long.$ HITACHI 235

HD6805W1---------------------------------------------------------------IMemoryiIII~IPROG LOA #$F8 05BE A61------1058F F8IIAIndex e9IStack PointProg Count05COCCF8§IIIFigure 22 Immediate Addressing ExampleIIIIII~lEAMemory I004BiItIIAdderIICAT FCB 32 0048 20oloPROG LOA CAT 0520 B6I052E 48I/~IAJI20IIndex RegI IIStack PointI IIProg Count052FICC~IIIII :II, ,Figure 23 Direct Addressing Example236 ~HITACHI

---------------------------------------------------------------HD6805WliiiiMemoryi~0000IIA40PROG LOA CATIndex Reg040A M09~ 06040B E5 JStack PointIII I Prog CountCAT FeB 64 06E5 40 040CCCFigure 24 Extended Addressing ExampleMemoryii@PROG SEQ PROG2 04A 7 2704A8 18I0000AStack PointIndex Reg§I, I ,Figure 25 Relative Addressing Example_HITACHI 237

HD6805W1---------------------------------------------------------------MemoryTABl FCC t Lit 00B84C49A4CIndex RegB8PROG LOA XI~F'~§IStack PointProg Count05F5CCFigure 26 Indexed (No Offset) Addressing ExampleTABL FCB #BF 0089FCB #86 008AFCB #OB 008BFCB #CF 008CPROG LOA TABL. X 075B075CtJ EAMemory I008CJi IIitIIiIBFB6DBCFE689i§iIIAdder/ -~IIIA~J-.CFIIndex RegJ 03IStack PointIProg Count0750ICCII , I ,238Figure 27Indexed (S·Sit Offset) Addressing Example~HITACHI

-----------------------------------------------------------------HD6805WlPROGI•IMemory~IILOATABLX_2~0693 070694 7EIADBIndex Reg02Stack PointProg Count0695 _~ITABL FCB "BF 077E BFFCB :86 077F 86FCB ::OB 0780 DBFCB ::CF 0781 CFICCFigure 28 Indexed (16-Bit Offset) Addressing ExampleMemoryPORT B EQU 0001 BF0000AIndex RegPROG BCLR 6. PORT B 058F 100590 1---- 0- 1-----4Stack Point,Prog Count0591CC~• IIIII,Figure 29 Bit Set/Clear Addressing Example_HITACHI239 .

HD6805Wl-----------------------------------------------------------------PORT C EaU 2 0002PROG BRCLR 2. PORT C. PROG 2 057405750576MemlryiI,IFO,I,I050210I ,~, ,I/Bit200001 J~OR~~lEA0002JtAdder~i0000JAdder/IIAIIIStack PointIndex RegIIIProg Count0594IccIC IFigure 30 Bit Test and Branch Addressing ExampleMemoryI,IIPROGTAX~II05BA~AE5Index RegE5Prog Count05BBIICC~Figure 31Implied Addressing Example240~HITACHI

-------------------------------------------------------------HD6805W1• INSTRUCTION SETThe MeU has a set of 59 basic instructions. These instructionscan be divided into five different types; register/memory,read/modify/write, branch, bit manipulation and control. Eachinstruction is breifly explained below. All of the instructionswithin a given type are presented in individual tables.• RegisterlMemory InstructionsMost of these instructions use two operands. One operandis either the accumulator or the index register. The otheroperand is obtained from memory by using one of the addressingmodes. The jump unconditional (JMP) and jump to subroutine(JSR) instructions have no register operand. Refer toTable 8.• ReadlModify/Write InstructionsThese instructions read a memory location or a register,modify or test its contents and write the modified value backto the memory or register. The TST instruction for test ofnegative or zero is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table9.• Branch InstructionsThe branch instructional cause a branch from a programwhen a certain· condition is met. Refer to Table 10.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 256 bytesof the memory. One group either sets or clears. The othergroup performs the bit test and branch operations. Refer toTable II.• Control InstructionsThe control instructions control the MeU operations duringprogram execution. Refer to Table 12.• Alphabetical ListingThe complete instruction set is given in alphabetical orderin Table 13.• Opcode MapTable 14 is an opcode map for the instructions used on theMeU.~HITACHI 241

~ '"Table 8 Register/Memory Instructions:I:oa>(Xlo01~ .....Addressing ModesFunctionMnemonicImmediateOp # #Code Bytes CyclesDirectExtendedIndexed(No Offset)Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIndexed(8-Bit Offset)Op # #Code Bytes CyclesIndexed(16-Bit Offset)Op # #Code Bytes CyclesLoad A from MemoryLOAA6 2 2B6 2 4 C6 3 5 F6 1 4E6 2 506 3 6Load X from MemoryStore A in MemoryStore X in MemoryAdd Memory to ALOXSTASTXADDAE 2 2- - -- - -AB 2 2BE 2 4 CE 3 5 FE 1 4B7 2 5 C7 3 6 F7 1 5BF 2 5 CF 3 6 FF 1 5BB 2 4 CB 3 5 FB 1 4EE 2 5E7 2 6EF 2 6EB 2 5DE 3 607 3 7OF 3 7DB 3 6~%~():EAdd Memory andCarry to ASubtract MemorySubtract Memory fromA with BorrowAND Memory to AOR Memory with AAOCSUBSBCANDORAA9 2 2AO 2 2A2 2 2A4 2 2AA 2 2B9 2 4 C9 3 5 F9 1 4BO 2 4 CO 3 5 FO 1 4B2 2 4 C2 3 5 F2 1 4B4 2 4 C4 3 5 F4 1 4BA 2 4 CA 3 5 FA 1 4E9 2 5EO 2 5E2 2 5E4 2 5EA 2 509 3 6DO 3 602 3 604 3 6OA 3 6Exclusive OR Memorywith AEORA8 2 2B8 2 4 C8 3 5 F8 1 4E8 2 508 3 6Arithmetic Compare Awith MemoryCMPAl 2 2B1 2 4 C1 I 3 5 Fl 1 4E1 2 501 3 6Arithmetic Compare Xwith MemoryCPXA3 2 2B3 2 4 C3 3 5 F3 1 4E3 2 503 3 6Bit Test Memory with A(Logical Compare)Jump UnconditionalJump to SubroutineBITJMPJSRA5 2 2- - -- - -B5 2 4 C5 3 5 F5 1 4BC 2 3 CC 3 4 FC 1 3BO 2 7 CD 3 8 FD 1 7E5 2 5EC 2 4ED 2 805 3 6DC 3 5DO 3 9Symbols:Op: Operation Abbreviation# : Instruction Statement

Table 9Read/ModifylWrite InstructionsAddressing ModesFunctionMnemonicImplied (A) Implied (X) DirectOp # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIndexed(No Offset)Op # #Code Bytes CyclesIndexed(8·Bit Offset)Op # #Code Bytes CyclesIncrementINC4C 1 4 5C 1 4 3C 2 67C 1 66C 2 7DecrementDEC4A 1 4 5A 1 4 3A 2 67A 1 66A 2 7ClearClR4F 1 4 5F 1 4 3F 2 67F 1 66F 2 7-l:~();ComplementNegate(2's Complement)Rotate left Thru CarryRotate Right Thr\J CarryCOMNEGROlROR43 1 4 53 1 4 33 2 640 1 4 50 1 4 30 2 649 1 4 59 1 4 39 2 646 1 4 56 1 4 36 2 673 1 670 1 679 1 676 1 663 2 760 2 769 2 766 2 7logical Sh ift leftlSl48 1 4 58 1 4 38 2 678 1 668 2 7logical Shift RightlSR44 1 4 54 1 4 34 2 674 1 664 2 7Arithmetic Shift RightASR47 1 4 57 1 4 37 2 677 1 667 2 7Arithmetic Shift leftASl48 1 4 58 1 4 38 2 678 1 668 2 7Test for Negative orZeroTST40 1 4 5.0 1 4 3D 2 67D 1 660 2 7Symbols:Op: Operation Abbreviation# : Instruction Statement~(,.)Ia0>ex>o01~

HD6805W1---------------------------------------------------------------Table 10 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN- 21 2 4Branch IF Higher BHI 22 2 4Branch I F lower or Same BlS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch I Flower) (BlO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch IF Half Carry Clear BHCC 28 2 4Branch IF Half Carry Set BHCS 29 2 4Branch I F Plus BPL 2A 2 4Branch IF Minus BMI 2B 2 4Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch IF Interrupt Line is low Bil 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AD 2 8Symbols: Op: Operation Abbreviation #: Instruction StatementTable 11Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set BRSET n (n=O ..... 7) - - - 2-n 3 10Branch I F Bit n is clear BRClR n (n=O ..... 7) - - - 01+2-n ,3 10Set Bit n BSET n (n=O ..... 7) 10+2-n 2 7 - - -Clear bit n BClR n (n=O ..... 7) 11+2-n 2 7 - - -Symbols: Op: Operation Abbreviation #: Instruction StatementFunctionTable 12 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit ClC 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2- -Symbols: Op: Operation AbbreViation#: Instruction Statement244 ~HITACHI

---------------------------------------------------------------HD6805WlTable 13 Instruction SetAddressing ModesCondition CodeMnemonicIndexed Bit BitImme- Ex- Re-Indexed IndexedImpliedDirect(No~t/ Test & H I N Zdiatetended lative(8 Bits) (16 Bits)COffset) Clear BranchADC x x x x x x 1\ 1\ 1\ 1\ADD x x x x x x 1\ • 1\ 1\ 1\AND x x x x x x 1\ 1\ •ASL x x x x 1\ 1\ 1\ASR x x x x• • 1\ 1\ 1\BCC x• • • • •BCLR x• • • • •BCS x -. • • • •BEQ x • • • • •BHCC x• • • • •BHCS x• • • • •BHI x• • • • •BHS x• • • • •BIH x• • • • •BIL x• • • • •BIT x x x x x x• • 1\ 1\ •BLO x• • • • •BLS x• • • • •BMC x• • • • •BMI x• • • • •BMS x• • • • •BNE x• • • • •BPL x• • • • •BRA x • • • • •BRN x • • • • •BRCLR x• • • • 1\BRSET x 1\BSET x BSR x •CLC x • 0CLI x 0 • • CLR x x x x 0 1 •CMP x x x x x x 1\ 1\ 1\COM x x x x• • 1\ 1\ 1CPX x x x x x x• •1\ 1\ 1\DEC x x x x • • 1\ 1\ •EOR x x x x x x• • 1\ 1\ •INC x x x x• • 1\ " •JMP x x x x x• • • • •JSR x x x x x• • • • •LOA x x x x x x• • 1\" •LOX x x x x x x• •" 1\ •Condition Code Symbols:Ii Half Carry (From Bit 3) C Carry BorrowI Interrupt Mask1\ Test and Set if True, Cleared OtherwiseN . Negative (Sign Bit)• Not AffectedZ Zero(to be continued)~HITACHI 245

HD6805W1---------------------------------------------------------------MnemonicImpliedAddressing ModesImme- Ex- Re-Directdiatetended lativeTable 13 Instruction SetIndexed Bit Bit(No Indexed Indexed(8 Bits) (16 Bits)Set/ Test & HOffset) Clear BranchLSL x x x x•LSR x x x x•NEQ x x x x•NOP x•ORA x x x x x x •ROL x x x x •ROR x x x x •RSP x•RTI x ?RTS x •SBC x x x x x x•SEC x •SEI x •STA x x x x x •STX x x x x x•SUB x x x x x x •SWI x •TAX x•TST x x x x •TXA x •Condition Code Symbols:H Half Carry (From Bit 3) C Carry/BorrowI I nterrupt Mask /\ Test and Set if True. Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From StackCondition CodeIN• /\• 0• /\• •• /\• /\• /\• •? ?• •• /\• •1 •• /\• /\• /\1 •• •• /\• •ZC/\ /\/\ /\/\ /\• •/\ •/\ /\/\ /\• •? ?• •/\ /\• 1• •/\ •/\ •/\ /\• •• •/\ •• •Table 14 Opcode MapBit Manipu lation Brnch Read/Modify/Write Control Register IMemoryTest & SetlRei OIR A x .XlBranch Clear\\ \\ .XO IMP IMP IMM \ OIR \ EXT \ )(2 \ )(10 1 2 3 j 4 I 5 I 6 I 7 B 9 A I B I C I 0 I E0 BRSETO BSETO BRA NEO RTI' - SUB1 BRClRO BClRO BRN - RTS' - CMP2 BRSET1 BSET1 BHI - - - SBC3 BRClRl BClRl BlS COM SWI' - CPX4 BRSET2 BSET2 BCC lSR - - AND5 BRClR2 BClR2 BCS - - - BIT6 BRSET3 BSET3 BNE ROR - - lOA7 BRClR3 BClR3 BEQ ASR - TAX - I STA(+l)B BRSET4 BSET4 BHCC lSl/ASl - ClC EOR9 BRClR4 BClR4 BHCS ROl - SEC AOCA BRSET5 BSET5 BPl DEC - CLI ORAB BRClR5 BClR5 BMI - - SEI ADDC BRSET6 BSET6 BMC INC - RSP - I JMP(-l)o BRClR6 BClR6 BMS TST - NOP BSR" JSR(-3)E BRSET7 BSET7 Bil - - - lOXF BRClR7 BClR7 BIH ClR - TXA - ISTX(+lI3/10 217 2/4 2/6 , 1/4 I 1/4 I 217 I 1/6 1/' 1/2 2/2 I 2/4 I 3/5 13/6 1 2/5[NOTE) 1. Undefined opcodes are marked with "-".2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).Mnemonics followed by a "." require a different number of cycles as follows:RTI 9RTS 6SWillBSR 83. ( ) indicate that the number in parenthesis must be added to the cycle count for that instruction.246 $ HITACHI\.XOI F11/4~H IGH0123 l4 o5 W6789ABC0EF

HD6301 V1 ,HD63A01 V1 ,--­HD63B01V1CMOS MCU (Microcomputer Unit)The HD6301Vl is an 8-bit CMOS single-chip microcomputerunit. Object Code compatible with the 806801. 4kBROM. 128 bytes RAM. Serial Communication Interface (SCn,parallel I/O ports and multi function timer are incorporatedin the HD6301Vl. It is bus compatible with HMCS6800. Executiontime of key instructions are improved and severalnew instructions are added to increase system throughput.The HD6301Vl can be expanded up to 65k words. Like theHMCS6800 family. I/O level is TTL compatible with +5.0Vsingle power supply. As 8D6301Vl is fabricated by the advancedCMOS process technology, power dissipation is extremelyreduced. In addition to that. H0630 1 V 1 has Sleep Mode andStandby Mode at lower power dissipation mode. Thereforeflexible low power consumption application is possible.• FEATURES• Object Code Upward Compatible with HD6801 Family• Abundant On-Chip Functions Compatible with HD6801VO;4kB ROM, 128 Bytes RAM,29 Parallel I/O Lines, 2 Lines ofData Strobe, l6-bit Timer, Serial Communication Interface• Low Power Consumption Mode: Sleep Mode, Standby Mode• Minimum Instruction Execution Time1~s (f=lMHz), 0.67~s (f=1.5MHz), O.5~s (f=2MHz)• Bit Manipulation, Bit Test Instruction• Protection from System Upset: Address Trap, On-Code Trap• Up to 65k Words Address Space• Wide Operation RangeVcc=3 to 6V (f=O.1-

HD6301V1,HD63A01V1,HD63B01V1------------------------~-------------------• PIN ARRANGEMENT• HD6301V1P, HD63A01V1P,HD63B01V1Pose,se,p,.P"P"P"P,.P,.P,.P"p ..P.,2 p.,P.,p ..P ••P ••P.,p" --.... ______ ~ Vee(Top View)• BLOCK DIAGRAM• HD6301V1F, HD63A01V1F,HD63B01V1F(Top View)• HD6301V1CG,HD63A01V1CG,HD63B01V1CG~~J t;J L~J L~J ~;J ~~J t~J t~J ~~J L~jP3. f~ [~s P44PJO 3j]~~ P4SSCz 3~J (2) P4.SC, 3jJ[2j P41E {oj [~1 Vee1] [~ PHXTAL ~JEXTAL ~JNMI ~]IRQ, ~]r~l r,::.1 r~1 f;'l r§1 f::1 r~1 :-~l f:!i r~1_NM.,O _Nrra:o:tta: ~i'.(Top View).... -~+-Pzo~-r---4--+- PZI~+-r-"""'P2Z~+-~-PZ3PZ4248~HITACHI

-----------------------HD6301 Vl ,HD63AOl Vl ,HD63 801 Vl• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee -0.3 - +7.0 VInput Voltage Yin -0.3 - Vee+0.3 VOperating Temperature Topr 0- +70 °cStorage Temperature Tstg -55 -+150 °c(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.But be careful not to apply overvoltage more than maximum ratings to these high input impedance protectioncircuits. To assure the normal operation, we recommend Vin , Vout : Vss ~ (Vin or Vout) ~ Vee.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)Item Symbol Test Condition min typRES, STBY Vee-0.5 -Input "High" Voltage EXTAL V'H VeexO.7Other Inputs 2.0 -Input "Low" Voltage All Inputs V'L -0.3 - 0.8Input Leakage Current NM I, fRO"RES, STBY lI in I Yin =0.5-Vee-0.5V - - 1.0Three State (off-state) PlO-P17, P 20 -P 24 ,Leakage Current P 30 -P 37 , P 40 -P 4 7, ~Output "High" Voltage All Outputs VOH-maxVee+0.3IITs,1 Yin =0.5-Vee -O.5V - - 1.0IOH = -200p.A 2.4 - -IOH = -lOp.A Vee-0.7 - -Output "Low" Voltage All Outputs VOL IOL = 1.6mA - - 0.55Input Capacitance All Inputs CinVin=OV, f= 1.OMHz,Ta = 25°C- - 12.5Standby Current Non Operation Icc - 2.0 15.0Cu rrent Dissipation *IccOperating (f=l MHz**) - 6.0 10.0Sleeping (f=l MHz**) 1.0 2.0RAM Stand-By Voltage V RAM 2.0 - --UnitVVp.Ap.AVVVpFp.AmAV• V'H.min = vcc-1.OV. VIL max = O.8V•• Current Oissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max,values about Current Dissipations at f = x MHz operation are decided according to the following formula;typ, value (f = x MHz) = typ, value If = 1 MHz) x xmax. value (f = x MHz) = max, value (f = 1 MHz) x x(both the sleeping and operating)~HITACHI249

HD6301V1,HD63A01V1,HD63B01V1~~~~~~~~~~~~~~~~~~~~~~~• AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)BUS TIMINGTest HD6301Vl HD63A01Vl HD63B01VlItem Symbol Con- Unitdition min typ max min typ max min typ maxCycle Time t cvc 1 - 10 0.666 -. 10 0.5 - 10 JlSAddress Strobe Pulse Width"High"- - - - - nsPWASH 220 - 150 110Address Strobe Rise Time tASr - - 20 - - 20 - - 20 nsAddress Strobe Fall Time tASf - - 20 - - 20 - - 20 nsAd~ress Strobe Delay Time tASO 60 - - 40 - - 20 - - nsEnable Rise Time tEr - - 20 - - 20 - - 20 nsEnable Fall Time tEf - - 20 - - 20 - - 20 nsEnable Pulse Width "High" Level PWEH 450 - - 300 - - 220 - - nsEnable Pulse Width "Low" Level . PWEL 450 - - 300 - - 220 - - nsAddress Strobe to Enable DelayTimet ASEO60 - - 40 - - 20 - - nsAddress Delay Time ~ - - 250 - - 190 - - 160 nst A02 Fig. 1 - - 250 - - 190 - - 160 nsAddress Delay Time for Latch tAoL Fig. 2 - - 250 - - 190 - - 160 nsData Set-up TimeData Hold TimeWrite tosw 230 - - 150 - - 100 - - nsRead tOSR 80 - - 60 - - 50 - - nsRead tHR 0 - - 0 - - 0 - - nsWrite tHW 20 - - 20 - - 20 - - nsAddress Set-up Time for Latch tAS L 60 - - 40 - - 20 - - nsAddress Hold Time for Latch tAHL 30 - - 20 - - 20 - - nsAddress Hold Time tAH 20 - - 20 - - 20 - - nsAo - A, Set-up Time Before E tASM 200 - - 110 - - 60 - - nsI Non-MultiplexedPeripheral Read Bus(tACCN) - - 650 - - 395 - - 270 nsAccess Time I Multiplexed Bus (tACCM) - - 650 - - 395 - - 270 nsOscillator stabilization Time tRC Fig. 10 20 - - 20 - - 20 - - msProcessor Control Set-up Time tpcs Fig. 11 200 - - 200 - - 200 - - ns250PERIPHERAL PORT TIMINGPeripheral DataSet-up TimePeripheral DataHold TimeTest HD6301Vl HD63A01Vl HD63B01VlItem Symbol Con- Unitdition min typ max min typ max min typ maxPort 1, 2, 3,4 tposu Fig. 3 200 - - 200 - - 200 - - nsPort 1,2,3,4 tpOH Fig. 3 200 - -200 - - 200 - - nsDelay Time, Enable PositiveTransition to OS3 Negative 1oS01 Fig. 5 - - 300 - - 300 - - 300 nsTransitionDelay Time, Enable PositiveTransition to ~ Positive 1os02 Fig. 5 - - 300 - - 300 - - 300 nsTransitionDelay Time, Enable "091-1 Port 1tive Transition to Peri- 2* 3 4pheral Data Valid ' ,tpwo Fig. 4 - - 300 - - 300 - - 300 nsInput Strobe Pulse Width tpWIS Fig. 6 200 - - 200 - - 200 - - nsInput Data Hold Time 1 Port 3 tlH Fig. 6 150 - - 150 - - 150 - - nsInput Data Setup Time I Port 3 tiS Fig. 6 0 - - 0 - - 0 - - ns• Except P21~HITACHI

-----------------------HD6301V1,HD63A01V1,HD63B01V1TIMER, SCI TIMINGItemTimer Input Pulse WidthDelay Time, Enable PositiveTransition to Timer OutSCI Input Clock CycleSCI Input Clock Pulse WidthTest HD6301V1 HD63A01V1 HD63B01V1Symbol Conditionmin typ max min typ max min typ maxtpWTt TODt ScvctPWSCK2.0 - -Fig. 7 - - 4002.0 - -0.4 - 0.62.0 - - 2.0 - -- - 400 - - 4002.0 - - 2.0 - -0.4 - 0.6 0.4 - 0.6UnittcvcnstcvctScvcMODE PROGRAMMINGItemRES "Low" Pulse WidthMode Programming Set·up TimeMode Programming Hold TimeTest HD6301V1 HD63A01V1 HD63B01V1Symbol Conditionmin typ max min typ max min typ maxPW RSTLtMPstMPH3 - -Fig. 8 2 - -150 - -3 - - 3 - -2 - - 2 - -150 - - 150 - -UnittcvctcvcnsAdd,ess StrobeIASI2.4VEnablelEIR/Vii .Ar-A.ISC. IPo'141MCU W,ileD.-D"Ao··A,IPo,,31MCU Read0.-0.,. A.-A,IPo,,31~ NotValidFigure 1 Expanded Multiplexed Bus Timing_HITACHI251

HD6301Vl,HD63A01Vl,HD63B01Vl---------------------------------------------leyeEnoblolEIA. -A, ,Port 4)R/W ISC"iaS ISCdMCUWrite0,-0, ---+----~-----

~~~~~~~~~~~~~~~~~~~~~~-HD6301V1.HD63A01V1.HD63B01V1TimerCount.r ____ J '"--F;';';;"'~--' ___ _P"OutputI;-:~~:~~~:: )------{I~----..:If""Figure 8 Mode Programming TimingFigure 7 Timer Output TimingTe .. PO,nlm'11" .. ,,-rVeeRL =2.2kn 14.0kn fm EI1 I 152074@C =90pF for P30-P37, P.o-p", SC" SC,=30pF for P,o-P17 , P,o-P"=40pF for ER =12kQ for P,o-P17, P,o-P", PJO -P'I7, P.o-P", E, SC" SC,Figure 9 Bus Timing Test Loads (TTL Load)InterruptTestInternalAddress Bus __ "'-...... ____ "''"_-'----''---J''--J,--~-..J'. ...... _~ _ _'' ............ I ..... --'''''--....... r ...... -..r. ..... -,......NMI. IRQ" IRQ,..... --v-Internal --"\J'-~.r--"\J'-~.r---v'-~,---u""'-\.r-""""--\.r-",,,,"--...,..-_,"--...,..--u Data Bus __.I\.._..J"--.......""".......-J"--.......-".......--J"-.........J'._......."-_J''--.......,............ J''--_r.. ............I'\.,-_''-_..J'._.......'''-InternalReadInternalWrite______ -J!Figure 10 Interrupt SequenceE -..--u-u-t.,~_--!Is-----+-____ ~)---:.....i ---!!~~VeeV-~~-------~~--+-4-----------~!~~ ~C--4~~vee~~-5-V---------r-ve~e-~-.s-v---------~'·~ ~REs~)-1 _________.;~---J,~~;S_I ________::"er .... ,,)\\\\\\\\\\\\\\\\\\\\\\RNi ~\\\\\\\\\\\\\\\\\\\\\\\,~:-.. :\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\" I: ... ~.S-f -----­~'''n''I\WM\\\\\\\\\\\\\\\\\\\\\Figure 11Reset Timing~HITACHI 253

HD6301V1,HD63A01V1,HD63B01V1~~~~~~~~~~~~~~~~~~~~~~• FUNCTIONAL PIN DESCRIPTION• Vee, VssThese two pins are used for power supply and GND. Recommendedpower supply voltage is 5V ±10%. 3 to 6V canbe used for low speed operation (100 - 500 kHz).• XTAL, EXTALThese two pins are connected with parallel resonant fundamentalcrystal, AT cut. For instance, in order to obtain thesystem clock IMHz, a 4MHz resonant fundamental crystal isused because the devide by 4 circuitry is included. EXT ALaccepts an external clock input of duty 50% (±10%) to drive,then internal clock is a quarter the frequency of an externalclock. External' driving frequency will be less than 4 times asmaximum internal clock. For external driving, XTAL pinshould be open. An example of connection circuit is shown inFig. 12.AT Cut Parallel Resonance CrystalCo = 7 pF maxRs = 60 n maxXTAL~--~-----'CJEXTAL~-"""""(a) Crystal InterfaceXTALEXTALN.C.C L1 - C L2 -10-22pF ± 20%(32-8MHz)External Clock(b) External ClockFigure 12 Connection Circuit• Standby (STBY)This pin is used to place the MCU in the Standby mode.If this goes to "Low" level, the oscillation stops, the internalclock is tied to Vss or Vee and the MCU is reset. In order toretain information in RAM during standby, write "0" into RAMenable bit (RAME). RAME is bit 6 of the RAM Control Registerat address $0014. This disables the RAM, so the contents ofRAM is guaranteed. For details of the standby mode, see theStandby section.• Reset (RES)This input is used to reset the MCU. RES must be held"Low" for at least 20ms when the power starts up. It should benoted that, before clock generator stabilize, the internal stateand I/O ports are uncertain, becau'le MCU can not be resetwithout clock. To reset the MCU during system operation, itmust be held "Low" for at least 3 system clock cycles. Fromthe third cycle, all address buses become "High-impedance"and it continues while RES' is "Low". If RES goes to "High",CPU does the following.254 $ HITACHI(1) I/O Port 2 bits, 2,1,0 are latched into bits PC2, PCI, PCO ofprogram control register.(2) The contents of the two Start Addresses, $FFFE, $FFFFare brought to the program counter, from which programstarts (see Table I).(3) The interrupt mask bit is set. In order to have the CPUrecognize the maskable interrupts IRQ1 and IRQ:!, clear'it before those are used.• Enable (E)This output pin supplies system clock. Output is a singlephase,TTL compatible and 1/4 of the crystal oscillation frequency.It will drive two LS TTL load and 40pF.• Non maskable Interrupt (NM'i)When the falling edge of the input signal of this pin is recognized,NMI sequence starts. The current instruction is continuedto complete, eVfm if NMI signal is detected. Interruptmask bit in Condition Code Regist~r has no effect on NMIdetection. In response to NMI interrupt, the information ofProgram Counter, Index Register, Accumulators, and ConditionCode Register are stored on the stack. On completion of thissequence, vectoring address $FFFC and $FFFD are generatedto load the contents to the program counter. Then the CPUbranch to a non maskable interrupt service routine.• Interrupt Request (fROi)This level sensitive input requests maskable interrupt sequence.When lRQl goes to "Low", the CPU waits until itcompletes the current instruction that is being executed. Then,if the interrupt mask bit in Condition Code Register is not set,CPU begins interrupt sequence; otherwise, interrupt request isneglected.Once the sequence has started, the information of PwgramCounter, Index Register, Accumulators, Condition Code Registerare stored on the stack. Then the CPU sets the interruptmask bit so that no further maskable interrupts may be responded.Table 1 I nterrupt Vectoring memory mapHighestPriorityLowestPriorityVectorMS8 LS8FFFEFFEEFFFCFFFAFFF8FFFIFFF4FFF2FFFOFFFFFFEFFFFOFFF8FFF9FFF7FFF5FFF3FFFIInterruptAnTRAPNMISo''''.'. 'nte,rupt CSWIIiReS, Co, iSllICF CTimer InpUt Captu,.1OCF (1'i"., OutpUt ComP8reTOF CTi ..... Ove,"_1SCI CRORF. ORFE. TORE 1At the end of the cycle, the CPU generates 16 bit vectoringaddresses indicating memory addresses $FFF8 and $FFF9, andload the contents to the Program Counter, then branch to aninterrupt service routine.The Internal Interrupt will generate signal (IRQ:!) which isquite the same as IRQ1 except that it will use the vector address$FFFO to $FFF7.When IRQi and IRQ:! are generated at the same time, theformer precede the latter. Interrupt Mask Bit in the conditioncode register, if being set, will keep the both interrupts off.IRQt has no internal latch. Therefore, if IRQ1 is removedduring suspension, that IR'QI is ignored.

-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1On occurrence of Address error or Op-code error, TRAPinterrupt is invoked. This interrupt has priority next to RES.Regardless of the Interrupt Mask Bit condition, the CPU willstart an interrupt sequence. The vector for this interrupt will be$FFEE, $FFEF.The following pins are available only in single chip mode.Table 2 Port and Data Direction Register AddressesPortsPort AddressData Oi rectionRegister AddressI/O Port 1 $0002 $0000I/O Port 2 $0003 $0001I/O Port 3 $0006 $0004I/O Port 4 $0007 $0005• Input Strobe (lS3) (SCI)This signal controls IS3 interrupt and the latch of Port 3.When the falling edge of this signal is detected, the flag ofPort 3 Control Status Register is set.For detailed explanation of Port 3 Control Status Register,see the I/O PORT 3 CONTROL STATUS REGISTER section.• Output Strobe (OS3) (SC2 )This signal is used to send a strobe to an external device,indicating effective data is on the I/O pins. The timing chart forOutput Strobe are shown in Figure 5.The following pins are available for Expanded Modes.• Read/Write (R/W) (SC2)This TTL compatible output signal indicates peripheral andmemory devices whether CPU is in Read ("High"), or in Write("Low"). The normal stand-by state is Read ("High"). Itsoutput will drive one TTL load and 90pF.• I/O Strobe (lOS) (SCI)In expanded non multiplexed mode 5 of operation, lOSgoes to "Low" only when A9 through AI5 are "0" and As is"1" . This allows external access up to 256 addresses from$0100 to $01 FF in memory. The timing chart is shown inFigure 2.• Address Strobe (AS) (SCI)In the expanded multiplexed mode, address strobe signalappears at this pin. It is used to latch the lower 8 bits addressesmultiplexed with data at Port 3. The 8-bit latch is controlledby address strobe as shown in Figure 18. Thereby, I/O Port 3can become data bus during E pUlse. The timing chart of thissignal is shown in Figure 1.Address Strobe (AS) is sent out even if the internal addressarea is accessed.• PORTSThere are four I/O Ports on HD6301Vl MCU (three 8-bitports and one 5-bit port). 2 control pins are connected to oneof the 8-bit port. Each port has an independent write-only datadirection register to program individual I/O pins for input oroutput.*When the bit of associated Data Direction Register is "1".I/O pin is programmed for output, if "0", then programmed foran inpu.t.There are four ports: Port 1, Port 2, Port 3, and Port 4.Addresses of each port and associated Data Direction Registersare shown in Table 2.* Only one exception is bit 1 of Port 2 which becomes either adata input or a timer output. It cannot be used as an outputport.RE~ does not affect I/O port Data Register. Therefore, justafter RES, Data Register is uncertain. Data Direction Registersare reset.• I/O Port 1This is an 8-bit port, each bit being defined individually asinput or outputs by associated Data Direction Register. The8-bit output buffers have three-state capability, maintaining inhigh impedance state when they are used for input. In order tobe read accurately, the voltage on the input lines must be mOrethan 2.0V for logic "1" and less than 0.8 V for logic "0".These are TTL compatible. After the MCU has been reset, allI/O lines of Port 1 are configured as inputs in all modes exceptmode 1. In all modes except expanded non multiplexed mode(Mode 1), Port 1 is always parallel I/O. In mode I, Port 1 will beoutput line for lower order address lines (Ao to A7).• I/O Port 2This port has five lines, whose I/O direction depends on itsdata direction register. The 5-bit output buffers have three-statecapability, going high impedance state when used as inputs. Inorder to be read accurately, the voltage on the input lines mustbe more than 2.0V for logic "1" and less than 0.8V for logic"0". After the MCU has been reset, I/O lines are configured asinpu ts. These pins of Port 2 (pins P20, P2l , P22 of the chip) arcused to program the mode of operation during reset. The valuesof these three pins during reset are latched into the upper 3 bits(bit 7, 6 and 5) of Port 2 Data Register, which is explained inthe MODE SELECTION section.In all modes, Port 2 can be configured as I/O lines. This portalso provides access to the Serial I/O and the Timer. However,note that bit 1 (P21) is the only pin restricted to data input orTimer output.• I/O Port 3This is an 8-bit port which can be configured as I/O lines, adata bus, or an address bus multiplexed with data bus. Itsfunction depends on hardware operation mode programmed bythe user using 3 bits of Port 2 during Reset. Port 3 as a data busis bi-directional. For an input from peripherals, regular TTLlevel must be supplied, that is greater than 2.0V for a logic" 1"and less than O.8V for a logic "0". This TTL compatible threestatebuffer can drive one TTL load and 90pF. In the expandedModes, data direction register will be inhibited after Reset anddata direction will depend on the state of the R/W line. Functionof Port 3 is shown below.Single Chip Mode (Mode 7)Parallel Inputs/Outputs as programmed by its correspondingData Direction Register.There are two control lines associated with this port in thismode, an input strobe (IS5) and an output strobe (053), bothbeing used for handshaking. They are controlled by I/O Port 3Control/Status Register. Function of these two control lines ofPort 3 are summarized as follows:(1) Port 3 input data can be latched using IS3 (SCI) as ainput strobe signal.(2) 0S3 can be generated by CPU read or write to Port 3'sdata register.(3) IRQ! interrupt can be generated by an ID fallingedge.~HITACHI 255

HD6301V1,HD63A01V1,HD63B01V1~~~~~~~~~~~~~~~~~~~~~~Port 3 strobe and latch timing is shown in Figs. 5 and 6respectively.I/O Port 3 Control/Status Register is explained as follows:I/O Port 3 Control/Status Registerport becomes inputs. In order to use these pins as addresses,they should be programmed as outputs. When all of the eightbits are not required, the remaining lines can be used as I/Olines (input only).Expanded Multiplexed Mode (Mode 0,2,4): In this mode, Port4 becomes output for upper order address lines (As to A15)regardless of the value of data direction register.Bit 0 Not ulld.Bit 1 Not ulld_Bit 2 Not used.Bit 3 LATCH ENABLE.Bit 3 is used to control the input latch of Port 3. If the bit isset at "I", the input data on Port 3 is latched by the falling edgeof ~. The latch is released by the MCU read to Port 3; nownew data can be latched again by iS3 falling edge. Bit 3 iscleared by a reset. If this bit is "0", IS3 does not affect I/OPort 3 latch operation.Bit 4 OSS (Output Strobe Select)This bit ideritifies the ca1,lse of output strobe generation: awrite operation or read operation to I/O Port 3. When the bit iscleared, the strobe will be generated by a read operation to Port3. When the bit is not cleared, the strobe will be generated by awrite operation. Bit 4 is cleared by a reset.Bit 5 Not used.Bit 6 1I31RQ1 ENABLE.If this bit is set, IROt interrupt by IS3 Flag is enabled.Otherwise the interrupt is disabled. The bit is cleared by areset.Bit 7TH FLAG.Bit 7 is a read-only bit which is set by the falling edge of IS3(SCI). It is cleared by a read of the Control/Status Register followedby a read/write of I/O Port 3. The bit is cleared by rese·t.Expanded Non Multiplexed Mode (mode 1,5)In this mode, Port 3 becomes data bus. (Do'" D7)Expanded Multiplexed Mode (mode 0, 2, 4, 6)Port 3 becomes both the data bus (Do '" D7) and lower bitsof the address bus (Ao '" A7). An address strobe output is "High"while the address is on the port.• I/O Port 4This is an 8-bit port that becomes either I/O or addressoutputs depending on the selected operation mode. In orderto be read accurately, the voltage at the input lines must begreater than 2.0V for a logic" 1", and less than 0.8V for a logic"0". For outputs, each line is TTL compatible and can drive oneTTL load and 90pF. Function of Port 4 for each mode isexplained below.Single Chip Mode (Mode 7): Parallel Inputs/Outputs as programmedby its associated data direction register.Expanded Non Multiplexed Mode (Mode 5): In this mode,Port 4 becomes the lower address lines (Ao to A7) by writing"1"s on the data direction register. After reset, this portbecomes inputs. In order to use these pins as addresses, theyshould be programmed as outputs.When all of the eight bits are not required as addresses, theremaining lines can be used as I/O lines (Inputs only).Expanded Non Multiplexed Mode (Mode 1): In this mode, Port4 becomes output for upper order address lines (As to Al 5)regardless of the value of the direction register.Expanded Multiplexed Mode (Mode 6): In this mode, Port 4becomes the upper address lines (As to AlS). After reset, this256 ~HITACHIThe relation between each mode and I/O Port 1 to 4 issummarized in Table 3.• MODE SELECTIONThe operation mode after the reset must be determined bythe user wiring the P20, P2l and P22 pins externally. These threepins are lower order bits; I/O 0, I/O 1, I/O 2 of Port 2. They arelatched into the control bits PCO, PC 1, PC2 of I/O Port 2 registerwhen reset goes "High". I/O Port 2 Register is shown below.Port 2 DATA REGISTER4 1$00031 ~21 ~1 I PCO 1"0411/0311/0211/0 1 1110 0 IAn example of external hardware used for Mode Selection isshown in Fig. 13. The HD14053B is used to separate the peripheraldevice from the MCU during reset. It is necessary ifthe data may conflict between peripheral device and Modegeneration circuit.No mode can be changed through software because the bits5, 6, and 7 of Port 2 Data Register are read-only. The modeselection of the HD6301Vl is shown in Table 4.The HD630 1 V 1 operates in three basic modes: (1) SingleChip Mode; (2) Expanded Multiplexed Mode (compatible withthe HMCS6800 peripheral family), (3) Expanded Non MultiplexedMode (compatible with HMCS6800 peripheral family).• Single Chip Mode (Mode 7)In the Single Chip Mode, all ports will become I/O. This isshown in Figure 15. In this mode, SCI, SC2 pins are configuredfor control lines of Port 3 and can be used as input strobe (IS3)and output strobe (OSJ) for data handshaking.• Expanded Multiplexed Mode (Mode 0, 2. 4, 6)In this mode, Port 4 is configured for I/O (inputs only) oraddress lines. The data bus and the lower order address bus aremultiplexed in Port 3 and can be separated by the AddressStrobe.Port 2 is configured for 5 parallel I/O or Serial I/O, or Timer,or any combination thereof. Port 1 is configured for 8 parallelI/O. In this mode, HD630I VI is expandable up to 65k words(See Fig. 16).• Expanded Non Multiplexed Mode (Mode 1.5)In this mode, the HD630 I VI can directly address HMCS6800peripherals with no external logic. In mode 5, Port 3 becomes adata bus. Port 4 becomes Ao to A 7 address bus or partialaddress bus and I/O (inputs only). Port 2 is configured for aparallel I/O, Serial I/O, Timer or any combination thereof.Port 1 is configured as a parallel I/O only.In this mode, HD630IVI is expandable to 256 locations.In mode 1, Port 3 becomes a data bus and Port I becomesAo to A7 address bus, and Port 4 becomes A8 to Ais addressbus.

-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1In this mode, the HD6301Vl is expandable to 65k wordswith no extemallogic. (See Fig. 17)• lower Order Address Bus latchBecause the data bus is multiplexed with the lower orderVeeaddress bus in Port 3 in the expanded multiplexed mode,address bits must be latched. It requires the 74LS373 Trans·parent octal D·type to latch the LSB. Latch connection ofthe HD6301Vl is shown in Figure 18.RR, R, R,p,. -0+--+-+--+------1P".P" -+--+--i-+---4HD6301Vl.I-----l p,. (PCOII-----l P" (Pcn1-----lP" (PC21Note 1) Figure of Mode 72) RC"'Reset Constant3) R, =10knFigure 13 Recommended Circuit for Mode SelectionTruth TableControl InputSelectInhIbItC B A0 0 0 00 0 0 10 0 1 00 0 1 1x0 1 0 00 1 0 1yy,~------------------~~~--~0 1 1 0Zoo----------------------*~--~0 1 1 1zZ,o-----------------------~~~ 1 X X XInhABCOn SWItchHD1405JBZ. Y. X.Z. Y. X,Z. Y, X.Z •. Y, X,ZI Y" XoZ, Y. X,Z, Y, X.Z. VI XI..Figure 14 HD140538 Multiplexers/De·MultiplexersVeeVeeEnablePort 18 LinesPort 1 Port 38110 Lines Multiplelled8 I/O Lines 81/0 LinesData/Add,essPo,t 2 Po,t 451/0 LinesPort 4 Port 28 Address81/0 Lines 5 I/O Lines SCI Lines 0,Tim.,SCI8 I/O LinesTimer(Inputs Only)vssVssFigure 15 HD6301V1 MCU Single·Chip ModeFigure 16 HD6301V1 MCU ExpandedMultiplexed Mode$ HITACHI 257

HD6301V1,HD63A01Vl,HD63B01V1---------------------------------------------VeeVeePort 18 Parallel I/OPort 38 Data LinesPort 1To 8 Address LinesPort 38 Data LinesPort 25 Parallel I/OSCITimer(a) Mode 5Port 48 AddressLines or8 I/O Lines(Inputs OnlylPort 25 Parallel I/OSCITimerVss(b) Mode tPort 48 AddressLinesGNOASFigure 17 HD6301V1 MCU Expanded Non Multiplexed ModedG OC0, 0,POri 3 [ 74LS373) A",_A,-A,Address/Data0, 0,!II1) D ... D,-D,OutputControl(oelLLLHFunction TableEnableG 0H HH LL XX XOutPUt0HLC.ZFigure 18 Latch Connection• Summary of Mode and MCU SignalThis section gives a description of the MeU signals for thevarious modes. Sf I and Sf 2 are signals which vary with the mode.Table 3 Feature of each mode and linesMODEPORT 1 PORT 2 PORT 3 PORT 4Eight Lines Five Lines Eight Lines Eight LinesSINGLE CHIP (Mode 7) I/O I/O I/O 1/0-_._--ADDRESS BUSEXPANDED MUX(Ao-A7) ADDRESS BUS·I/O I/O(Mode 0, 2,4,6) DATA BUS (Ae-Als)(00-07)I DATA BUS ADDRESS BUS·EXPANDED ! (Mode 5) i I/O I/O(00-07) (Ao-A7)ADDRESS BUSNON·MUXDATA BUS ADDRESS BUSi (Mode 1) I/O: (Ao-A7) (00-07) I (Ae-Als)"These lines can be substituted for I/O (Input Only) (except Mode 0, 2,4)I Input 153 = Input Strobe SC = Strobe Controlo Output OS3 = Output Strobe AS = Address StrobeA/W AeadlWrite lOS = I/O Select258 ~HITACHIISCIIS3 (I)AS(O)10S(0)Not UsedSCzOS3(0)R/W(O)R/W(O)R!W(O)

---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1Table 4 Mode Selection SummaryModeI~~~) l~tlll I~l:'b)ROM RAMInterruptVectorsBusMode7 H H H I I I I6 H H L I I I MUX(4)5 H L H I I I NMUX(4)4 H L L EI21 1111 E MUX3 L H H - - - -2 'L H L E(2) 1(1) E MUX1 L L H E(2) I E NMUX0 L L L I I 1131 MUXOperatingModeSingle ChipMultiplexed/Partial DecodeNon·Multiplexed/Partial DecodeMultiplexed/RAMNot UsedMultiplexed/RAMNon-MultiplexedMultiplexed TestLEGEND:·(NOTES)I -Ihternal 1) Internal RAM is addressed at $0080.E - External 2) Internal ROM is disabled.MUX - Multiplexed3) Reset vector is external for 3 or 4 cycles afterNMUX - Non·MultiplexedRES goes "high",L - Logic "0"4) Idle lines of Port 4 address outputs canH - Logie "1"be assigned to I nput Port.• MemoryMapThe MCU can provide up to 65k byte address spacedepending on the operating mode. Fig, 19 shows a memory mapfor each operating mode. The first 32 locations of each map arefor the MCU's internal register only. as shown in Table 5.Table 5 Internal Register AreaRegisterPort 1 Data Direction Register· .. •Port 2 Data Direction Register····Port 1 Data RegisterPort 2 Data RegisterPort 3 Data Direction Register····Port 4 Data Direction Register ••••Port 3 Data RegisterPort 4 Data RegisterTimer Control and Status RegisterCounter (High Byte)Counter (Low Byte)Output Compare Register (High Byte)Output Compare Register (Low Byte)Input Capture Register (High Byte)Input Capture Register (Low Byte)Port 3 Control and Status RegisterRate and Mode ContrOl RegisterTransmit/Receive Control and Status RegisterReceive Data RegisterTransmit Data RegisterRAM ContrOl RegisterReservedAddress00·0102·0304··05·'·06··07···OB09OAOBoc00OEOF"1011121314lS'lF• External address in Mode 1External address in Modes 0, 1, 2,4, 6; cannot beaccessed in Mode 5External address in Modes 0, 1,2,41 = Output, 0 = Input~HITACHI259

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------HD6301V10ModeHD6301V1 1ModeMultiplexed Test mode$0000(1)Internal Registers$001FExternal Memory Space$0080Internal RAM$OOFFNon-Multiplexed. Partial Decode$0000Internal Registers$001FExternal Memory Space$0080Internal RAM$ooFFExternal Memory SpaceExternal Memory Space$FOOOInternal ROM$FFFF(2)$F FF F '-----~)(NOTES]1) Excludes the following addresses which may beused externally: $04, $05, $06, $07 and $OF.2) Addresses $FFFE and $FFFF are conSideredexternal If accessed within 3 or 4 cycles after apositive edge of RES and internal at all other times.3) After 3 or 4 CPU cycles, there must be no overlappingof internal and external memory spaces to avoiddriving the data bus with more than one device.4) This mode is the only mode which is used fortesting.(NOTE]Excludes the following addresses which may beused externally; $00, $02, $04, $05, $06, $07and $OF.(to be continued)Figure 19 HD6301V1 Memory Maps260_HITACHI

-----------------------H 0630 1 V 1 ,H D63AO 1 V 1 ,HD63 BO 1 V1HD6301V12ModeHD6301Vl.J1Mode ..HD6301V15ModeMultiplexed/RAM$0000Internal Registers$OOlFExternal Memory Space$0080Internal RAM$OOFFNon-Multiplexed/Partial Decode$0000$OOlF$0080$OOFF$0100}$01 F F L-_.,...._~} Internal Registers} Internal RAMExternal Memory SpaceExternal Memo~y Space$FOOO$FFFF '-____ )$FFFFInternal ROMInternal Interrupt Vectors[NOTE)Excludes the following address whichmay be used externally; $04, $05, $06,$07, $OF_[NOTE)Excludes $04, $06, $OF.These address cannot be usedexternally.(to be continued)Figure 19 HD6301Vl Memory Maps~HITACHI261

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------HD6301V16ModeHD6301V17ModeMultiplexed/Partial DecodeSingle Chip$0000$001F$0080$OOFFInternal RegistersExternal Memory SpaceInternal RAM$0000S001F$0080$OOFFInternal Registers} Internal RAMExternal Memory SpaceSF 000$FOOOSFFFF]Internal ROMInternal Interrupt Vectors$FFFFInternal ROMInternal Interrupt Vectors(NOTE)Excludes the following address which may beused externally: $04. $06. $OF.Figure 19 HD6301V1 Memory Maps262_HITACHI

~~~~~~~~~~~~~~~~~~~~~~-HD6301V1.HD63A01V1.HD63B01V1• PROGRAMMABLE TIMERThe HD6301Vl contains 16-bit programmable timer whichmay be used to make measurement of input waveform. Inaddition to that it can generate an output waveform by itself.For both input and output waveform, the pulse width may varyfrom a few microseconds to several seconds.The timer hardware consists of• an 8-bit control and status register• a 16-bit free running counter• a 16-bit output compare register, and• a 16-bit input capture registerA block diagram of the timer is shown in Figure 20.iiiQ,HD6301V1 Internal BusBit 1Port 2DDR____ j~~:pu~-I:putLevelBit 1EdgeSitOPort 2 Port 2Figure 20 Programmable Timer Block Diagram• Free Running Counter ($0009: $OOOA)The key element in the programmable timer is a 16-bit freerunning counter, that is driven by an E (Enable) clock toincrement its values. The counter value will be read out by theCPU software at any time with no effects on the counter.Reset will clear the counter.When the MSB of this counter is read, the LSB is storedin temporary latch. The data is fetched from this latch by thesubsequent read of LSB. Thus consistent double byte data canbe read from the counter.When the CPU writes arbitrary data to the MSB ($09), thevalue of $FFF8 is being pre-set to the counter ($09, $OA)regardless of the write data value. Then the CPU writes arbitrarydata to the LSB ($OA), the data is set to the "Low" byteof the counter, at the same time, the data preceedingly writtenin the MSB ($09) is set to "High" byte of the counter.When the data is written to this counter, a double bytestore instruction (ex. STD) must be used. If only the MSB ofcounter is written, the counter is set to $FFF8.The counter value written to the counter using the doublebyte store instruction is shown in Figure 21.To write to the counter may disturb serial operations, so itshould be inhibited during using the SCI in internal clock mode.(SAF3 written to the counter)Figure 21Counter Write Timing• Output Compare Register ($OOOB:$OOOC)This is a 16-bit read/write register which is used to control anoutput waveform. The contents of this register are constantlybeing compared with current value of the free running counter.When the contents match with the .value of the free runningcounter, a flag (OCF) in the timer control/status register(TCSR) is set and the current value of an output level Bit(OLVL) in the TCSR is transferred to Port 2 bit 1. When bit 1of the Port 2 data direction register is "I" (output), the OLVLvalue will appear on the bit I of Port 2. Then, the value of OutputCompare Register and Output level bit may be changedfor the next compare.The output compare register is set to $FFFF during reset.The compare function is inhibited at the cycle of writingto the high byte of the output compare register and at thecycle just after that to ensure valid compare. It is also inhibitedin same manner at writing to the free running counter.In order to write a data to Output Compare Register, adouble byte store instruction (ex. STD) must be used.• Input Capture Register ($OOOD:$OOOE)The input capture register is a 16-bit read-only register usedto hold the current value of free running counter when theproper transition of an external input signal occurs.The input transition change required to trigger the countertransfer is controlled by the input edge bit (IEDG).To allow the external input signal to go in the edge detectunit, the bit of the Data Direction Register corresponding to bito of Port 2 must have been cleared (to zero).To insure input capture in all cases, the width of an inputpulse requires at least 2 Enable cycles.• Timer Control/Status Register (TCSR) ($0008)This is an 8-bit register. All 8 bits are readable and the lower5-bit may be written. The upper 3 bits are read-only, indicatingthe timer status information as is shown below.(1) A proper transition has been detected on the input pin(ICF).(2) A match has been found between the value in the freerunning counter and the output compare register (OCF).(3) When counting up to $0000 (TOF).Each flag has an individual enable bit in TCSR whichdetermines whether or not an interrupt request mayoccur (IRQ2). If the I-bit in Condition Code Register hasbeen cleared, a priority vectored address occurs correspondingto each flag. A description of each bit is as follows.Timer Control I Status Register76543210I,CF I OCF I TOF I EICI I EOCI I ETOIIIEOG I OLVLI s0008Bit 0OLVL (Output Level); When a match is found in thevalue between the counter and the output com-~HITACHI 263

HD6301Vl,HD63A01Vl,HD63B01Vl~~~~~~~~~~~~~~~~~~~~~~Bit 1Bit 2Bit 3pare register, this bit is transferred to the Port 2bit 1. If the DDR corresponding to Port 2 bit 1 isset" 1", the value will appear on the outpu t pin ofPort 2 bit 1.IEDG (Input Edge): This bit control which transitionof

~~~~~~~~~~~~~~~~~~~~~~-HD6301V1,HD63A01V1,HD63B01V1Bit 6TORE (Transmit Data Register Empty); When the datais transferred from the Transmit Data Registerto Output Shift Register, this bit is set by hardware.The bit is cleared by reading the status registerfollowed by writing the next new data intothe Transmit Data Register. TDRE is initializedto 1 by RES.ORFE (Over Run Framing Error); When overrun orframing error occurs (receive only), this bit is setby hardware. Over Run Error occurs if the attemptis made to transfer the new byte to the receivedata register while the RDRF is "1". FramingError occurs when the bit counter is not synchronizedwith the boundary of the byte in the receivingbit stream. When Framing Error is detected,RDRF is not set. Therefore Framing Errorcan be distinguished from Overrun Error. That is,if ORFE is "1" and RDRF is "1 ", Overrun Erroris detected. Otherwise Framing Error occurs.The bit is cleared by reading the status registerfollowed by reading the receive data register, orbyRES.Bit 7 RDRF (Receive Data Register Full); This bit is set byhardware when the data is transferred from thereceive shift register to the receive data register.It is cleared by reading the status register followedby reading the receive data register, or by RES.Bit 7 Rate and Mode Control Register Bit 0I I CCI I ceo I 551 I 550 IS10Transmit/Receive Control and Status RegisterPo", 2Receive Shift RegisterClOCk 10Bit .... --=..!:.-------..2.... ------E~-----------------Figure 22 Serial I/O Register6 5 4 3 ox x I CCl CCO SSl SSO AD DR : $0010Transfer Rate 1 Mode Control RegisterTable 6 SCI Bit Times and Transfer RatesXTAL 2.4576 MHz 4.0 MHz 4.9152MHzSS1 : SSO E 614.4 kHz 1.0MHz 1.2288MHz0 0 E+ 16 26 115/38,400 8aud 16 115/62,500 Baud 13 I's/76,800Baud0 1 E + 128 2oe,..s/4,8oo 8aud 128 115/1812.5 Baud 104.21'sl 9,600Baud1 0 E + 1024 1.67ms/600 Baud 1.024ms/976.6 8aud 833.31'51 1,200Baud1 1 E + 4096 6.67ms/150 Baud 4.096ms/244.1 Blud 3.333ms/ 300Baud~HITACHI 265

HD6301Vl,HD63A01Vl,HD63B01Vl~~~~~~~~~~~~~~~~~~~~~~-Table 7SCI Format and Clock Source ControlCC1:CCO Format Clock Source0 0 - I -0 1 NRZ Internal1 0 NRZ Internal1 1 NRZ External• Clock output is available regardless of values for bits RE and TE .•• Bit 3 is used for serial input if RE = "1" in TRCS.Bit 4 is used for serial output if TE = "1" in TRCS.*** This pin can be used as I/O port.Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4- - -Not Used *** .. ..Output· .. ..Input .. . • Transfer rate/Mode Control Register (RMCR)The register controls the following serial I/O functions:• Bauds rate ·data format • clock source• Port 2 bit 2 featureIt is 4-bit write-only register, cleared by RES. The 4 bits areconsidered as a pair of 2-bit fields. The lower 2 bits control thebit rate of internal clock while the upper 2 bits control theformat and the clock select logic.Bit 0 SSO}Bit 1 SS1 Speed SelectThese bits select the Baud rate for the internal clock. Therates selectable are function of E clock frequency of the CPU.Table 6 lists the available Baud Rates.Bit2 CCO }Bit 3 CCI Clock Control/Format SelectThey control the data format and the clock select logic.Table 7 defines the bit field.• Internally Generated ClockIf the user wish to use externally an internal clock of theserial I/O, the following requirements should be noted.·CCl, CCO must be set to "10".• The maximum clock rate must be E/16.• The clock rate is equal to the bit rate.• The values of RE and TE have no effect.• Externally Generated ClockIf the user wish to supply an external clock to the SerialI/O, the following requirements should be noted.• The CC 1, CCO must be set to "11" (See Table 7).• The external clock must be set to 8 times of the desiredbaud rate.• The maximum external clock frequency is E/2 clock.• Serial OperationsThe serial I/O hardware must be initialized by the softwarebefore operation. The sequence will be normally as follows.• Writing the desired operation control bits of the Rate andMode Control Register.·Writing the desired operation control bits of the TRCSregister.If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may bekept set. When TE, RE bit are cleafed during SCI operation,and subsequently set again, it should be noted that TE, REmust be kept "0" for at least one bit time of the current baudrate. If TE, RE are set again within one bit time, there may bethe case where the initializing of internal function for transmitterand receiver does not take place correctly.• Transmit OperationData transmission is enabled by the TE bit in the TRCSregister. When set, the output of the transmit shift registeris connected with Port 2 bit 4 which is unconditionally configuredas an output.After RES, the user should initialize both the RMC registerand the TRCS register for desired operation. Setting the TE bitcauses a transmission of ten-bit preamble of" 1 "s. Following thepreamble, internal synchronization is established and the transmitteris ready to operate. Then either of the following statesexists.(1) If the transmit data register is empty (TDRE = 1), theconsecu tive "l"s are transmitted indicating an idlestates.(2) If the data has been loaded into the Transmit DataRegister (TDRE = 0), it is transferred to the outputshift register apd data transmission begins.During the data transfer, the start bit ("0") is first transferred.Next the 8-bit data (beginning at bit 0) and finally thestop bit ("1 "). When the contents of the Transmit Data Registeris transferred to the output shift register, the hardware sets theTDRE flag bit: If the CPU fails to respond to the flag withinthe proper time, TDRE is kept set and then a continuous stringof 1 's is sent until the data is supplied to the data register.• Receive OperationThe receive operation is enabled by the RE bit. The serialinput is connected with Port 2 bit 3. The receiver operationis determined by the contents of the TRCS and RMC register.The received bit stream is synchronized by the first "0" (startbit); During 10-bit time, the data is strobed approximately atthe center of each bit. If the tenth bit is not "1" (stop bit),the system assumes a framing error and the ORFE is set.If the tenth bit is "1 ", the data is transferred to the receivedata register, and the RDRF flag is set. If the tenth bit of thenext data is received and still RDRF is preserved set, thenORFE is set indicating that an overrun error has occurred.After the CPU read of the status register as a response toRDRF flag or ORFE flag, followed by the CPU read of thereceive data register, RDRF or ORFE will be cleared.• RAM CONTROL REGISTERThe register assigned to the address $0014 gives a statusinformation about standby RAM.RAM Control Register85430~'41 s~ IRAMEI x I x I x I x I x x IBit 0 Not used_Bit 1 Not used.Bit 2 Not used.266 ~HITACHI

----------------------HD6301 V1 ,HD63AO 1 V1, HD63 B01 V1Bit 3 Not used.Bit 4 Not used.Bit 5 Not used.Bit 6 RAM Enable.Using this control bit, the user can disable the RAM. RAMEnable bit is set on the positive edge of RES and RAM isenabled. The program can write "I" or "0". If RAME iscleared, the RAM address becomes external address and theCPU may read the data from the outside memory.Bit 7 Standby BitThis bit can be read or written by the user program. It iscleared when the Vee voltage is removed. Normally this bitis set by the program before going into stand-by mode. Whenthe CPU recovers from stand-by mode, this bit should bechecked. If it is "I ", the data of the RAM is retained duringstand-by and it is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD630lVI has an upward object code compatible withthe HD6801 to utilize all instruction sets of the HMCS6800.The execution time of the key instruction is reduced to increasethe system through-put. In addition, the bit operation instruction,the exchange instruction between the index and theaccumulator, the sleep instruction are added. This sectiondescribes:• CPU programming model (See Fig. 23)• Addressing modes• Accumulator and memory manipulation instructions (SeeTable 8)• New instructions• Index register and stack manipulation instructions (SeeTable 9)• Jump and branch instructions (See Table 10)• Condition code register manipulation instructions (SeeTable II)·Op-code map (See Table 12)• Cycle-by-Cycle Operation (See Table 13)• CPU Programming ModelThe programming model for the HD6301VI is shown in Figure23. The double accumulator is physically the same as theaccumulator A concatenated with the accumulator B, so thatthe contents of A and B is changed with executing operation ofan accumulator D.t ----A ____ 1J~ ____ ~ ____ ~18.8it Accumulators A and B15 D . 0 Or 16·B,t Double Accumulator D• CPU Addressing ModesThe HD630 I V I has seven address modes which depend onboth of the instruction type and the code. The address mode forevery instruction is shown along with execution time given interms of machine cycles (Table 8 to 12). When the clockfrequency is 4 MHz, the machine cycles will be microseconds.Accumulator (ACCX) AddressingOnly the accumulator (A or B) is addressed. Either accumulatorA or B is specified by one-byte instructions.Immediate AddressingIn this mode, the operand is stored in the second byte of theinstruction except that the operand in LDS and LDX, etc arestored in the second and the third byte. These are two orthree-byte instructions.Direct AddressingIn this mod~, the ~econd byte of instruction indicates theaddress where the opel.md is stored. Direct addreSSing allowsthe user to directly address the lowest 256 Bytes in the machinelocations zero through 255. Improved execution times areachieved by storing data in these locations. For systemconfiguration, it is recommended that these locations should beRAM and be utilized preferably for user's data realm. These aretwo-byte instructions except the AIM, OIM, ElM and TIMwhich have three- byte.Extended AddressingIn this mode, the second byte indicates the upper 8 bitsaddresses where the operand is stored, while the third byteindicates the lower 8 bits. This is an absolute address inmemory. These are three-byte instructions.Indexed AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the Index Register. For each of AIM, OIM, ElMand TIM instructions, the contents of the third byte are addedto the lower 8 bits in the Index Register. In addition, theresulting "carry" is added to the upper 8 bits in the IndexRegister. The result is used for addressing memory. Because themodified address is held in the Temporary Address Register,there is no change to the Index Register. These are two-byteinstructions but AIM, OIM, ElM, TIM have three-byte .Implied AddressingIn this mode, the instruction itself gives the address; stackpointer, index register, etc. These are I-byte instructions.Relative AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the program counter. The resulting carry orborrow is added to the upper 8 bits. This helps the user toaddress the data within a range of - 126 to + 129 bytes of thecurrent execution instruction. These are two-byte instructions.11'1 '51 '51 '5 XSPPCo II ndex Register (X)o I Stack Pointer (SP)7 001 Program Counter (PC)H I N Z V C Condition Code Register (CCR)Carry/Borrow from MSBOverflowZeroNegativeInterruptHalf Carry (From Bit 3)Figure 23 CPU Programming Model~HITACHI 267

HD6301 V1 ,HD63A01 V1 ,HD63B01 V1Table 8 Accumulator, Memory Manipulation InstructionsAddressing ModesOper.tions Mnemonic BooleanlIMMED DIRECT INDEX EXTEND IMPLIED Arithmetic OperationCondition CodeRegister5 4 3 2 1 0'OP - It OP - It OP - It OP - It OP - It H I N Z V CAdd ADDA 8B 2 2 9B 3 2 AB 4 2 B8 4 3 A+M-A t e t t t tADOB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B t e t t t tAdd Doable AOOO C3 3 3 03 4 2 E3 5 2 F3 5 3 A:B+M:M+l-A:B e t t t tAdd Accumul.to,s ABA lB 1 1 A+ B- A t· t t t tAdd With Carry AOCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A t ; t t tAOCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-B t t t I tAND ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A,M-A t t R ANOB C4 2 2 04 3 2 E4 4 2 F4 4 3 B,M-B t t R Bit Test BIT A 85 2 2 95 3 2 A5 4 2 B5 4 3 A'M J I R BIT 8 C5 2 2 05 3 2 E5 4 2 F5 4 3 B'M · ·t t R Cle., CLR 6F 5 2 7F 5 3 OO-M S R R·RCLRA 4F 1 1 OO-A R S R RCLRB 5F 1 1 00 -8 R S R RComp.,e CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3 A-M t t t ICMPB Cl 2 2 01 3 .2 El 4 2 Fl 4 3 8-M I I I ICompe,eCeA 11 1 1 A-BAccumul8torst t t tCompliment,l's COM 63 6 2 73 6 3 M-M t t R SCOMA 43 1 1 A -A t I R SCOMB 53 1 1 B -B I t R SComplement, 2's NEG 60 6 2 70 6 3 OO-M-M t I (j)~(Negate' NEGA 40 1 1 OO-A-A I I \~,~ ~2)NEGB 50 1 1 00-8-B t t (I) ';I,Converts bInary add of BCDDecim.1 Adjust, A DAA 19 2 1 cheracters Into BCD formatt I t ~)Decrement DEC SA 6 2 7A 6 3 M-l -M t t (o!) •OECA 4A 1 1 A -1-A t I (4) •OECB 5A 1 1 B-l-B t I (4) •Exclusive OR EORA 88 2 2 98 3 2 AS 4 2 B8 4 3 A(!) M-A I t REORB C8 2 2 08 3 2 E8 4 2 FB 4 3 B (!)M- B I t R ·Increment INC 6C 6 2 7C 6 3 M+l-M I I . ~INCA 4C 1, A + 1 - A I t ($) •INCB 5C 1 1 B + 1- B t t @ •Load LOAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-A I t RAccumul.torLOAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M-B t t R Load DoubleLDD CC 3 3 DC 4 2 ec 5 2 FC 5 3 M + 1- B, M- A I I RAccumul.to,· ·Multiply Unsigned MUL 30 7 1 A.B-A:B·OR, Inclusive ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+M-A·DRAB CA 2 2 OA 3 2 EA 4 2 FA 4 3 B + M- B·Push O.t. PSHA 36 4 1 A - Msp, SP - 1 - SP·PSHB 37 4 1 B - Msp, SP - 1 - SP·Pull O.t. PULA 32 3 1 SP + 1 - SP, Msp - A·PULB 33 3 1 SP + 1 - SP, Msp - B·Rot.te L.ft ROL 69 6 2 79 6 3ROLA 49 1 1·ROLB 59 1 1Rot.te Right ROR 66 6 2 76 6 3RORA 46 1 1·RORB 56 1 1Note) Condition Code Register will be explained in Note of Table ",·· t • @I R t t R ··· t @· · tt:j C9i I I ! ! I I nOl t t @ t• 1i7 IiO t t @ It t (j) t:j Gi?1! I ! ! ! ! ! P t t (ij I• b7 bOt t jj t·· (to be continued)268 ~HITACHI

-----------------------HD6301V1,HD63A01V1,HD63B01V1Table 8 Accumulator, Memory Manipulation InstructionsOperationsMnemonicAddressing ModesIMMEO DIRECT INDEX EXTEND IMPliEDBooleanlArithmetic OperationCondition CodeRegister5 4 3 2 1 0OP- "OP - "OP- "OP - "OP - "H I N Z V CShift Left ASL 68 6 2 78 6 3M} _ · · , ,

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------Table 9 Index Register, Stack Manipulation InstructionsPOInter OperatIons MnemoniCCondition CodeAddressIng ModesBooleanlRegisterIMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V C·Compare Index Reg CPX 8C 3 3 9C 4 2 AC 5 2 BC 5 3 X-MM+l---c-- -- - --- -~Decrement Index Reg DEX'091 1 X -1- X--~ ---,Decrement Stack Pntr DES-.- .34 1 1 SP-l-SPIncrement Index Reg INX 1-- 08 '1 --------- X + 1 - X""INs' 31 1 1 sP+l-SP·· : l · : ll l ··· (j) l R J; l R ·····Increment Stack Pntrload Index Reg lOX CE "- "'3 --.. 3 DE - i-' 4 - :2 EE 5 2 FE 5 3 M - XH.IM + 11- XL • III· l Rload Stack Pntr lOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M- sPH.IM+lI-SP LStore Inde.. Reg STX OF 4 2 EF 5 2 FF 5 3 XH - M. XL -1M + 11 ---- f-I-- --Store Stack Pntr STS 9F 4 2 AF 5 2 BF 53 SPH - M,SP L -IM+ 11 (t l RIndex Reg - Stack Pntr TXS 35 1 1 X-l-SP ··Stack Pntr - Index Reg TSX 30 1 1 SP + 1 - XAdd ABX 3A 1 1 B + X- XPush Data PSHX 3C 5 1 XL - Mil>' SP - 1 - SPXH - Mil>' SP - 1 - SPPull Data PUlX 38 4 1 SP + 1 - SP. Mil> - X HSP + 1 - SP. Mil> - XLExchange XGDX 18 2 1 ACCD .. IX• • • • • •Note) Condition Code Register will be explained in Note of Table 11.OperationsMnemonicTable 10 Jump, Branch InstructionAddressing ModesRELATIVE DIRECT INDEX EXTEND IMPLIEDBranch TestCondItion CodeRegister5 4 3 2, 0OP- - # OP # OP - # OP - - # OP # H I N Z V CBranch Always BRA 20 3 2 NoneBranch Never-BRN --f-:213 2 None Branch If Carry Clear BCC--- 24 3 2 c=o Branch If Carry Set BCS 25 3 2 C = ,Branch If - Zero BEQ 27 3 2 Z - 1 Branch If .. Zero BGE 2C 3 2 N (!) V- 0Brench If > Zero BGT 2E 3 2 Z + (N ® VI - 0 Branch If Higher BHI 22 3 2 C+Z-O Branch If < Zero BlE 2F 3 2 Z + (N (!) VI - ,Branch If lower OrBlSSame23 3 2 C+Z-'i-- - ----c-'Branch If < Zero BlT 20 3 2 N (!) V -,--Branch If Minus BMI 2B 3 2 N -, Branch If Not EqualZeroBNE 26 3 2 z=o Branch If OverflowClearBVC 28 3 2 v-oBranch If Overflow Set BVS 29 3 2 V -I--Branch If Plus BPl 2A 3 2 N-O Branch To Subroutine BSR 80 5 2 Jump JMP 6E 3 2 7E 3 3Jump To Subroutine JSR 90 5 2 AD 5 2 80 6 3 No Operation NOP 01Advances Prog. Cntr.1 1Only······Return From Interrupti RTI 3B 10 1 --@ --Return FromSubroutineRTS J9 5 1· Softwere Interrupt SWI 3F 12 1 SWait for Interrupt" WAI 3E 9 1 (j).· · · · ·Sleep SlP tA 4 t• • • • • •Note) 'WAI ~~ts R/W hIgh; Address Bus goes to FFFF; Data Bus goes to the three state.CondItIon Code Register will be explained in Note of Table 11.270 ~HITACHI

~~~~~~~~~~~~~~~~~~~~~~-HD6301V1,HD63A01V1,HD63B01V1Table 11Condition Code Register Manipulation Instructions]AddressingMOde!Condition Code RegisterOperetions Mnemonic IMPLIED Boolean Operation 5 4 3 2 1 0OP - "H I N Z V CCINt Carry CLC OC 1 O-CClelr Intlrrupt Mask CLI OE , , 0-1 ·CMrOverflow CLV OA 1 1 O-V·SetCllrry SEC 00 1 l-CSet Intlrrupt Mask SEI OF 1, , -I· Set Owrflow SEV OB 1 1 1 -V·• RR R SS · S · · · · ·Accumul.tor A - CCR TAP 06 , 1 A_ CCR --- III ---CeR - Accumulator A TPA 07 , 1 CCR-A·[NOTE 11 Condition Code Register Notes: (Bit set if test is true and cleared otherwise)(D (Bit V) Test: Result = 100000007~ (Bit C) Test: Result \ OOOOOOOO?@ (Bit C) Test: BCD Character of high~rder byte greater than 97 (Not cleared if previously set)@ (Bit V) Test: Operand = 10000000 prior to execution?@ (Bit V) Test: Operand = 01111111 prior to execution?@ (Bit V) Test: Set equal to NeC=1 after the execution of instructionsiJ) (Bit N) Test: Result less than zero? (Bit 15=1)@ (All Bit) Load Condition Code Register from Stack.@ (Bit II Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the waitstate.@l (All Bit) Set according to the contents of Accumulator A.@ (Bit C) Result of Multiplication Bit 7= 1 of ACCB?[NOTE 21 CLI instructions and interrupt. ____If interrupt mask-bit is set (1="1") and interrupt is requested (lRQI = "0" or IRQ2 = "0")"and then CLI instruction is executed, the CPU responds as follows.1 the next instruction of CLI is one-machine cycle instruction.Subsequent two instructions are executed before the interrupt is responded.That is, the next and the next of the next instruction are executed.2 the next instruction of CLI is two-machine cycle (or more) instruction.Only the next instruction is executed and then the CPU jump to the interrupt routine.Even if TAP instruction is used, instead of CLI, the same thing occurs.0010 2 ~ ~---------Table 12 OP-Code MapI~OPACC ACCACCA or SPACCB or XINOCODEA B OIR IMM I OIR liND I EXT IMM -r OIR liND I Exi-0000 0001 0010 0011 0100 0101 0110 0111 10001 1001 1 1010 I 1011 1100 I 1101 I~---II 10_tl IIILO 0 I 2 3 4 5 6 7 8 I 9 I A i B C ! 0 'E -F--0000 O~ SBA BRA TSX NEG SUB00001 I NOP CBA BRN INS I AIM CMPIBHI PULA DIM sac20011 3 ~ ~ BlS PUlB COM SUBO AD 0030100 4 lSRO ~ BCC DES LSR AND40101 5 ASlO BCS TXS __ I_EI~ BIT5f-----.0110 6 TAP TAB BNE PSHA ROR lOA , 60111 7 TPA TBA BEQ PSHB ASR ...-/1 STA ~ STA 71000 8 INX XGOX BVC PUlX ASl EOR I 81001 9 OEX OAA BVS RTS ROL AOC 91010 A ClV SlP BPl ABX DEC ORA ATIM ADD s-1100 C ClC ./" BGE PSHX INC CPX LOO C1101 0 SEC ~ BlT MUl TST BSR I JSR ...-/1 STO 0lOll B SEV ABA BMI RTI----1110 E CLI ~ BGT WAI ~~ JMP lOS lOX E1111 F SEI ~ BlE SWI ClR ~l STS ...........-I STX F0 I '1 3 4 5 6 7 8 I 9 I A 1 B C I o I E i FUNDEFINED OP CODE ~* Only for instructions of AIM, OIM, ElM, TIM~HITACHI 271

HD6301V1,HD63A01Vl,HD63B01Vl---------------------------------------------• I nstruction Execution CyclesIn the HMCS6800 series, the execution cycle of each instructionis the number of cycles between the start of thecurrent instruction fetch and just before the start of the subsequent instruction fetch.The HD6301Vl uses a mechanism of the pipeline controlfor the instruction- fetch and the subsequent instructionfetch is performed during the current instruction being exe-cuted.Therefore, the method to count instruction cycles used inthe HMCS6800 series cannot be applied to the instruction cyclessuch as MULT, PULL, DAA and XGDX in the HD6301Vl.Table 13 provides the information about the reillionshipamong each data on the Address Bus, Data Bus, and R/W statusin cycle-by-cycle basis during the execution of each instruction.Address Mode &InstructionsTable 13 Cycle-by-Cycle OperationAddress BusData BusIMMEDIATEADC ADDAND BITCMP EORLOA ORASBC SUBADDD CPXLDD LOSLOX SUBD2II1213 23Op Code Address+ 1 1 Operand DataOp Code Address+2 1 Next Op CodeOp Code Address+ 1 1 Operand Data (MSB)Op Code Address+2 1 Operand Data (LSB)Op Code Address+3 1 Next Op CodeDIRECTADCANDCMPLOASBCSTAADDDLDDLOXSTDSTXJSRTIMAIMOIMADDBITEORORASUBCPXLOSSUBDSTSElM123 313 2317243412434125 345124341236456Op Code Address+ 1 1 Address of Operand (LSB)Address of Operand 1 Operand DataOp Code Address+2 1 Next Op CodeOp Code Address + 1 1 Destination AddressDestination Address 0 Accumulator DataOp Code Address+2 1 Next Op CodeOp Code Address+ 1 1 Address of Operand (LSB)Address of Operand 1 Operand Data (MSB)Address of Operand + 1 1 Operand Data (LSB)Op Code Address+2 1 Next Op CodeOp Code Address+ 1 1 Destination Address (LSB)Destination Address 0 Register Data (MSB)Destination Address+ 1 0 Register Data (LSB)Op Code Address + 2 1 Next Op CodeOp Code Address + 1 1 Jump Address (LSB)FFFF 1 Restart Address (LSB)Stack Pointer 0 Return Address (LSB)Stack Pointer-1 0 Return Address (MSB) ,Jump Address 1 First Subroutine Op CodeOp Code Address + 1 1 Immediate DataOp Code Address+2 1 Address of Operand (LSB)Address of Operand 1 Operand DataOp Code Address + 3 1 Next Op CodeOp Code Address+ 1 1 Immediate DataOp Code Address + 2 1 Address of Operand (LSB)Address of Operand 1 Operand Data·FFFF 1 Restart Address (LSB)Address of Operand 0 New Operand DataOp Code Address+3 1 Next Op Code- Continued -272~HITACHI

~~~~~~~~~~~~~~~~~~~~~~HD6301V1,HD63A01V1,HD63B01V1Table 13 Cvcle~v-Cvcle Operation (Continued)Address Mode &InstructionsAddress BusData BusINDEXEDJMPADCANDCMPLOASBCTSTSTAADDDCPXLOSSUBDSTDSTXJSRASLCOMINCNEGRORTIMCLRAIMOIMADDBITEORORASUBLDDLOXSTSASRDECLSRROLElM34455565571 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)3 Jump Address 1 First Op Code of Jump Routine1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data4 Op Code Address + 2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 0 Accumulator Data4 Op Code Address + 2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data (MSB)4 IX+Offset+ 1 1 Operand Data (LSB)5 Op Code Address + 2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 0 Register Data (MSB)4 IX+Offset+ 1 0 Register Data (LSB)5 Op Code Address+2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer - 1 0 Return Address (MSB)5 IX + Offset 1 First Subroutine Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 . Restart Address (LSB)3 IX + Offset 1 Operand Data4 FFFF 1 Restart Address (LSB)5 IX + Offset 0 New Operand Data6 Op Code Address + 1 1 Next Op Code1 Op Code Address + 1 1 Immediate Data2 Op Code Address + 2 1 Offset3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 Op Code Address + 3 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data4 IX + Offset 0 005 Op Code Address + 2 1 Next Op Code1 Op Code Address + 1 1 Immediate Data2 Op Code Address + 2 1 Offset3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 FFFF 1 Restart Address (LSB)6 IX + Offset 0 New Operand Data7 Op Code Address + 3 1 Next Op Code- Continued -~HITACHI 273

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusEXTENDJMPADC ADD TSTAND BITCMP EORLOA ORASBC SUBSTAADDDCPXLOSSUBD-STDSTXJSRASLCOMINCNEGRORCLRLDDLOXSTSASRDECLSRROLi344I 556651 Op Code Address + 1 1 Jump Address (MSB)2 Op Code Address + 2 1 Jump Address (LSB)3 Jump Address 1 Next Op Code1 Op Code Address + 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 Op Code Address + 3 1 Next Op Code1 Op Code Address+ 1 1 Destination Address (MSB)2 Op Code Address+2 1 Destination Address (LSB)3 Destination Address 0 Accumulator Data4 Op Code Address+3 1 Next Op Code1 Op Code Address+ 1 1 Address of Operand (MSB)2 Op Code Address + 2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data (MSB)4 Address of Operand + 1 1 Operand Data (LSB)5 Op Code Address+3 1 Next Op Code1 Op Code Address+ 1 1 Destination Address (MSB)2 Op Code Address+2 1 Destination Address (LSB)3 Destination Address 0 Register Data (MSB)4 Destination Address + 1 0 Register Data (LSB)5 Op Code Address+3 1 Next Op Code1 Op Code Address+ 1 1 Jump Address (MSB)2 Op Code Address+2 1 Jump Address (LSB)3 FFFF 1 Restart Address (LSB)4 Stack Pointer 0 Return Address (LSB)5 Stack Pointer - 1 0 IReturn Address (MSB)6 Jump Address 1 First Subroutine Op Code1 Op Code Address + 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 FFFF 1 Restart Address (LSB)5 Address of Operand 0 New Operand Data6 Op Code Address + 3 1 Next Op Code1 O.p Code Address+ 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 Address of Operand 0 005 Op Code Address + 3 1 Next Op Code- Continued -274~HITACHI

-----------------------HD6301V1,HD63A01V1,HD63B01V1Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusIMPLIEDABA ABXASL ASLDASR CBACLC CLICLR CLVCOM DECDES DEXINC INSINX LSRLSRD ROLROR NOPSBA SECSEI SEVTAB TAPTBA TPATST TSXTXSDAA XGDXPULAPULB..PSHA PSHBPULXPSHXRTSMUL12344557I1 Op Code Address + 1 1 Next Op Code1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (lSB)1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (lSB)3 Stack Pointer + 1 1 Data from Stack1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (lSB)3 Stack Pointer 0 Accumulator Data4 Op Code Address + 1 1 Next Op Code1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (lSB)3 Stack Pointer + 1 1 Data from Stack (MSB)4 Stack Pointer + 2 1 Data from Stack (LSB)1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (lSB)3 Stack Pointer 0 Index Register (LSB)4 Stack Pointer - 1 0 Index Register (MSB)5 Op Code Address + 1 1 Next Op Code1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer + 1 I 1 Return Address (MSB)4 Stack Pointer + 2 1 Return Address (LSB)5 Return Address 1 First Op Code of Return Routine1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 FFFF 1 Restart Address (LSS)4 FFFF 1 Restart Address (LSB)5 FFFF 1 Restart Address (LSB)6 FFFF 1 Restart Address (LSS)7 FFFF 1 Restart Address (LSB)- Continued -I----.. -~HITACHI 275

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusIMPLIEDWAIRTISWISLP9101241 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer-1 0 Return Address (MSB)5 Stack Pointer - 2 0 Index Register (LSB)6 Stack Pointer - 3 0 Index Register (MSB)7 Stack Pointer-4 0 Accumulator. A8 Stack Pointer - 5 0 Accumulator B9 Stack Pointer - 6 0 Conditional Code Register1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer 1 Conditional Code Register4 Stack Pointer + 1 1 Accumulator B5 Stack Pointer+2 1 Accumulator A6 Stack Pointer + 3 1 Index Register (MSB)7 Stack Pointer+4 1 Index Register (LS8)8 Stack Pointer + 5 1 Return Address (MSB)9 Stack Pointer + 6 1 Return Address (LSB)10 Return Address 1 First Op Code of Return Routine1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer - 1 0 Return Address (MSB)5 Stack Pointer - 2 0 Index Register (LSB)6 Stack Pointer - 3 0 Index Register (MSB)7 Stack Pointer - 4 0 Accumulator A8 Stack Pointer - 5 0 Accumulator B9 Stack Pointer - 60 Conditional Code Register10 Vector Address FFFA I 1 Address of SWI Routine (MSB)11 Vector Address FFFB ! 1 Address of SWI Routine (LSB)12 Address of SWI Routine 1 First Op Code of SWI Routine1 Op Code Address+ 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)FFFFHigh Impedance-Non MPX Mod erAddress Bus -MPX ModeSleep13 FFFF Restart Address (LSB)4 Op Code Address + 1 Next Op Code1- Continued -276$ HITACHI

---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusRELATIVEBCC BCS 1 Op Code Address+ 1 ! 1 Branch OffsetBEQ BGE 3 2 FFFF 1 Restart Address (LSB)BGT BHIi Branch Address······Test= I First Op Code of Branch Routine3 "'"1BLE BLS Op Code Address+ '···Test="O·· Next Op CodeBLT BMTBNE BPLBRA BRNBVC BVS----------_1.. -BSR 1 00 Code Add.ess+ 1, Offset2 FFFF 1 Restart Address (lSB)5 3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer - ,I 0 Return Address (MSB)5 Branch Address 1 I First Op Code of Subroutine• LOW POWER CONSUMPTION MODEThe HD630 I VI has two low power consumption modes; sleepand standby mode.• Sleep ModeOn execution of SLP instruction, the MCU is brought to thesleep mode. In the sleep mode, the CPU sleeps (the CPU clockbecomes inactive), but the contents of the registers in the CPUare retained. In this mode, the peripherals of CPU will remainactive. So the operations such as transmit and receive of theSCI data and counter may keep in operation. In this mode,the power consumption is reduced to about 1/6 the value ofa normal operation.The escape from this mode can be done by interrupt, RES,STBY. The RES resets the MCU and the STBY brings it into thestandby mode (This will be mentioned later). When interrupt isrequested to the CPU and accepted, the sleep mode is released,then the CPU is brought in the operation mode and jumps tothe interrupt routine. When the CPU has masked the intenupt,after recovering from the sleep mode, the next instruction ofSLP starts to execute. However, in such a case that the timerinterrupt is inhibited on the timer side, the sleep mode cannotbe released due to the absence of the interrupt request to theCPU.This sleep mode is available to reduce an average powerconsumption in the applications of the HD630lVI which maynot be always running .• Standby ModeBringing 'STBY "Low", the CPU becomes reset and allclocks of the HD630IVI become inactive. It goes into thestandby mode. This mode remarkably reduces the power con·sumptions of the HD6301 VI.In the standby mode, if the HD630 I VI is continuouslysupplied with power, the contents of RAM is retained. Thestandby mode should escape by the reset start. The followingis the typical application of this mode.First, NMI routine stacks the MCU's internal information andthe contents of SP in RAM, disables RAME bit of RAM controlregister, sets the Standby bit, and then goes into the standbymode. If the Standby bit keeps set on reset start, it meansthat the power has been kept during standby mode and thecontents of RAM is normally guaranteed. The system recoverymay be possible by returning SP and bringing into the conditionbefore the standby mode has started. The timing relation foreach line in this application is shown in Figure 24.VeeHD6301V1~------~Irl----~r-I !-------if r--:I ~:I I I~"Stack registers,. RAM conlrolregIster setFigure 24 Standby Mode Timing~HITACHI 277

HD6301V1,HD63A01V1,HD63B01V1~~~~~~~~~~~~~~~~~~~~~~• ERROR PROCESSINGWhen the HD6301Vl fetches an undefined instruction orfetches an instruction from unusable memory area, it generatesthe highest priority internal interrupt, that may protect fromsystem upset due 10 noise or a program error.• Op-Code ErrorFetching an undefined op-code, the HD6301Vl will stack theCPU register as in the case of a normal interrupt and vector tothe TRAP (SFFEE, SFFEF), that has a second highest priority(RES is the highest). .• Addr .. ErrorWhen an instruction is fetched from other than a residentROM, RAM, or an external memory area, the CPU starts thesame interrupt as op-code error. In the case which the instructionis fetched from external memory area and that area is notusable, the address error cannot be detected.The addresses which cause address error in particular modeare shown in Table 14.This feature is applicable only to the instruction fetch, not tonormal read/write of data accessing.Table 14 Address ErrorMode 0 1 2,4 5 6 7SOOOO SOOOO SOOOO SOOOO SOOOO SOOOOI I I I I IAddress SOOIF SOOIF SOOIF SOO7F SOOIF 'OO7FS0200SOIOOISEFFFISEFFFSystem Flow chart of HD6301 VI is shown in Fig. 25.Transitions among the active mode, sleep mode, standbymode and reset are shown in Fig. 26.Figures 27, 28, 29 and 30 shows a system configuration.278 ~HITACHI

-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1PCl ~ MSPPCH -< Msp·lIXL < MSP·2IXH· MSP·3ACCA ·MSP·4ACCB • MSP·5CCR • MSP·6Figure 25 HD6301Vl System Flow Chart~HITACHI279

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------Figure 26 Transitions among Active Mode, Standby Mode,Sleep Mode, and ResetVeeveeRESPort 181/0Lonesc:JEnableNMIIRO,POrt 38 TransferLinesEnableNMIiJm",Port 181/0 LinesPOrt 48110 LinesPort 2 Port 25110 Lines 5110 LinesSCISCIPort 481/0 LinesVssvssFigure 27 HD6301V1 MCU Single-Chip Dual Processor Configuration280~HITACHI

-----------------------HD6301V1,HD63A01V1,HD63B01V1=HD6301VlMCUAddressBusDataBus Address Bus Data BusFigure 28 HD6301V1 MCU Expanded Non-Multiplexed Mode(Mode 5)Figure 29HD6301 V1 MCU Expanded Multiplexed ModeHD6301Vl MCU16 8Address BusData BusFigure 30 HD6301V1 MCU Expanded Non-Multiplexed Mode (Mode 1)~HITACHI 281

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------• PRECAUTION TO THE BOARD DESIGN OF OSCILLA­TION CIRCUITAs shown in Fig. 31, there is a case that the cross talk disturbsthe normal oscillation if signal lines are put near theoscillation circuit. When designing a board, pay attention tothis. Crystal and C L must be put as near the HD6301 VI aspossible.~ ~ii iic: c:01 01~ inCL IJ7i ............_....;....-(.1 XT ALt-

---------------------- HD6301V1,HD63A01V1,HD63B01V1Table 16 Pin Condition during RESET~e0,2,4,6pm1 5 7Port 1high impedance (input) .. .. ..PIO '" PI7Port 2high impedance (input) .. .. ..P20'" P24Port 3E: "1" outputhigh impedanceP30 '" P37E: high impedance• ..Port 4high impedance (input) .. .. ..P40 '" P47SC2(RM)"1" output (Read) .. .. "1" outputSCIE: "1" output..(AS)"1" outputE: "0" outputhigh impedance (input)~HITACHI 283

HD6301 XO ,HD63A01 XO ,-­HD63B01XOCMOS MCU (Microcomputer Unit)-PRELIMINARY-The HD630lXO is a CMOS Single-chip microcomputer unit(MCU) which includes it CPU compatible with the HD630lVl,4k bytes of ROM, 192 bytes of RAM, 53 parallel I/O pins, aSerial Communication Interface (SCI) and two timers on chip.HD6301 XOP, HD63A01 XOP;HD63B01XOP• FEATURES• Instruction Set Compatible with the HD6301V1• Abundant On-chip Functions4k Bytes of ROM, 192 Bytes of RAM53 Parallel I/O Ports16-Bit Programmable TimerB·Bit Reloadable TimerSerial Communication InterfaceMemory ReadyHaltError·Detection (Address Trap, Op Code Trap)• Interrupts ... 3 External, 7 Internal• Operation ModeMode 1 ... Expanded (Internal ROM Inhibited)Mode 2 •.. Expanded (Internal ROM Valid)Mode 3 ... Single-chip Mode• Low Power Dissipation ModeSleepStandby• Wide Range of OperationVee = 3 - 6V (f = 0.1 - 0.5MHz).Vee = 5V±10%(f = 0.5 - 1.0MHz; HD6301XO )f 0.5 - 1.5MHz; HD63A01XOf = 0.5 - 2.0MHz; HD63B01XO(DP-64S)HD6301XOF, HD63A01XOF,HD63B01XOF(FP-80)284 ~HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO• PIN ARRANGEMENT• HD6301XOP, HD63A01XOP, HD63B01XOPv .. iOXTAlp,.EXTAl 3Pl11MP. ~P12MP,P13RES eP,.STBY 7P30NMI 8p.,P,.~P32P" ~ p ••P22 11P""P 1l l p ..p,. p ..p .., P37p,.p,.P" Pl1P 50 1P12p.,P13PS1 'P14p ••p,.p .. 1PIOp •• P"p ••Vssp.,1 P40PooP41p.,p.,p.,PoPu p ..p .. p ..p ••p ••p •• 1P.,p.,Vee(Top View)• BLOCK DIAGRAMP2CJ(Tin)v« __ _V .. --­V .. ---P .. IToutl)'---1~P,,{SCLK) ----¥~Pu(Rx)PN{Tx)P,,{Tout2), --fl-t+1~P,o(Tout3)-H++H+-IP,,{TCLK)-'-:H+t+++-I• HD6301XOF, HD63A01XOF, HD63B01XOFlilii ,Ne ,i::Ii...i i::Ii ::IiI Ip>oIiiiiP"tWAPn/R/WPu!ORP,.,SAPwOo(Top View)P"dD IPu/02Pu/o,P).iID ..P"ID,P./D.P,,/O,p""nm;)p"jllllb)P,,{MR)P,,{iiAlT)PI'P".lp.oI""Pu/A,Pu/AlPu/AlPulA..p."",pt./A.PI "A"P"",..Pc,/A,P41/"10p.,/A'1P.JAlaP.slAt )p ..P"P"POl ..p .. lp ..p ..0:gcot:I.RAM192 By!ftROM4k By!ftP..JAt •P.dAIIP"~HITACHI285

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee -0.3 - +7.0Input Voltage Yin -0.3 - Vee+0.3Operating Temperature Topr 0-+70Storage Temperature Tstg -55 - +150INOTEI This product has protection circuits in input terminal from high static electricity voltage and high electric field.But be careful not to apply overvoltage more than maximum ratings to these high input impedance protectioncircuits. To assure the normal operation, we recommend Vin, Vout: VSS ~ IVin or Voutl ~ Vee.UnitVV°c°c, • ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, T. = O-+70 o C, unless otherwise noted.)Item Symbol Test Condition minRES,STBY Vee-0 .5Input "High" Voltage EXTAL V 1H VeexO.7Other Inputs 2.0Input "Low" Voltage All Inputs V 1L -0.3Input Leakage CurrentNMI, RES, STBY,MPo , MP 1 , Port 5 IIlnl Yin = 0.5-Vee-0.5V -Three State (off-state)Leakage CurrentPorts 1,2,3,4,6,7 IITsd Yin = 0.5-Vee-0.5V -IOH = -200J.l.A 2.4Output "High" Voltage All OutputsVOHIOH = -10J.l.A Vee-0 .7Output "Low" Voltage All Outputs VOL IOL = 1.6mA -Darlington DriveCurrentPorts 2, 6 -loH Vout = 1.5V 1.0Input CapacitanceYin = OV, f = lMHz,All Inputs Cin Ta = 25°C-Standby Current Non Operation ISTB -Sleeping (f = lMHz**) -Current Dissipation *IsLP Sleeping (f = 1.5MHz**) -Sleeping (f = 2MHz**) -Operating (f = lMHz**) -lee Operating (f = 1.5MHz**) -Operating (f = 2MHz**) -RAM Standby Voltage V RAM 2.0·V1H min" Vee-1.OV, V1L max = O.SV IAII output terminals are at no load.)··Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.values about Current Dissipations at x MHz operation are decided according to the following formula;typo value If" x MHz) .. typo value If = 1 MHz) x xmax. value If" x MHz) = max. value If = 1 MHz) x xIboth the sleeping and operating)typ max Unit-Vee-+0.3V-- 0.8 V- 1.0 J.l.A- 1.0 J.l.A- - V- - V- 0.4 V- 10.0 mA- 12.5 pF3.0 15.0 J.l.A1.5 3.0 mA2.3 4.5 mA3.0 6.0 mA7.0 10.0 mA10.5 15.0 mA14.0 20.0 mA- - V286 _HITACHI

-----------------------H 0630 1 XO,HD63AO 1 XO,HD63B01 XO• AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70oC, unless otherwise noted.)BUS TIMINGItemSymbolTest HD6301XO HD63A01XO HD63B01XOCondition min typ max min typ max min typ maxCycle Time tCYC 1 - 10 0.666 - 10 0.5 - 10Enable Rise Time tEr - - 25 - - 25 - - 25Enable Fall Time tEf - - 25 - - 25 - - 25Enable Pulse Width "High" Level* PWEH 450 - - 300 - - 220 - -Enable Pulse Width "Low" Level* PWEL 450 - - 300 - - 220 - -Address, RIWDeiay Time* tAD - - 250 - - 190 - - 160Data Delay Time I Write toow - - 200 - - 160 - - 120Data Set-up Time I Read tOSR80 - - 70 - - 70 - -Fig. 1Address, R/W Hold Time* tAH 80 - - 50 - - 35 - -Data Hold TimeI Write* tHW 80 - - 50 - - 40 - -I Read tHR 0 - - 0 - - 0 - -RD, WR Pulse Width* PWRW 450 - - 300 - - 220 - -RD, WR Delay Time tRWO - - 40 - - 40 - - 40RD, WR Hold Time tHRW - - 30 - - 30 - - 25OR Delay Time tOLR - - 200 - - 160 - - 120rm Hold Time tHLR 10 - - 10 - - 10 - -MR Set-up Time* tSMR 400 - - 280 - - 230 - -M R Hold Time * tHMR Fig. 2 - - 90 - - 40 - - 0E Clock Pulse Width at MR PWEMR - - 9 - - 9 - - 9Processor Control Set-up Time tpcsFig. 3,200 - - 200 - - 200 - -10, 11Processor· Control Rise Time tpcr - - 100 - - 100 - - 100Fig. 2, 3Processor Control Fall Time tpCf- - 100 - - 100 - - 100BA Delay Time teA Fig. 3 - - 250 - - 190 - - 160Oscillator Stabilization Time tRC Fig. 11 20 - - 20 - - 20 - -Reset Pulse Width PW RST 3 - - 3 - - 3 - -• These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc isminimum- (= in the highest speed operation).UnitJJ.SnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsJ.l.snsnsnsnsmstcycPERIPHERAL PORT TIMINGPeripheral DataSet-upTimePeripheral DataHold TimeItemDelay Time (EnableSymbolTest HD6301XO HD63A01XO HD63B01XOCondition min typ max min typ max min typ maxPorts 2, 3, 5, 6 tposu Fig. 5 200 - - 200 - - 200 - -I p 1 2?orts 2, 3, 5, 6 tpOH Fig. 5 200 - - 200 - - 200 - -Negative Transition to 3 o~ts 6 '7 ' tpwo Fig. 6 - - 300 - - 300 - - 300Peripheral Data Valid) , ., ,Unitnsnsns~HITACHI287

HD6301XO,HD63A01XO,HD63B01XO----------------------TIMER, SCI TIMINGTest HD6301XO HD63A01XO HD63B01XOItemSymbolUnitCondition min tvp max min typ max min tvp maxTimer 1 Input Pulse Width tPWT Fig.B 2.0 - - 2.0 - - 2.0 - - 'tcycDelay Time (Enable PositiveTransition to Timer Output)tTOD Fig.7 - - 400 - - 400 - - 400 nsSCI Input l Async. Mode Fig. B 1.0 - - 1.0 - - 1.0 - - tCYCtScyCClock Cycle I Clock Sync.Fig.4,8 2.0 - - 2.0 - - 2.0 - - tCYcSCI Transmit Data DelayTime (Clock Sync. Mode)SCI Receive Data Set-upTime (Clock Sync. Mode)SCI Receive Data Hold Time(Clock Sync. Mode)tTXD - - 200 - - 200 - - 200 nstSRX Fig. 4 290 - - 290 - - 290 - - nstHRx 100 - - 100 - - 100 - - nsSCI Input Clock Pulse Width tPWSCK 0.4 - 0.6 0.4 - 0.6 0.4 - 0.6 tSCYCTimer 2 Input Clock Cycle ttcyC 2.0 - - 2.0 - - 2.0 - - tCYCTimer 2 Input Clock PulseWidth Fig. 8Timer 1·2, SCI Input ClockRise TimeTimer 1·2, SCI Input ClockFall TimetpwTCK 200 - - 200 - - 200 - - nstCKr - - 100 - - 100 - - 100 nstCKf - - 100 - - 100 - - 100 ns288 ~HITACHI

----------------------HD6301XO,HD63A01XO,HD63B01XO1-----------tCyc------------IE1-----PWEl---~f-.---PWEH--------IAo-A15,R/W2.4VO.BVRO,WRMCU Write00-07MCU Read00-07Figure 1 Mode 1, Mode 2 Bus TimingI-------PWEMR-------tE--1---1--tHMR\\\'-----O.8VMRFigure 2 Memory Ready and E Clock Timing$ HITACHI289

HD6301XO,HD63A01XO,HD63B01XO----------------------------------------------ELast InstructionExecution CycleI ·1HALT CycleInstruction ExecutionCycleSAtBA~~,----~I~--------------------~2.4VFigure 3 HALT and SA TimingSynchronous ClockTransmit DatatSRX tHRXjReceive Data --( 2.0V~ H~ ___________ ~~O_.8_V ________..~ ______ _• 2.0V is high level when clock input.2.4V is high level when clock output.EFigure 4 SCI Clocked Synchronous TimingEr- MCUWriteP30-P37(I!'puts)P'O-P17. P20-P27----------~ 100 ........... -­P30- P37. P40- P47PSO-P67. P70-P74----------- ~~u.. __(Outputs)Figure 5 Port Data Set-up and Hold Times (MCU Read)Figure 6 Port Data Delay Times IMCU Writ.)290~HITACHI

----------------------HD6301XO,HD63A01XO,HD63B01XOETimer 1 ----.... ,.-,..,L":;';;;':'==-----­FRCP 21 , P 2S --------.:.-..:..Outputs --------.... 'Jt.~:.:....---(a) Timer 1 Output Timing(b) Timer 2 Output TimingFigure 7Timer Output Timing* Timer 2; ttcycSCI ; tSCYc* * Timer 1; tPWTTimer 2; tPWTCKSCI ;tPWSCKVeemRL=2.2kQTest Point1S2074(8)C R or ~quiv.C=90pF for Port 1, Port 3, Port 4, E=30pF for Port 2, Port 6. Port 7R= 12kQ for Port 1 - Port 4, Port 6, Port 7, EFigure 8 Timer 1-2, SCI Input Clock TimingFigure 9 Bus Timing Test Loads (TTL Load)InterruptTestInternalAddress Bus __ J,-I-....... "-_..rI__"-_.J'~_J'\._...J"__J'\._......."-_J'\._......."-_-"_......."-_J\_......."-_-"...NMI, iimi.iRQi.IR

HD6301XO,HD63A01XO,HD63B01XO----------------------~~-------------------Vee--5.5~V~ ________ ~ ______ 4-______________ ~1/l---'---'AC -----j~'PCSv ec -O.SvAn --41.......--------_,~fr·"Ia~\\\\\\\\\\\\\\\\\\\\\\\C:X=~~:::X::X::X::FFFF FFFF FFFF FFFF FFFF FFFE FFFF lIIow PC ''''--F1FF FFFF FFFFW'·rna' 8\1)\\\\\\\\\\\\\*\\\\\\\\I~~'I-' ---__ADWI!_~\\\\\\\\\\\\\'\~\\\\\\f1\Dt:\\\\\\\\\",,\\\\~~\\\W'~~~)-'---­n f~~')-I ----~·III£;J~IWI"jlifill'lmlijlmlmlijllijpD~----------~~~~~'-----------PCB- PCO- First'PCl5 PC7 InstructionFigure 11 Reset Timing• FUNCTIONAL PIN DESCRIPTION• Vee, VssVee and V ss provide power to the MCU with 5V± 10% supply.In the case of low speed operation (fmax = 500kHz), theMCU can operate with three through six volts. Two V ss pinsshould be tied to ground.be less than four times of the maximum operable frequency.When using the external clock, XT AL pin should be open.Fig. 12 shows examples of connection circuit. The crystaland C Ll , CL2 should be mounted as close as possible to XT ALand EXT AL pins. Any line must not cross the line between thecrystal oscillator and XT AL, EXT AL.• XTAL,EXTALThese two pins interface with an AT -cut parallel resonantcrystal. Divide-by-four circuit is on chip, so if 4MHz crystaloscillator is used, the system clock is lMHz for example.EXTAL pin is drivable with the external clock of 45 to50% duty, and one fourth frequency of the external clockis produced in the LSI. The external clock frequency shouldAT Cut Parallel Resonant Crystal OscillatorCo=7pF maxRs=60Q maxXTAL~--~-----'CJEXTALI---.-.....(a)-lCl2t llCrystal InterfaceCll =Cl2= 10pF-22pF±20%(3.2-SMHz)XTAL~ N.C.eXTALj---

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO($FFFE, $FFFF) into the program counter and start theprogram from this address. (Refer to Table 1).* The MCU is unable to accept a reset input until the clockbecomes normal oscillation after power on (max. 20ms). Duringthis transient time, the MCU and I/O pins are undefined. Pleasebe aware of this for system designing.• Enable (E)This pin provides a TTL-compatible system clock to externalcircuits. Its frequency is one fourth that of the crystal oscillatoror external clock. This pin can drive one TTL load and 90pFcapacitance.• Non-Maskable Interrupt (NMI)When the falling edge of the input signal is detected at thispin, the CPU begins non-maskable interrupt sequence internally.As well as the IRQ mentioned below, the instruction beingexecuted at NMI signal detection will proceed to its completion.The interrupt mask bit of the condition code register doesn'taffect non-maskable interrupt at all.When starting the acknowledge to the NMI, the contents ofthe program counter, index register, accumulators and conditioncode register will be saved onto the stack. Upon completionof this sequence, a vector is fetched from $FFFC and $FFFDto transfer their contents into the program counter and branchto the non-maskable interrupt service routine. After reset start,the stack pointer should be initialized on an appropreate memoryarea and then the falling edge be input to NMI pin.• Interrupt Request (IRO l , IR0 2 )These are level-sensitive pins which request an internalinterrupt sequence to the CPU. At interrupt request, the CPUwill complete the current instruction before its request acknowledgement.Unless the interrupt mask in the condition coderegister is set, the CPU starts an interrupt sequence; if set, theinterrupt request will be ignored. When the sequence starts, thecontents of the program counter, index register, accumulatorsand condition code register will be saved onto the stack, tht''lthe CPU sets the interrupt mask bit and will not acknowledgethe maskable request. During the last cycle, the CPU fetchesvectors depicted in Table 1 and transfers their contents to theprogram counter and branches to the service routine.The CPU uses the external interrupt pins, IRQl and IRQ2also as port pins Pso and Pst. so it provides an enable bit toBit 0 and 1 of the RAM port 5 controiregister at $0014. Referto "RAM/PORT 5 CONTROL REGISTER" for the details.When one of the internal interrupts, ICI, OCI, TOI, CMI orSIO is generated, the CPU produces internal interrupt signal(IRQ3). IRQ3 functions just the same as IRQl or IRQ2 exceptfor its vector address. Fig. 13 shows the block diagram of theinterrupt circuit.PriorityMSBTable 1 Interrupt Vector Memory MapVectorLSBHighest FFFE FFFF RESFFEE FFEF TRAPFFFC FFFD NNIIInterruptFFFA FFFB SWI (Software Interrupt)FFF8 FFF9 IRO lFFF6 FFF7 ICI (Timer 1 I nput Capture)FFF4 FFF5 OCI (Timer 1 Output Compare 1, 2)FFF2 FFF3 TOI (Timer 1 Overflow)FFEC FFED CMI (Timer 2 Counter Match)FFEA FFEB IR0 2Lowest FFFO FFF1 SIO (RDRF+ORFE+TDRE)~HITACHI 293

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Each Register's InterruptEnable Flag"1"; Enable, "0"; DisableICF0-+----1 Condition~--.... Code----t--o-~CHI_---I RegisterI-MASKICIOCF1IRChOCF2 ---~o---TOFCMFRDRFORFETORE ----+--O-~InterruptRequestSignalSleepCancelSignalTRAPSWI• Mode Program (MP 0, MP I)These two pins decide the operation mode_ Refer to "MODESELECTION" for mode details.The following signal desc14t'tions are applicable only for theexpanded mode.• Read/Write (R/W; P 72 )This signal, usually be in read state ("High"), shows whetherthe MCU is in read ("Hi6h") or write ("Low") state to theperipheral or memory devices. This can drive one TTL loadand 30pF capacitance.• RD,WR (P'lO,P71 )These signals show active low outputs when the CPU isreading/writing to the peripherals or memories. This enablesthe CPU easy to access the peripheral LSI with RD and WRinput pins. These pins can drive one TTL load and 30pF capacitance.• Load Instruction Register (LIR; P 73)This . signal shows the instruction ope code being on databus (active low). This pin can drive one TTL load and 30pFcapacitance.Figure 13 Interrupt Circuit Block Diagram• Memory Ready (MR; P 52 )This is the input control signal which stretches the systemclock's "High" period to access low-speed memories. DuringCPU to interface with low-speed memories (See Fig. 2). Up to9p.s can be stretched.During internal address space access or nonvalid memoryaccess, MR is prohibited internally to prevent decrease of operationspeed. Even in the halt state, MR can also stretch "High"period of system clock to allow peripheral devices to accesslow-speed memories. As this signal is used also as P 52 , an enablebit is provided at bit 2 of the RAM/port 5 control register at$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" formore details.• Halt (HALT; P 53 )This is an input control Signal to stop instruction executionand to release buses free. When this signal switches to "Low",the CPU stops to enter into the halt state after having executedthe present instruction. When entering into the halt state, itmakes BA (P74) "High" and also an address bus, data bus, RD,WR, R/W in high impedance. When an interrupt is generatedin the halt state, the CPU uses the interrupt handler after thehalt is cancelled. When halted during the sleep state, the CPUkeeps the sleep state, while BA is "High" and releases the buses.Then the CPU returns to the previous sleep state when the·HALT signal becomes "High". The same thing can be said whenthe CPU is in the interrupt wait state after having executed theWAI instruction.this signal being in "High", the system clock operates in normal • Bus Available (BA; P74)sequence. But this signal in "Low", the "High" period of the This is an output control signal which is normally "Low"system clock will be stretched depending on its "Low" level but "High" when the CPU accepts HALT and releases the buses.duration in integral multiples of the cycle time. This allows the The HD6800 and HD6802 make BA "High" and release the294 * HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XObuses at WAI execution, while the HD6301XO doesn't makeBA "High" under the same condition. But if the HALT becomes"Low" when the CPU is in the interrupt wait state after havingexecuted the WAI, the CPU makes BA "High" and releases thebuses. And when the HALT becomes "High", the CPU returnsto the interrupt wait state.• PORTThe HD6301XO provides seven I/O ports (six 8·bit ports anda 5·bit port). Table 2 gives the address of ports and the datadirection register and Fig. 14 the block diagrams of each port.Table 2 Port and Data Direction Register AddressPort Port Address Data Direction RegisterPort 1 $0002 -Port 2 $0003 $0001Port 3 $0006 $0004Port 4 $0007 -Port 5 $0015 -Port 6 !at0017 $0016Port 7 $0018 -• Port 1An 8·bit port for output only. In mode 3, port 1 goes to highimpedance during reset and keeps the state even after acceptingreset cancellation. It continues till a write operation is madeto port 1. When a write operation is made to port 1, the highimpedance state shifts to the output state and t: ..i written datawill be output. Once port 1 gets in the output state, it operatesas an output till reset occurs. CPU can also read the value of thePort 1 data register, thus enables the CPU to use bit manipula·tion.In mode 1 and 2, port 1 acts as "Low" address buses. Thisport can drive one TTL load and 90pF capacitance .• Port 2An 8·bit input/output port. The data direction register(DDR) of port 2 is responsible for I/O state. It provides twobits; bit 0 decides the I/O direction of P 20 and bit 1 the I/Odirection ofP 21 to P 27 ("0" for input, "I" for output).Port 2 is also used as an I/O pin for the timers and theSCI. When used as an I/O pin for the timers and the SCI, port2 except P 20 automatically becomes an input or an outputdepending on their functions regardless of the data directionregister's value.Port 2 Data Direction Register7 6 4 3A reset clears the DDR of port 2 and configures port 2 as aninput port. This port can drive one TTL and 30pF. In addition,it can produce ImA current when Vout = 1.5V to drive directlythe base of Darlington transistors.Port Write SignalData BusData BusAddress Bus,Control SignalData BusMode 1, 2...LPort 1, Port 4. Port 7Timer 1, 2,:--i--___ ~SCI OutputPort Read Signal-'--Timer 1, 2,_--______ CSCI InputPort 2Data BusPort Write SignalCPU Internal Bus _----~Port 3Timer 1 Input_---____ -CIP. o only)Data Bus---~""-CPort 5Figure 14 Port Block Diagram~HITACHI 295

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------• Port3An 8-bit I/O port. The DDR of port 3 is responsible forI/O state. It provides only one bit which decides I/O state bythe byte ("0" for input and "1" for output). It is cleared duringreset.Port 3 Data Direction Register6 4 3 o• Port4An 8-bit port for output only like Port 1. In mode 1 and 2,"High" address will be produced.• Port5An 8-bit port for input only. The lower four bits are alsousable as input pins for interrupt, MR and HALT.• Port6An 8-bit I/O port. This port provides an 8-bit DDR correspondingto each bit and can specify input or output by thebit ("0" for input, "1" for output). This port can drive oneTTL load and 30pF. A reset clears the DDR of port 6. Inaddition, it can produce ImA current when Vout = l.SV todrive directly the base of Darlington transistors.• Port7A S·bit port for output only. In mode 3, port 7 goes to highimpedance during reset and keeps the state even after acceptingreset cat:lcellation. It continues till a write operation is made toport 7. When a write operation is made to port 7, the highimpedance state shifts to the output state and the written datawill be output. Once port 7 gets in the output state, it operatesas an output till reset occurs. Port 7 can also read the value ofthe data register, thus enables the CPU to use the bit manipulationinstruction. In this case b 7 - bs are" 1".In mode 1 and 2, port 7 acts as outputs for control signals(RD, WR, R/W, LIR and BA). This port can drive one TTLload and 30pF.• RAM/PORT 5 CONTROL REGISTERThe control register located at $0014 controls on-chipRAM and port 5.RAM/Port 5 Control Register765432101!::;IRAMEI-I--IHLTEIMREII~Q211:Q'I$0014Bit 0, Bit 1 I RO I , I R0 2 Enable Bit (I R0 1 E, I R0 2 E)When using Pso and PSI as interrupt pins, write "1" inthese bits. When "0", the CPU doesn't accept an externalinterrupt or a sleep cancellation by the external interrupt.These bits become "0" during reset.regardless of the value of this bit. This bit becomes "I" duringreset.Bit 3 Halt Enable bit (HL TE)When using P S3 as an input for Halt signal, write "I" in thisbit. When "0", the halt function is prohibited. In mode 3, thehalt function is prohibited regardless of the value of this bit.This bit becomes "1" during reset.Bit 4, Bit 5 Not Used.Bit 6 RAM Enable (RAME)On-chip RAM can be disabled by this control bit. TheMCU Reset sets "1" at this bit and enables on-chip RAMavailable. This bit can be written "1" or ''0'' by software.When RAM is in disable condition (= logic ''0''), on-chip RAMis invalid and the CPU can read data from external memory.This bit should be ''0'' at the beginning of standby mode toprotect on-chip RAM data.Bit 7 Standby Power Bit (STBY PWR)When Vee is not provided in standby mode, this bit iscleared. This is a flag for both read/write by software. If this bitis set before standby mode, and remains set even after returningfrom standby mode, Vee voltage is provided during standbymode and the on-chip RAM data is valid.• MODE SELECTIONMode program pins, MPo and MP. determine the operationmode of the HD6301XO as Table 3 gives.• Mode 1 (Expanded Mode)In this mode, port 3 is data bus and port 1 "Low" addressbus and port 4 "High" address bus to realize a direct inter§cewith the HMCS6800 buses. A control signal such as R/W isproduced at port 7. In mode 1, on-chip ROM is disabled and65k bytes of address space are externally expandable (referto Fig. 15).• Mode 2 (Expanded Mode)This mode is also expandable as well as mode 1. But in thismode, on-chip ROM is enabled and the expandable addressspace is 61k bytes (refer to Fig. 16) .• Mode 3 (Single-chip Mode)In this mode, all ports are available (refer to Fig. 17).Mode MP.Table 3 Mode SelectionMPo ROM RAMInterruptVectorOperation Mode1 "L" "H" E 1* E Expanded Mode2 "H" "L" I 1* I Expanded Mode3 "H" "H" I I I Single-chip Mode"L" = Logic "0", "H" = Logic "1", I; Internal, E; External... The addressing RAM area can be external by clearing RAME bit at$0014.Bit 2 Memory Ready Enable Bit (MRE)When using PS2 as an input for Memory ReadY'signal, write"1" in this bit. When "0", the memory ready function is prohibited.In mode 3, the memory ready function is prohibited296 ~HITACHI

----------------------------------------------HD6301XO,HD63A01XO,HD63B01XOVeeADCJWRDWRR/INR/WRES ITR RES LlRSTBY- HD6301XO STBY-NMIBAHD6301XONMIBAPort 2Port 3 Port 2 MCU81/0 LinesPort 38 Data Bus 8 110 LinesTimer 1,2 Tuner 1, 2 SCI 8 Data BusSCIPort 5 Port 1Port 58 Input Lines [Port 1IRO" IR028 Address BusMR, HALTMR, HALTPort 6Port 4Port 6Port 48 I/O Lines8 Address Bus8 1/0 Lines 8 Address Bus81Rrr;~ ~-Wffi8 Address BusR5Figure 15 Mode 1 Figure 16 Mode 2VeeCJPort 28 I/O LinesTimer 1, 2 SCIPort 58 Input Linesrna;: iRQiPort 68 I/O LinesPort 75 Output LinesPort 38 I/O LinesPort 18 Output LinesPort 48 Output LinesFigure 17 Mode 3• Mode and PortTable 4 shows MeV signals in each mode.Table 4 MCU Signals in Each Mode~PortMode 1 Mode 2Port 1 Address Bus (Ao-A 7 ) Address Bus (Ao-A 7 )Port 2 I/O Port I/O PortPort 3 Data Bus (Do -0 7 ) Data Bus (Do -0 7 )Port 4 Address Bus (As -A 1S ) Address Bus (As-Au)Port 5 Input Port Input PortPort 6 I/O Port I/O PortPort 7 RD, WR, R/W, UR, BA RD, WR, R/W, UR, BAMode 3Output PortI/O PortI/O PortOutput PortInput PortI/O PortOutput Port~HITACHI297

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------• MEMORY MAPThe MCU can address up to 65k bytes depending on itsoperation mode. Fig. 18 gives memory maps in each operationmode. 32 internal registers use addresses from "00" as shown inTable 5.Table 5 Internal RegisterAddressRegisters00 -01 Port 2 Data Direction Register02* Port 103 Port 204* Port 3 Data Direction Register05 -06* Port 307* Port 408 Timer Control/Status Register 109 Free Running Counter ("High")OAFree Running Counter ("Low")08 Output Compare Register 1 ("High")OCOutput Compare Register 1 ("Low")00 Input Capture Register ("High")OEInput Capture Register ("Low")OF Timer Control/Status Register 210 Rate. Mode Control Register11 Tx/Rx Control Status Register12 Receive Data Register13 Transmit Data Register14 RAM/Port 5 Control Register15 Port 516 Port 6 Data Direction Register17 Port 618* Port 719 Output Compare Register 2 ("High")1AOutput Compare Register 2 ("Low")18 Timer Control/Status Register 31CTime Constant Register10 Timer 2 Up Counter1E -1F** Test Register• External Address in Mode 1, 2 .•• Test Register. Do not access to this register .••• R : Read Only RegisterW : Write Only RegisterR/W: Read/Write RegisterRIW*** Initialize at RESET- -W$FCRIWUndefinedRIWUndefinedW$FE- -RIWUndefinedRIWUndefinedRIW $00RIW $00RIW $00RIWRIW$FF$FFR $00R $00RIW $10RIW $00RIW $20R $00W $00RIW$7C or $FCR -W $00RIWRIWRIWRIWUndefinedUndefined$FF$FFRIW $20W$FFRIW $00----298$ HITACHI

HD6301 XO,HD63AOl XO,HD63BOl XOHD6301XOExpanded ModeMode 1HD6301XOExpanded ModeMode 2HD6301XOSingle-chip ModeMode 3Internal*RegistersExternalMemorySpaceInternalRAM$OOFFInternal*RegisterExternalMemorySpaceInternalRAM$OOlF$0040$OOFFInternalRegisterInternalRAMExternalMemorySpaceExternalMemorySpace$FOOOInternalROMInternalROM$FFFF '--____ - .. 1'$FFFF "-"'~~~J)* Excludes the following addresseswhich may be used externally:$02, $04, $06, $07, $18.* Excludes the following addresseswhich may be used externally:$02, $04, $06, $07, $18.Figure 18 HD6301 XO Memory Map• TIMER 1The HD6301XO provides a 16-bit programmable timer whichcan measure an input waveform and generate two independentoutput waveforms. The pulse widths of both input/outputwaveforms vary from microseconds to seconds.Timer 1 is configurated as follows (refer to Fig. 20).• Control/Status Register 1 (8 bit)• Control/Status Register 2 (7 bit)• Free Running Counter (16 bit)• Output Compare Register 1 (16 bit)• Output Compare Register 2 (16 bit)• Input Capture Register (16 bit)• Free-Running Counter (FRC) ($0009 : OOOA)The key timer element is a 16-bit free-running counter drivenand incremented by system clock. The counter value is readableby software without affecting the counter. The counter iscleared by reset.When writing to the MSB byte ($09), the CPU writes thepreset value ($FFF8) into the counter (address $09, $OA)regardless of the write data value. But when writing to theLSB byte ($OA) after MSB byte writing, the CPU write notonly LSB byte data into lower 8 bit, but also MSB byte datain to higher 8 bit of the FRC.The counter will be as follows when the CPU writes to itby double store instructions (STD, STX etc.).Counter value$09 Write $OA Write$FFF8In the case of the CPU write ($5AF3) to the FRCFigure 19 Counter Write Timing• Output Compare Register (OCR)($0008, $OOOC; OCR1) ($0019, $O01A ; OCR2)The output compare register is a 16-bit read/write registerwhich can control an output waveform. It is always comparedwith the FRC.When data matches, output compare flag (OCF) in the timercontrol/status register (TCSR) is set. If an output enable bit(OE) in the TCSR2 is "1", an output level bit (OLVL) in theTCSR will be output to bit 1 (Tout 1) and bit 5 (Tout 2) ofport 2. To control the output level again by the next compare, achange is necessary for the OCR and OLVL. The OCR is set to$FFFF at reset. The compare function is inhibited for a cyclejust after a write to the OCR or to the upper byte of theFRC. This is to set the 16-bit value valid in the register forcompare. In addition, it is because $FFF8 is set at the nextcycle of the CPU's MSB byte write to the FRC.* For data write to the FRC or the OCR, 2-byte transferinstruction (such as STX etc.) should be used.• Input Capture Register (lCR) ($0000 : OOOE)The input capture register is a 16-bit read only register whichstores the FRC's value when external input signal transitiongenerates an input capture pulse. Such transition is defined byinput edge bit (IEDG) in the TCSRI.In order to input the external input signal to the edgedetecter, a bit of the DDR corresponding to bit 0 of port 2should be cleared ("0"). When an input capture pulse occuresby input transition at the next cycle of CPU's high-byte read ofthe ICR, the input capture pulse will be delayed by one cycle.In order to ensure the input capture operation, a CPU read ofthe ICR needs 2-byte transfer instruction. The input pulse widthshould be at least 2 system cycles. This register is cleared($0000) during reset.~HITACHI 299

HD6301XO.HD63A01XO.HD63B01XO~~~~~~~~~~~~~~~~~~~~~~• Timer Control/Status Register 1 (TCSR1) ($0008)The timer control/status register} is an 8-bit register. All bitsare readable and the lower 5 bits are also writable. The upper 3bits are read only which indicate the following timer status.Bit 5 The counter value reached to $0000 as a result ofcounting-up (TOF).Bit 6 A match has occured between the FCR and the OCR I(OCFI).Bit 7 Defined transition of the timer input signal causes thecounter to transfer its data to the ICR (ICF).The followings are each bit descriptions.7 6Timer Control/Status Register 1Bit 0 Ol Vll Output level 1OLVLl is transferred to port 2, bit I when a matchoccurs between the counter and the OCRI. If OEl,namely, bit 0 of the TCSR2, is set to "I", OLVLl willappear at bit I of port 2.Bit 1 IEDG Input EdgeThis bit determines which rising edge or falling ofinput signal of port ,2, bit 0 will trigger data transferfrom the counter to the ICR. For this function, theDDR corresponding to port 2, bit 0 should be clearedbeforehand.IEDG=O, triggered on a falling edge("High" to "Low")IEDG= I, triggered on a rising edge("Low" to "High")Bit 2 ETOI Enable Timer Overflow InterruptWhen this bit is set, an internal interrupt (IRQ3) byTOI interrupt is enabled. When cleared, the interrupt isinhibited.Bit 3 EOCll Enable Output Compare Interrupt 1When this bit is set, an internal interrupt (IRQ3) byDCIl interrupt is enabled. When cleared, the interruptis inhibited.Bit 4 EICI Enable Input Capture InterruptWhen this bit is set, an internal interrupt (IRQ3 )'byICI interrupt is enabled. When cleared, the interrupt isinhibited.Bit 5 TOF Timer Overflow FlagThis read only bit is set when the counter incrementsfrom $FFFF by I. Cleared when the counter'sMSB byte ($0009) is read by the CPU following theTCSRI read.Bit 6 OCFl Output Compare Flag 1This read only bit is set when a match occurs betweenthe OCR} and the FRC. Cleared by writing tothe OCR} ($OOOB or $OOOC) following the TCSR I orTCSR2 read.Bit 7 ICF Input Capture FlagThis read only bit is set when an input signal ofport 2, bit 0 makes a transition as defined by IEDG andthe FRC is transferred to the ICR. Cleared when readingthe MSB byte ($OooD) of the ICR following the TCSRIor TCSR2 read.• Timer Control/Status Register 2 (TCSR2) ($OOOF)The timer control/status register 2 is a 7-bit register. All bitsare readable and the lower 4 bits are also writable. But theupper 3 bits are read-only which indicate the following timerstatus.Bit 5 A match has occured between the FRC and the OCR2Bit 6(OCF2).The same status flag as the OCFt flag of the TCSRl,bit 6.Bit 7 The same status flag as the ICF flag of the TCSRI , bit 7.The followings are each bit descriptions.Timer Control/Status Register 276543210ICF IOCF 11 OCF21 - roc'2~LvL21 OE21 o~ $OOOFBit 0 OEl Output Enable 1This bit enables the OLVLl to appear at port 2, bitI when a match has occurred between the counter andthe output compare register I. When this bit cleared, bitI of port 2 will be I/O port. When set, it will be anoutput ofOLVLl automatically.Bit 1 OE2 Output Enable 2This bit enables the OLVL2 to appear at port 2, bit5 when a match has occurred between the counter andthe output compare register 2. When this bit cleared,port 2, bit 5 will be I/O port. When set, it will be anoutput of OLVL2 automatically.Bit 2 Ol Vl2 Output level 2OLVL2 is transferred to port 2, bit 5 when a matchhas occurred between the counter and the OCR2. IfOE2, namely bit 5 of the TCSR2, is set to "I", OLVL2will appear at port 2, bit 5.Bit 3 EOCI2 Enable Output Compare Interrupt 2When this bit is set, an internal interrupt (IRQ3) byOCI2 interrupt is enabled. When cleared, the interruptis inhibited.Bit 4 Not UsedBit 5 OCF2 Output Compare Flag 2This read-only bit is set when a match has occurredbetween the counter and the OCR2. Cleared whenwriting to the OCR2 ($0019 or $OOIA) following theTCSR2 read.Bit 6 OCFl Output Compare Flag 1Bit 7 ICF Input Capture FlagOCF I and ICF addresses are partially decoded.CPU read of the TCSRl/TCSR2 makes it possible toread OCFI and ICF into bit 6 and bit 7.Both the TCSRI and TCSR2 will be cleared during reset.(Note) If OEI or OE2 is set to "I" before the first outputcompare match occurs after reset restart, bit I or bit 5of port 2 will produce "0" respectively.(Note) Because the set condition of lCF precedes ,its resetcondition, ICF is not cleared when the set conditionand the reset condition occur simultaneously. Thesame phenomenon applies to OCF I, OCF2 or TOFrespectively.300 ~HITACHI

~-------------------------------------------HD6301XO,HD63A01XO,HD63B01XOFigure 20 Timer 1 Block Diagram• TIMER 2In addition to the timer 1, the HD6301XO provides an 8·bitreloadable timer, which is capable of counting the externalevent. This timer 2 contains a timer output, so the MCU cangenerate three independent waveforms. (Refer to Fig. 21.)The timer 2 is configured as follows:Control/Status Register 3 (7 bit)8·bit Up CounterTime Constant Register (8 bit)• Timer 2 Up Counter (T2CNT) ($0010)This is an 8·bit up counter which operates with the clockdecided by CKSO and CKSl of the TCSR3. The counter isalways readable without affecting itself. In addition, any valuecan be written to the counter by software even during counting.The counter is cleared when a match occurs between thecounter and the TCONR or during reset.If a write operation is made by software to the counter at thecycle of counter clear, it does not reset the counter but put thewrite data to the counter.• Time Constant Register (TCONR) ($001C)The time constant register is an 8·bit write only register. Itis always compared with the counter.When a match has occurred, counter match flag (CMF) ofthe timer control status register 3 (TCSR3) is set and the valueselected by TOSO and TOSl ofthe TCSR3 will appear at port 2,bit 6. When CMF is set, the counter will be cleared simultane·ously and then start counting from $00. This enables regularinterrupts and waveform outputs without any software support.The TCONR is set to "$FF" during reset.• Timer Control/Status Register 3 (TCSR3) ($001 B)The timer control/status register 3 is a 7·bit register. All bitsare readable and 6 bits except for eMF can be written.The followings are each pin descriptions.ITimer Control/Status Register 37 6 5 4 3.2 1 0CMF ,ECMII -I T2E ITOSllTOSolCKSllCKSol $0018$ HITACHI 301

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------HD6301 XO Internal Data Busr----- Timer1 FRCt-----t-- Port 2Bit 7t-+---+------1~~ Port 2Bit 6Figure 21Timer 2 Block DiagramBit 0 CKSO Input Clock Select 0Bit 1 C.KS 1 I nput Clock Select 1Input clock to the counter is selected as shown inTable 6 depending on these two bits. When an externalclock is selected, bit 7 of port 2 will be a clock inputautomatically. Timer 2 detects the rising edge of theexternal clock and increments the counter. The externalclock is countable up to half the frequency of thesystem clock.Table 6 Input Clock SelectCKS1 CKSO I nput Clock to the Counter0 0 E clock0 1 E clock/8*1 0 E clock/128*1 1 External clock• These clocks come from the FRC of the timer 1. If one of these clocksis selected as an input clock to the up counter, the CPU should notwrite to the FRC of the timer 1.Bit 2 TOSO Timer Output Select 0Bit 3 rOS1 Timer Output Select 1When a match occurs between the counter and theTCONR timer 2 outputs shown in Table 7 will appear atport 2, bit 6 depending on these two bits. When bothTOSO and TOSI are "0", bit 6 of port 2 will be an 1/0port.Table 7 Timer 2 Output SelectTOS1 TOSO Timer Output0 0 Tjmer Output Inhibited0 1 Toggle Output*1 0 Output "0"1 1 Output "1"* When a match occurs between the counter and the TCON R, timer 2output level is reversed. This leads to production of a square wave with50% duty to the external without any software support.Bit 4 T2E Timer 2 Enable BitWhen this bit is cleared, a clock input to the upcounter is prohibited and the up counter stops. When setto "1 ", a clock selected by CKSI and CKSO (Table 6) isinput to the up counter.(Note) P26 produces "0" when T2E bit cleared and timer 2 setin output enable condition by TOSI or TOSO. It alsoproduces "0" when T2E bit set "1" and timer 2 set inoutput enable condition before the first counter matchoccurs.Bit 5 Not UsedBit 6 ECMI Enable Counter Match InterruptWhen this bit is set, an internal interrupt (IRQ3) byCMI is enabled. When cleared, the interrupt is inhibited.Bit 7 CMF Counter Match 'FlagThis read only bit is set when a match occurs betweenthe up counter and the TCONR. Cleared by a softwarewrite (unablC' to write "1" by software).Each bit of the TCSR3 is cleared during reset.302 ~HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO• SERIAL COMMUNICATION INTERFACE (SCI)The HD6301XO SCI contains two operation modes; one is anasynchronous mode by the NRZ format and the other is aclocked synchronous mode which transfer data synchronizingwith the serial clock.The serial interface is configured as follows:• Control/Status Register (TRCSR)• Rate/Mode Control Register (RMCR)• Receive Data Register (RDR)• Receive Data Shift Register (RDSR)• Transmit Data Register (TDR)• Transmit Data Shift Register (TDSR)The serial I/O hardware requires an initialization by softwarefor operation. The procedure is usually as follows:1) Write a desirable operation mode into each correspond·ing control bit of the RMCR.2) Write a desirable operation mode into each correspond·ing control bit of the TRCSR.When using bit 3 and 4 of port 2 for serial I/O only, there isno problem even if TE and RE bit are set. But when setting thebaud rate and operation mode, TE and RE should be "0". Whenclearing TE and RE bit and setting them again, more than I bitcycle of the current baud rate is necessary. If set in less than 1bit cycle, there may be a case that the internal transmit/receiveinitialization fails.• Asynchronous ModeAn asynchronous mode contains the following two dataformats:I Start Bit + 8 Bit Data + 1 Stop BitI Start Bit + 9 Bit Data + 1 Stop BitIn addition, if the 9th bit is set to "1" when making 9bit data format, the format of1 Start bit + 8 Bit Data + 2 Stop Bitis also transferred.Data transmission is enabled by setting TE bit of the TRCSR,then port 2, bit 4 will become a serial output independently ofthe corresponding DDR.For data transmit, both the RMCR and TRCSR should beset under the desirable operating conditions. When TE bit isset during this process, 10 bit preamble will be sent in 8-bit dataformat and 11 bit in 9-bit data format. When the preamble isproduced, the internal synchronization will become stable andthe transmitter is ready to act.The conditions at this stage are as follows.1) If the TDR is empty (TDRE=I), consecutive l's areproduced to indicate the idle state.2) If the TDR contains data (TDRE=O), data is sent to thetransmit data shift register and data transmit starts.During data transmit, a start bit of "0" is transmitted first.Then 8-bit or 9-bit data (starts from bit 0) and a stop bit of "1"are transmitted .When the TDR is "empty", hardware sets TDRE flag bit. Ifthe CPU doesn't respond to the flag in proper timing (the TDREis in set condition till the next normal data transfer starts fromthe transmit data), "1" is transferred instead of the start bit "0"and continues to be transferred till data is provided to the dataregister. While the TDRE is "1", "0" is not transferred.Data receive is possible by setting RE bit. This makes port 2,bit 3 be a serial input. The operation mode of data receive isdecided by the contents of the TRCSR and RMCR. The first"0" (space) synchronizes the receive bit flow. Each bit of thefollowing data will be strobed in the middle. If a stop bit is not"1", a framing error assumed and ORFE is set.When a framing error occurs, receive data is transferred tothe receive data register and the CPU can read error-generatingdata. This makes it possible to detect a line break.If the stop bit is "1", data is transferred to the receive dataregister and an interrupt flag RDRF is set. If RDRF is stillset when receiving the stop bit of the next data, ORFE is set toindicate overrun generation.When the CPU read the receive data register as a response toRDRF flag or ORFE flag after having read TRCS, RDRF orORFE is cleared.(Note) Clock Source in Asynchronous ModeWhen using an internal clock for serial I/O, the followingsshould be kept in mind.• Set CC I and eco to "I" and "0" respectively.• A clock is generated regardless of the value of TE,RE.Maximum clock rate is E+16.• Output clock rate is the same as bit rate.When using an external clock for serial I/O, the followingsshould be kept in mind.• Set eC1 and CCO in the RMCR to "I" and "I" respectively.• The external clock frequency should be set 16 timesof the applied baud rate.• Maximum clock frequency is that of the systemclock.• Clocked Synchronous ModeIn the clocked synchronous mode, data transmit issynchronized with the clock pulse. The HD6301XO SCIprovides functionally independent transmitter and receiverwhich makes full duplex operation possible in the asynchronousmode. But in the clocked synchronous mode an SCI clock I/Opin is only P 22, so the simultaneous receive and transmitoperation is not available. In this mode, TE and RE shouldnot be in set condition (" I") simultaneously. Fig. 23 gives asynchronous clock and a data format in the clocked synchronousmode.~HITACHI 303

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Transmit/Receive Control and Status RegisterTimerl FRC.Timer2Up CounterData transmit is realized by setting TE bit in the. TRCSR.Port 2, bit 4 becomes an output unconditionally independentof the value of the corresponding DDR.Both the RMCR and TRCSR should be set in the desirableoperating condition for data transmit.When an external clock input is selected, data transmit isSynchronousclockFigure 22 Serial Communication Interface Block Diagram

----------------------------------------------HD6301XO,HD63A01XO,HD63B01XOTransmit/Receive Control Status Register765432 0IRDRFIORFEITDREI RIE I RE I TIE I TE I WU ,$0011Bit 0 WU Wake-upIn a typical multi-processor configuration, thesoftware protocol provides the destination address atthe first byte of the message. In order to make uninterestedMCU ignore the remaining message, a wake-upfunction is available. By this, uninterested MCU can inhibitaU further receive processing till the next messagestarts_Then wake-up function is triggered by consecutivel's with 1 frame length (10 bits for 8-bit data, 11 for9-bit). The software protocol should provide the idletime between messages.By setting this bit, the MCU stops data receive till thenext message. The receive of consecutive "I" with oneframe length wakes up and clears this bit and then theMCU restarts receive operation. However, the RE flagshould be already set before setting this bit. In theclocked synchronous mode WU is not available, so thisbit should not be set.Bit 1 TE Transmit EnableWhen this bit is set, transmit data will appear at port2, bit 4 after one frame preamble in asynchronous mode,while in clocked synchronous mode appear immediately.This is executed regardless of the value of the correspondingDDR. When TE is cleared, the serial I/Odoesn't affect port 2, bit 4.Bit 2 TIE Transmit Interrupt EnableWhen this bit is set, an internal interrupt (IRQ3) isenabled when TDRE (bit 5) is set. When cleared, theinterrupt is inhibited.Bit 3 RE Receive EnableWhen set, a signal is input to the receiver from port2, bit 3 regardless of the value of the DDR. When REis cleared, the serial I/O doesn't affect port 2, bit 3.Bit 4 RIE Receive Interrupt EnableWhen this bit is set, an internal interrupt, IRQ3 isenabled when RDRF (bit 7) or ORFE (bit 6) 'is set.When cleared, the interrupt is inhibited.Bit 5 TORE Transmit Data Register EmptyTDRE is set when the TDR is transferred to thetransmit data shift register in the asynchronous mode,while in clocked synchronous mode when the TDSR is"empty". This bit is reset by reading the TRCSR andwriting new transmit data to the transmit data register.TDRE is set to "1" during reset.Bit 6 ORFE Overrun Framing ErrorORFE is set by hardware when an overrun or a framingerror is generated (during data receive only). Anoverrun error occurs when new receive data is ready tobe transferred to the RDR during RDRF still being set.A framing error occurs when a stop bit is "0". But inclocked synchronous mode, this bit is not affected. Thisbit is cleared when reading the TRCSR, then the RDR,or during reset.Bit 7 RDRF Receive Data Register FullRDRF is set when the RDSR is transferred to theRDR. Cleared when reading the TRCSR, then the RDR,or during reset.(Note) When a few bits are set between bit 5 to bit 7 in theTRCSR, a read of the TRCSR is sufficient for clearingthose bits. It is not necessary to read the TRCSR everytimeto clear each bit.• Transmit Rate/Mode Control Register (RMeR)The RMCR controls the following serial I/O:• Baud Rate• Clock Source• Data Format• Port 2, Bit 2 FunctionIn addition, if 9-bit data format is set in the asynchronousmode, the 9th bit is put in this register. All bits are readable andwritable except bit 7 (read only). This register is set to $00during reset.Transfer Rate/Mode Control RegisterI ROB' TDB' 552' CC21 CCl I76543210cco I 551 , 550 1$0010Bit °Bit 1Bit 5SSO}SSlSS2Speed SelectThese bits control the baud rate used for the SCI. Table8 lists the available baud rates. The timer I FRC (SS2=0) andthe timer 2 up counter (SS2=1) provide the internal clock to theSCI. When selecting the timer 2 as a baud rate source, it functionsas a baud rate generator. The timer 2 generates the baudrate listed in Table 9 depending on the value of the TCONR.(Note) When operating the SCI with internal clock, do notperform write operation to the timer/counter which isthe clock source of the SCI.Bit 2Bit 3Bit 4CCO}CClCC2Clock Control/Format Select*These bits control the data format and the clock source(refer to Table 10).* CCO, CCI and CC2 are cleared during reset and the MCUgoes to the clocked synchronous mode of the externalclock operation. Then the MCU forces port 2, bit 2in the clock input state. When using port 2, bit 2 as anoutput port, the DDR of port 2 should be set to "I" andCCI and CCO to "0" and "1" respectively.~HITACHI 305

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------(1) Asynchronous ModeTable 8 SCI Bit Times and Transfer RatesXTAL I 2.4576MHz I 4.0MHz 4.9152MHzSS2 SS1 SSO E I 614.4kHz i 1.0MHz 12288MHz0 0 0 E..,..16I26 i lS/38400BaudI16,us/62500Baud13"S/76800Baud0 0 1 E..,..128I 208,us.4800Baud 128"S/7812.5Baud 104.2"S/9600Baud0 0 E.,..10241.67ms 600Baud 1.024ms/976.6Baud 833.3,us/1200Baud!0 E..,..4096 6.67ms,150Baud 4.096ms/ 244. 1 Baud 3.333ms/300BaudIi * * ** When SS2 is "I", Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N.Baud Ratef32 (N+l)(f: input clock frequency to the)timer 2 counterN=O -255(2) Clocked Synchronous Mode *XTAL 4.0MHz I 6.0MHz 8.0MHzSS2 SS1 SSO E 1.0MHz i1.5MHz 2.0MHz0 0 0 E""'2 2,us/bit0 0 1II1.33,us/bit1,usibitE..,..16 16,us/bit 10.7,us/bit 8,us/bit0 1 0 E+128 128,us/bit 85.3,us/bit 64,us/bit0 1 1IE""'512 512,us/bit341,us/bit256,us/bit1 - --I** I ** *** Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock isoperatable up to DC - 1/2 system clock.** The bit rate is shown as follows with the TCONR as N.Bit Rate (~s/bit) = 4 (~+1)f: input clock frequency to the)timer 2 counter(N = 0-255Table 9 Baud Rate and Time Constant Register Example2.4576MHzBaud~Rate (Baud3.6864MHz 4.0MHz 4.9152MHz110 21- 32- 35- 43-150 127 191 207 255300 63 95 103 127600 31 47 51 631200 15 23 25 312400 7 11 12 154800 3 5 - 79600 1 2 - 319200 0 - - 138400 - - - 0• E/8 clock is input to the timer 2 up counter and E clock otherwise.8.0MHz70-51-207103512512---306~HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XOTable 10 SCI Format and Clock Source ControlCC2 CCl CCO Format Mode0 0 0 B·bit data Clocked Synchronous0 0 1 8-bit data Asynchronous0 1 0 8-bit data Asynchronous0 1 1 a-bit data Asynchronous1 0 0 a-bit data Clocked Synchronous1 0 1 9-bit data Asynchronous1 1 0 9-bit data Asynchronous1 1 1 9-bit data Asynchronous• Clock output regardless of the TRCSR, bit RE and TE .•• Not used for the SCI.Clock SourceExternalInternalInternalExternalInternalInternalInternalExternalPort 2, Bit 2 Port 2, Bit 3 I Port 2, Bit 4InputNot Used**When the TRCSR, RE bit is "1",Output*bit 3 is used as a serial input.Input>OutputNot Used**Output*InputWhen the TRCSR, TE bit is "1",bit 4 is used as a serial output.Bit 6 TDa Transmit Data Bit aWhen selecting 9·bit data fonnat in the asynchron·ou·s mode, this bit. is transmitted as the 9th data. Intransmitting 9-bit data, write the 9th data into this bitthen write data to the receive data register.Bit 7 RDa Receive Data Bit aWhen selecting 9-bit data format in the asynchronousmode, this bit stores the 9th bit data. In receiving 9·bitdata, read this bit then the receive data register.• TIMER, SCI STATUS FLAGTable 11 shows the set and reset conditions of each statusflag in the timer 1 , timer 2 and SCI.Table 11 Timer 1, Timer 2 and SCI Status FlagSet ConditionReset ConditionICF FRC ~ ICR by edge input to P 20 • 1. Read the TCSR 1 or TCSR2 then ICRH,when ICF=l2. R£S=0OCFl OCR1=FRC 1. Read the TCSR 1 or TCSR2 then write to theOCR1H orOCRll,when OCF1=12. R£S=0Timer1 OCF2 OCR2=FRC 1. Read the TCSR2 then write to the OCR2H orOCR2l, when OCF2=12. m=OTOF FRC=$FFFF+1 cycle 1. Read the TCSRl then FRCH, when TOF=l2. rn=OTimer CMF T2CNT=TCON R 1. Write "0" to CM F , when CM F = 12 2. rn=ORORF Receive Shift Register ~ ROR 1. Read the TRCSR then ROR, when RORF=l2. R"ES=OORFE 1. Framing Error (Asynchronous Mode) 1. Read the TRCSR then ROR, when ORFE=lStop Bit= 02. Overrun Error (Asynchronous Mode)2. RES=OReceive Shift Register ~ ROR whenSCIRORF=lTORE 1. Asynchronous Mode Read the TRCSR then write to the TOR,TOR ~ Transmit Shift Registerwhen TORE=l2. Clocked Synchronous ModeTransmit Shift Register is "empty"3. FfES=o(Notel 1. ~; transfer2. For example; "ICRH" means High byte of ICR.~HITACHI 307

Il0l11I&I.-----"""""1J~HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------• LOW POWER DISSIPATION MODEThe HD630lXO provides two low power dissipation modes;sleep and standby.• SleepModeThe MCU goes to the sleep mode by SLP instruction execution.In the sleep mode, the CPU stops its operation, while theregisters' contents are retained. In this mode, the peripheralsexcept the CPU such as timers, SCI etc. continue their functions.The power dissipation of sleep-condition is one fifth thatof operating condition.The MCU returns from this mode by an interrupt, RES orSTBY; it goes to the reset state by RES and the standby modeby STBY. When the CPU acknowledges an interrupt request, itcancels the sleep mode, returns to the operation mode andbranches to the interrupt routine. When the CPU masks thisint~rrupt, it cancels the sleep mode and executes the nextinstruction. However, for example if the timer 1 or 2 prohibitsa timer interrupt, the CPU doesn't cancel the sleep mode becauseof no interrupt request.This sleep mode is effective to reduce the power dissipationfor a system with no need of the HD630IXO's consecutiveoperation.• Standby ModeThe HD630lXO stops all the clocks and goes to the resetstate with STBY "low. In this mode, the power diSsipation isreduced conspicuously. All pins except for the power supply,the STBY and XT AL are detached from the MCU internallyand go to the high impedance state.In this mode the power is supplied to the HD630IXO, sothe contents of RAM is retained. The MCU returns from thismode during reset. The followings are typical usage of thismode.Save the CPU information and SP contents on RAM by NMI.Then disable the RAME bit of the RAM control register and setthe STBY PWR bit to go to the standby mode. If the STBYPWR bit is still set at reset start, that indicates the power issupplied to the MCU and RAM contents are retained properly.So system can restore itself by returning their pre-standby informationsto the SP and the CPU. Fig. 24 depicts the timing ateach pin with this example.VeeHD6301XOI....-11111 -----If ...-J-----11: II 1111111 ( r::I 1 I~ oIEosc·llla~tloro Save Registerso RAM/Port 5 ControlStart TimeRegister Set ~RestartFigure 24 Standby Mode Timing• TRAP FUNCTIONThe CPU generates an interrupt with the highest priority(TRAP) when fetching an undefmed instruction or an instructionfrom non-memory space. The TRAP prevents the systemburstcaused by noise or a program error.• Address ErrorWhen an instruction fetch is made excluding internal ROM,RAM and external memory area, the MCU generates an interruptas well as an op code error. But on the system with nomemory in its external memory area, this error processing is notapplicable if an instruction fetch is made from the external nonmemoryarea. Table 12 provides addresses where an addresserror occurs to each mode.This processing is available only for an instruction fetch andis not applicable to the access of normal data read/write.• Op Code ErrorWhen fetching an undefmed op code, the CPU saves CPUregisters as well as a normal interrupt and branches to the TRAP($FFEE, $FFEF). This provides the priority next to reset.308 ~HITACHITable 12 Addresses Applicable to Address ErrorsMode 1 2 3$0000 $0000 $00001 1 1Address $OOlF $OOlF $003F$01001$EFFF

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO(Note) The TRAP interrupt provides a retry function differentlyfrom other interrupts. This is a program flow returnto the address where the TRAP occurs when a sequencereturns to a main routine from the TRAP interruptroutine by RTI. The retry can prevent the system burstcaused by noise etc.However, if another TRAP occurs, the program repeatsthe TRAP interrupt forever, so the consideration isnecessary in programming.• INSTRUCTION SETThe HD6301XO provides object code upward compatiblewith the HD6801 to utilize all instruction set of theHMCS6800. It also reduces the execution times of key instructionsfor throughput improvement.Bit manipulation instruction, change instruction of theindex register and accumulator and sleep instruction are alsoadded.The followings are explained here.• CPU Programming Model (refer to Fig. 25)• Addressing Mode• Accumulator and Memory Manipulation Instruction(refer to Table 13)• New Instruction• Index Register and Stack Manipulation Instruction(refer to Table 14)• Jump and Branch Instruction (refer to Table 15)• Condition Code Register Manipulation(refer to Table 16)• Op Code Map (refer to Table 17)• Programming ModelFig.25 depicts the HD6301XO programming model. Thedouble accumulator D consists of accumulator A and B, sowhen using the accumulator D, the contents of A and Baredestroyed.E A °U 7 8 j 8·B,. Accumulo'.n A ond B,,- - - - - - - - 0 - - - - - - - - ~ Or 16·81. Double Accu""ul.~or 01.5 01Inde.ReglS'If tXtI"SP 0 SllItk Po,nter IS')11'5PC 0 Progr.m Count ... fPCI17 0~' H I N Z V C Condllton Code Reg.slet' leeR)earry/Borrow trom MSBOverflowZ ...NeIIllweInterruptHat. Carry IFromBltllFigure 25 CPU Programming Model• CPU Addressing ModeThe HD6301XO provides 7 addressing modes. The addressingmode is decided by an instruction type and code. Table 13through 17 show addressing modes of each instruction withthe execution times counted by the machine cycle.When the clock frequency is 4 MHz, the machine cycle timebecomes microseconds directly.Accumulator (ACCX) AddressingOnly an accumulator is addressed and the accumulator A orB is selected. This is a one-byte instruction.Immediate AddressingThis addressing locates a data in the second byte of aninstruction. However, LDS and LDX locate a data in the secondand third byte exceptionally. This addressing is a 2 or 3-byteinstruction.Direct AddressingIn this addressing mode, the second byte of an instructionshows the address where a data is stored. 256 bytes ($0through $255) can be addressed directly. Execution timescan be reduced by storing data in this area so it is recommendedto make it RAM for users' data area in configurating a system.This is a 2-byte instruction, while 3 byte with regard to AIM,OIM, ElM and TIM.Extended AddressingIn this mode, the second byte shows the upper 8 bit of thedata stored address and the third byte the lower 8 bit. Thisindicates the absolute address of 3 byte instruction in thememory.Indexed AddressingThe second byte of an instruction and the lower 8 bit of theindex register are added in this mode. As for AIM, OIM, ElMand TIM, the third byte of an instruction and the lower 8 bitsof the index register are added.This carry is added to the upper 8 bit of the index registerand the result is used for addressing the memory. The modifiedaddress is retained in the temporary address register, so the contentsof the index register doesn't change. This is a 2-byteinstruction except AIM, OIM, ElM and TIM (3-byte instruction).Implied AddressingAn instruction itself specifies the address. That is, theinstruction addresses a stack pointer, index register etc. This is aone-byte instruction.Relative AddressingThe second byte of an instruction and the lower 8 bits ofthe program counter are added. The carry or borrow is added tothe upper 8 bit. So addressing from -126 to +129 byte of thecurrent instruction is enabled. This is a 2-byte instruction.(Note) CLI, SEI Instructions and Interrupt OperationWhen accepting the IRQ at a preset timing with the helpof CLI and SEI instructions, more than 2 cycles arenecessary between the CLI and SEI instructions. Forexample, the following program (a) (b) don't accept theIRQ but (c) accepts it.CLISEI(a)CLINOPSEI(b)CLINOPNOPSEIThe same thing can be said to the TAP instructioninstead of the CLI and SEI instructions.(c)~HITACHI 309

HD6301XO,HD63A01XO,HD63B01XO----------------------------------------------Table 13 Accumulator, Memory Manipulation InstructionsCondition CodeAddressing ModesRegisterOperations Mnemonic ~----~----- ~------ --------- Boolean/IMMED DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - # OP - # OP - # OP - - # OP # H I N Z V CAdd ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-+ A l l t t t-1-- - I-ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-+B l --t t t tAdd Double ADDD C3 3 3 03 4 2 E3 5 2 F3 5 3 A:B+M:M+l-+A:B---· t t t tAdd Accumulators ABAlB ~-I-;- A + B--+ A l t irr rr-Add With Carry AOCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A t t t t tAOCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-B t --- -.-t t t tAND ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A'M-+A l t RANDB C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M- B a t t R Bit Test BIT A 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M t t R BIT B C5 2 2 05 3 2 E5 4 2 ' F5 '4 3 B·M l t RClear CLR 6F 5 2 7F 5 3 00- M R S R · RCLRA 4F ~ ~~O-+A R S R R"-- - r---CLRB SF 1 1 ·OO·~ 8 R S R RCompare CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3- f--- A-M t t t I-lCMPB Cl '2 2 01 3 2 El 4 2 Fl 4 3 B-M t t l t-+-I--f----- I--CompareCBA 11 1 1 A-BAccumulatorst t t t-Complement, l's COM 63 6 2 73 6 3 M-~ M Rt t 1--1-- SCOMA "43-I-- 1 1 --6--- A-+A Rt t SCOMB 53 1 1 B -+B t t R SComplement, 2's NEG 60 6 2 70 6 3 OO-M-+M t t (!)~(Negate) NEGA 40 1 1 OO-A-+A t t (i)@)NEGB 50 1 1 OO-B-+B t t (j)@)Converts binary add of BCDDecimal Adjust, A DAA 19 2 1 characters into BCD format-- t t t @--I-- ~-Decrement DEC 6A 6 2 7A 6 3 M -1-+M t t @ • -DECA 4A 1 1 A-I -+ A t t @ •-OECB SA 1 1 B-l-+B t l ~ .1---Exclusive OR EORA 88 2 2 98 3 2 A8 4 2 B8 4 3 A~M-+ARt t EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 B ~ M-+ B ·t t R ---I--~.Increment INC 6C 6 2 7C 6 3 M+l -+M t t @ •INCA 4C 1 1 A + 1 -+ A t t @ •INCB 5C 1 1 8 + 1-+ B t t @ •Load LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-+A t t R -~-------AccumulatorLOAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M -+ B t t R Load DoubleLDO CC 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1 -+ B, M-+ A l t RAccumulator·Multiply Unsigned MUL 30 7 1 AxB-+A:BI- ·· • @~-1--1-----OR, Inclusi\ltl ORAA 8A 2 2 9A 3 2 AA 4 BA 4 3 A+M-+A t t R ORAB CA 2 2 OA 3 2 EA 4 2 FA 4 3 B +M-~ B t t RPush Data PSHA 36 4 1 A -+ Msp, SP - 1 -+ SP · ·PSHB 37 4 1 B -+ Msp, SP - 1 -+ SP·····:}~IIIIII ·· t t @ tPull Data PULA 32 3 1 SP + 1 -+ SP. Msp -+ APULB 33 3 1 SP + 1-+ SP. Msp-+ B Rot.te Left ROL 69 6 2 79 6 3ROLA 49 1 1 1i

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XOTable 13 Accumulator, Memory Manipulation InstructionsOper8tioMMnemonicAddressing ModesIMMED DIRECT INDEX EXTEND IMPLIEDBoolean/Arithmetic OperationCondition CodeRegister5 4 3 2 1 0OP - # OP - # OP - # OP - # op -# H I N Z V CShift Left ASL 68 6 2 78 6 3M} _ · . t t @tArithmeticASLA 48 1 1 A ~ I I I I I I I 1+ 0 ·ASLB 58 1 1B C b7 bO·Doubl. ShiftLeft, Arithmetic A7 AO B7 BOASLO 05 1 1 9'l ACC~ B 1+-0··. t t t· t t~ tt t~ ttt 6 t· t t 6 tt 6 tt @tt@tShift Right ASR 67 6 2 77 6 3~} r;c I llili I ~ · t t 6 tArithmeticASRA 47 1 1B b7 bO CASRB 57 1 1Shift Right LSR 64 6 2 74 6 3 M} _ RLoglcIIlLSRA 44 1 1 Ao~llllillr9 RLSRB 54 1 1R Double ShiftLSRO 04 1 1 0-.1 ACC AI Ace B t-.(J RRight Logical t kID tStore STAA 97 3 2 A7 4 2 B7 4 3 A-M t t R Accumul8torSTAB. 07 3 2 E7 4 2 F7 4 3 B_M t t R Store DoubleA_MSTO 00 4 2 EO 5 2 FO 5 3B _ M+1Accumulator·· ·t t RB b7 bOSubtract SUBA 80 2 2 90 3 2 AO 4 2 80 4 3 A-M _A·A7 AO B7 BO CSUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B -M-BDouble Subtract SUBO 83 3 3 93 4 2 A3 5 2 B3 5 3 A:B-M:M+1-A:B SubtractSBA 10 1 1 A-B- AAccumul8tors Subtract SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C-AWith carrySBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-B ··Trenlfer TAB 16 1 1 A-BAccumulatorsTBA 17 1 1 B .... A·Tilt Zero or TST 60 4 2 70 4 3 M-OOMinulTSTA 40 1 1 A -00TST8 50 1 1 B - 00·t t t tt t t tt t t tt t t tt t t tt t t tt t R ·t t R· t t R Rt t R Rt t R RAnd Immediate AIM 71 6 3 61 7 3 M.IMM~M• t t R •OR Immediate OIM 72 6 3 62 7 3 M+IMM~M e I t R EOR Immediate ElM 75 6 3 65 7 3 MEBIMM~M I I R Test Immediate TIM 7B 4 3 6B 5 3 M·IMM• • t I R •(Note) Condition Code Register will be explained in Note of Table 16 .• Additional InstructionIn addition to the H06801 instruction set, the HD630lXOprepares the fonowing new instructions.AIM •...•. , (M)o(IMM) ... (M)Executes "AND" operation to immediate data and thememory contents and stores its result in the memory.OIM . . . • . . . (M) + (IMM) ... (M)Executes "OR" operation to immediate data and thememory contents and stores its result in the memory.ElM • • • • . • . (M) (IMM) ... (M)Executes "EaR" operation to immediate data and thememory contents and stores its result in the memory.TIM . . . . . . . (M). (IMM)Executes "AND" operation to immediate data andchanges the relative flag of the condition code register.These area 3-byte instructions; the first byte is op code, thesecond immediate data and the third address modifier.XGDX ..... (ACCD) ~ (IX)SLPExchanges the contents of accumulator and the indexregister.Goes to the sleep mode. Refer to "LOW POWER DIS­SIP ATION MODE" for more details of the sleep mode.~HITACHI 311

Pointer OperationsTable 14 Index Register, Stack Manipulation InstructionsAddressing ModesBooleanlMnemonic IMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic OperationCondition CodeRegister5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V Ct : tCompare Index Reg CPX 81*3 3 9C 4 2 AC 5 2 BC 5 3 X-M:M+1~----------~~--~~----- - ~ -4---~~~~--~~~~~--------~+-~+-+-+--Decrement Index Reg DEX t 09 1 1 X - 1 ... X·___ ~ .1--- ___ --f---f-- ~~'_-~i-_14f---1 +s-P=-~=1="'.~S.~P========~=~=~=~~~~~~~Decrement Stack Pntr ~E-S-._ +. --~-t---t-Increment Index Reg INX j --1-- 08 . 1 1 X + 1'" XIncrement Stack Pntr INS --- 1--- I !--- --- - --+--j.-.,>----+,--+---I-3...,.1+1+-1+SP::-+-:-1....--=-SP=-------+-+-+-~Hf-------~.--------~ - !--- .~~+_c~-+-4~~~--~~--~-4--~~~~+--Load Index Reg LOX 'CEj3 3 DE 42 EE 5 2 FE 5 3 M ... XH,(M+lI'"XL (j) t R~''''~---lOS . 1:9= tit ~~ ~t2='_ +T-E+f--.;:..5-+l-.::..2-+-=-B~E~-~5~~3~~-=-~~~~-=-~M-=-- ... _--=S~P.!.:H'2.-=~, -(_M-=-+-=-1-~)- ... _-.::..S-!!P~:...L~-:f-.-_+i--_+:':::..-!-+.:...:...-!-+-.:...4.;---_+i9~ ~ T A~ ~ 2_ ~~ _ ~ 3 SPH ... ~, SPL-"'-(::M 7 +-:";1 )+-+-+~-:-+-::-+-§'Store Index Reg STX 'OF 4_+~ EF 5 2 FF 5 3 XH"'M XL"'(M+1)Store Stack Pntr STS _Index Reg ... Stack Pntr f---"!:.~~ __ t- _ _ --~----+----1--++--+- 35 1 1 X - 1'" SPStack Pntr ... Inde" R~ ~~_ ~_ f-- _~---.~~~=1-=-3:::0~1~11~1~~S:--P;;-:--:--+;1= ...Add A~)( __ _ --I--f-- _1-_1-_ ++-+ __ +--+-+-=-3A-+.::..1 +-1-+=-B_+_X_ ... __Push Data PSHX 3C 5 1 XL'" M .., SP - 1 ... SPXH'" M ..,SP -1'" SPPull DataPULX38 4 1 SP + 1 ... SP, Mop ... X HSP + 1'" SP,M .. '" XLExchangeXGDX(Note) Condition Code Register will be explained in Note of Table 16.18 2 1 ACCD··IX1 • • t I. ·· t · (f) t R (f).'. t R (/" t R · ···· ··.....• •••••~-:-X::--------:..----------1+--·~;·~;·~t·~t·=t·=X _____---+_.+.+.-+.-+.-+._Table 15 Jump, Branch InstructionAddressing Modes()perations MnemonicRELATIVE DIRECT INDEX EXTEND IMPLIEDBranch TestOP - - - - - # OP # OP # OP # OP #Branch Always BRA 20 3 2 I NoneBranch Never BRN 21 3 2 NoneBranch If Carry Clear BCC 24 3 2 C=OBranch If Carry Set BCS 25 3 2 C=lBranch If - Zero BEQ 27 3 2 Z = 1Branch If ;. Zero BGE 2C 3 2 NGlV-OBranch If > Zero BGT 2E 3 2 Z + (N Gl VI = 0Branch If Higher BHI 22 3 2 C+Z=OBranch If < Zero BLE 2F 3 2 Z + iN Gl VI· 1Branch If Lower OrSameBLS 23 3 2 . I C+Z=1Branch If < Zero BLT 20 3 2 NGlV=1Branch If Minus BMI 2B 3 2 N -1Branch If Not EqualZeroBNE 26 3 2 Z=OBranch If OverflowClearBVC 28 3 2 V-OBranch If Overflow Set BVS 29 3 2 V= 1Branch If Plus BPL 2A 3 2 N-OBranch To Subroutine BSR 80 5 2Jump JMP 6E 3 2 7E 3 3Jump To Subroutine JSR 90 5 2 AD 5 2 BD 6 3No Operation NOP 01 1 1Advances. Prog. Cntr.OnlyReturn From Interrupt RTI 3B 10 1Return FromSubroutineRTS 39 5 1Software Interrupt SWI 3F 12 1Weit for InterrUPt- WAI 3E 9 1Sleep SLP 1A 4 1(Note) * WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.Condition Code Register will be explained in Note of Table 16.Condition CodeRegister5 4 3 2 1 0H I N Z V C······.-· ······--@ --· S· · ev· ···• • • • • •312~HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XOTable 16 Condition Code Register Manipulation InstructionsClear CarryOperationsClear Interrupt MaskClear OverflowSet earrySet Interrupt MaskSet OverflowAccumulator A- CCAMnemonicClCCliClVSECSEISEVTAPCCA - Accumulator A TPA\AddressingModesIMPLIEDOP - #OC 1 1OE 1 1OA 1 100 1 1OF 1,OB 1 106 1 107 1 1LEGENDOP Operation Code (Hexadecimal)Number of MCU CyclesMsp Contents of memory location pointed to by Stack Pointer# Number of Program Bytes+ Arithmetic PlusArithmetic Minus• Boolean AND+ Boolean Inclusive ORBoolean Exclusive OReM Complement of M~ Transfer intoOBit = Zero00 Byte = ZeroBoolean Operation 5 4 3Condition Code Aegister· ·H I N Z V CO-C0-1 AO-V 1 - C A SI-I SI-V · A- CCA ---·· S@· ---·CCA - A·· ·CONDITION CODE SYMBOLSH Half-carry from bit 3 to bit 4I Interrupt maskN Negative (sign bit)Z Zero (byte)V Overflow, 2's complementC Carry/Borrow from Ito bit 7R Reset AlwaysS Set Alwayst Set if true after test or clear• Not Affected· ·A2 1 0· · ·(Note) Condition Code Register Notes: (Bit set if test is true and cleared otherwise)CD (Bit V) Test: Result = 100000007@ (Bit C) Test: Result ~ 000000007@ (Bit C) Test: BCD Character of high-order byte greater than 107 (Not cleared if previously set!@ (Bit V) Test: Operand = 10000000 prior to execution?® (Bit V) Test: Operand = 01111111 prior to execution 7® (Bit V) Test: Set equal to N

HD6301 XO,HD63A01XO,HD63B01XO----------------------• CPU OPERATION• CPU Instruction FlowWhen operating, the CPU fetches an instruction from amemory an~ecutes the required function. This sequencestarts with RES cancel and repeats itself limitlessly if notaffected by a special instruction or a control Signal. SWI, RTI,WAf and SLP instructions are to change this operation, whileNMI, IRQ1, IRQl, IRQ3, HALT and STBYare to control it.Fig. 26 gives the CPU mode transition and Fig. 27 the CPUsystem flow chart. Table 18 shows CPU operating states andport sta tes.• Operation at Each Instruction CycleTable 19 provides the operation at each instruction cycle.By the pipeline control of the HD6301XO, MULT, PUL, DAAand XGDX instructions etc. pre fetch the next instruction. Soattention is necessary to the counting of the instruction cyclesbecause it is different from the existent one·····op code fetchto the next instruction op code.Table 18 CPU Operation State and Port StatePort Mode Reset STBy· .. •Port 1 Mode 1,2 HlAo -A7 ) Mode 3 TPort 2Mode 1,2Mode 3Port 3 Mode 1,2(Do -0 7 ) Mode 3Port 4 Mode 1,2 HIA •. -A IS ) Mode 3 TMode 1,2Port 5 T TMode 3Port 6Port 7TTMode 1,2TMode 3Mode 1,2 .Mode 3 TH; High, L; Low, T; High Impedance• RD,WR,RIW,LlR=H,BA=LRD, WR, RIW-T, LIR, BAcHHALT is unacceptable in mode 3.E pin goes to high impedance state.TTTTTTHALT"·---T----KeepTTT----------Keep---..SleepHKeepKeepTKeepHKeepTKeep.KeepFigure 26 CPU Operation Mode Transition314_HITACHI

PC.IXACCA~:t:~():t:-(Note)1. The program sequence will come to the RES start fromany place of the flow during RES. When STBY=O. thesequence will go into the standby mode regardless of the CPUcondition.2. Refer to "FUNCTIONAL PIN DESCRIPTION" for moredetails of interrupts.~C1INFigure 27 HD6301XO System Flow Chart::r:o0)(,Jo~XP::r:o0)(,J»oX,0::r:o0)(,JO:Jo~Xo

HD6301XO,HD63A01XO,HD63B01XO----------------------Table 19 Cycle-by-Cycle OperationAddress Mode &InstructionsAddress BusData BusIMMEDIATEADC ADDAND BITCMP EORLOA ORASBC SUBADDD CPXLDD LDSLDX SUBD21213 23Op Code Address + 1 1I 0Op Code Address + 2 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0 iOp Code Address + 3 1 0 II1 1 Operand Data1 0 Next Op Code1 1 Operand Data (MSB)1 1 Operand Data (LSB)1 0 Next Op CodeDIRECTADCANDCMPLDASBCSTAADDDLDDLDXSTDSTXJSRTIMAIMOIMADDBITEORORASUBCPXLDSSUBDSTSElM123 313 231243412434125 345124341236456IOp Code Address + 1 1 0Address of Operand 1 0Op Code Address + 2 1 0Op Code Address + 1 1 0Destination Address 0 1Op Code Address + 2 1 0Op Code Address + 1 1 0Address of Operand 1 0Address of Operand + 1 1 0Op Code Address+2 1 0Op Code Address+ 1 1 0Destination Address 0 1Destination Address + 1 0 1Op Code Address+2 1 0Op Code Address+ 1 1 0FFFF 1 1Stack Pointer 0 1Stack Pointer - 1 0 1Jump Address 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0Address of Operand 1 0Op Code Address + 3 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0Address of Operand 1 0FFFF 1 1Address of Operand 0 1Op Code Address + 3 1 01 1 Address of Operand (LSB)1 1 Operand Data1 0 Next Op Code1 1 Destination Address0 1 Accumulator Data1 0 Next Op Code1 1 Address of Operand (LSB)1 1 Operand Data (MSB)1 1 Operand Data (LSB)1 0 Next Op Code1 1 Destination Address (LSB)0 1 Register Data (MSB)0 1 Register Data (LSB)1 0 Next Op Code1 1 Jump Address (LSB)1 1 Restart Address (LSB)0 1 Return Address (LSB)0 1 Return Address (MSB)1 0 First Subroutine Op Code1 1 Immediate Data1 1 Address of Operand (LSB)1 1 Operand Data1 0 Next Op Code1 1 Immediate Data1 1 Address of Operand (LSB)1 1 Operand Data1 1 Restart Address (LSB)0 1 New Operand Data1 0 Next Op Code(Continued)316$ HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XOAddress Mode &InstructionsAddress BusData BusINDEXEDJMPADCANDCMPlOASBCTSTSTAADDDCPXlOSSUBDSTDSTXJSRASlCOMINCNEGRORTIMCLRAIMOIMADDBITEORORASUBlDDlOXSTSASRDEClSRROlElM34455565571 Op Code Address+ 1 12 FFFF 13 Jump Address 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 14 Op Code Address+2 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 04 Op Code Address+2 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 14 IX + Offset + 1 15 Op Code Address+2 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 04 IX+Offset+l 05 Op Code Address+2 11 Op Code Address+l 12 FFFF 13 Stack Pointer 04 Stack Pointer - 1 05 IX + Offset 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 14 FFFF 15 IX + Offset 06 Op Code Address+ 1 11 Op Code Address + 1 12 Op Code Address+2 13 FFFF 14 IX + Offset 15 Op Code Address+3 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 14 IX + Offset 05 Op Code Address + 2 11 Op Code Address+ 1 12 Op Code Address+2 13 FFFF 14 IX + Offset 15 FFFF 16 IX + Offset 07 Op Code Address+3 10 1 1 Offset1 1 1 Restart Address (lSB)0 1 0 First Op Code of Jump Routine0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (lSB)1 0 1 Accumulator Data0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data (MSB)0 1 1 Operand Data (LSB)0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (lSB)1 0 1 Register Data (MSB)1 0 1 Register Data (LSB)0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (lSB)1 0 1 Return Address (lSB)1 0 1 Return Address (MSB)0 1 0 First Subroutine Op Code0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data1 1 1 Restart Address (lSB)1 0 1 New Operand Data0 1 0 Next Op Code0 1 1 Immediate Data0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data1 0 1 000 1 0 Next Op Code0 1 1 Immediate Data0 1 1 Offset1 1 1 Restart Address (lSB)0 1 1 Operand Data1 1 1 Restart Address (lSB)1 0 1 New ·Operand Data0 1 0 Next Op Code(Continued)~HITACHI317

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Address Mode 8.InstructionsAddress BusData BusEXTENDJMP 1 Op Code Address + 1 1 0 1 1 Jump Address (MSB)3 2 Op Code Address + 2 1 0 1 1 Jump Address (LSB)3 Jump Address 1 0 1 0 Next Op CodeADC ADD TST 1 Op Code Address + 1 1 0 1 1 Address of Operand (MSB)AND BIT2 Op Code Address + 2 1 0 1 1 Address of Operand (LSB)4CMP EOR 3 Address of Operand 1 0 1 1 Operand DataLDA ORA 4 Op Code Address + 3 1 0 1 0 Next Op CodeSBC SUBSTA 1 Op Code Address + 1 1 0 1 1 Destination Address (MSB)42 Op Code Address + 2 1 0 1 1 Destination Address (LSB)3 Destination Address 0 1 0 1 Accumulator Data4 Op Code Address+3 1 0 1 0 Next Op CodeADDD 1 Op Code Address + 1 1 0 1 1 Address-otOperand (MSB)CPX LDD 2 Op Code Address + 2 1 0 1 1 Address of Operand (LSB)LDS LDX 5 3 Address of Operand 1 0 1 1 Operand Data (MSB)SUBD 4 Address of Operand + 1 1 0 1 1 Operand Data (LSB)5 Op Code Address + 3 1 0 1 0 Next Op CodeSTD STS 1 Op Code Address + 1 1 0 1 1 Destination Address (MSB)STX 2 Op Code Address + 2 1 0 1 1 Destination Address (LSB)5 3 Destination Address 0 1 0 1 Register Data (MSB)4 Destination Address + 1 0 1 0 1 Register Data (LSB)5 Op Code Address + 3 1 0 1 0 Next Op CodeJSR 1 Op Code Address + 1 1 0 1 1 jump Address (MSB)2 Op Code Address + 2 1 0 1 1 Jump Address (LSB)63 FFFF 1 1 1 1 Restart Address (LSB)4 Stack Pointer 0 1 0 1 Return Address (LSB)5 Stack Pointer - 1 0 1 0 1 Return Address (MSB)6 Jump Address 1 0 1 0 First Subroutine Op CodeASL ASR 1 Op Code Address + 1 1 0 1 1 Address of Operand (MSB)COM DEC 2 Op Code Address + 2 1 0 1 1 Address of Operand (LSB)INC LSR3 Address of Operand 1 0 1 1 Operand Data6NEG ROL 4 FFFF 1 1 1 1 Restart Address (LSB)ROR 5 Address of Operand 0 1 0 1 New Operand Data6 Op Code Address + 3 1 0 1 0 Next Op CodeCLR 1 Op Code Address+ 1 1 0 1 1 Address of Operand (MSB)2 Op Code Address + 2 1 0 1 1 Address of Operand (LSB)5 3 Address of Operand 1 0 1 1 Operand Data4 Address of Operand 0 1 0 1 005 Op Code Address + 3 1 0 1 0 Next Op Code(Continued)318 ~HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XOAddress Mode &InstructionsAddress BusData BusIMPLIEDABAASLASRCLCCLRCOMDESINCINXLSRDRORSBASEITABTBATSTTXSDAAPULAPSHAPULXPSHXRTSMULABXASLDCBACLICLVDECDEXINSLSRROLNOPSECSEVTAPTPATSXXGDXPULBPSHB1234455f---71 Op Code Address + 1 11 Op Code Address+ 1 12 FFFF 11 Op Code Address+ 1 12 FFFF 13 Stack Pointer + 1 11 Op Code Address+ 1 12 FFFF 13 Stack Pointer 04 Op Code Address+ 1 1--1 Op Code Address+ 1 ~"12 FFFF 13 Stack Pointer + 1 14 Stack Pointer + 2 11 Op Code Address+l 12 FFFF 13 Stack Pointer 04 Stack Pointer-l 05 Op Code Address+ 1 11 Op Code "Address+ 1 -- c-----;"2 FFFF 13 Stack Pointer + 1 14 Stack Pointer + 2 15 Return Address 1,- Op Code Address + 1 12 FFFF 13 FFFF 14 FFFF 15 FFFF 16 FFFF 17 FFFF 10 1 0 Next Op Code0 1 0 Next Op Code1 1 1 Restart Address (LSB)0 1 0 Next Op Code1 1 1 Restart Address (LSB)0 1 1 Data from Stack0 1 1 Next Op Code1 1 1 Restart Address (LSB)1 0 1 Accumulator Data0 1 0 Next Op Code0 1 0 Next Op Code1 1 1 Restart Address (LSB)0 1 1 Data from Stack (MSB)0 1 1 Data from Stack (LSB)0 1 1 Next Op Code1 1 1 Restart Address (LSB)1 0 1 Index Register (LSB)1 0 1 Index Register (MSB)0 1 0 Next Op Code0 1 1 Next Op Code1 1 1 Restart Address (LSB)0 1 1 Return Address (MSB)0 1 1 Return Address (LSB)0 1 0 First Op Code of Return Routine0 1 0 Next Op Code1 1 1 Restart Address (LSB)1 1 1 Restart Address (LSB)1 1 1 Restart Address (LSB)1 1 1 Restart Address (LSB)1 1 1 Restart Address (LSB)1 1 1 Restart Address (LSB)(Continued)~HITACHI319

HD6301XO,HD63A01X~HD63B01XO~~~~~~~~~~~~~~~~~~~~~~Address Mode litInstructionsAddress BusData BusIMPLIEDWAIRTISWISLP91012412345 .678912345678910,-2345678910111212rSleep134Op Code Address + 11FFFF 1Stack Pointer 0Star.k Pointer-1 0Stack Pointer - 2 I 0Stack Pointer - 3 0Stack Pointer-4 0Stack Pointer-5 0Stack Pointer - 6 0Op Code Address + 1 1FFFF 1Stack Pointer + 1 1Stack Pointer + 2 1Stack Pointer + 3 1Stack Pointer+4 1Stack Pointer + 5I 1Stack Pointer + 6 1Stack Pointer + 71 1Return Address 1Op Code Address + 1 I 1FFFF 1Stack Pointer 0Stack Pointer - 1 0Stack Pointer - 2 0Stack Pointer - 3 0Stack Pointer-4 0'+... ,,' Po'0",-5 0Vector Address FFFA 1Vector Address FFFB 1Address of SWI Routine 1Op Code Address + 1 1FFFF 11FFFF 1Op Code Address + 1 10 1 1 Next Op Code1 1 1 Restart Address ILSB)1 0 1 Return Address ILSB)1 0 1 Return Address IMSB)1 0 1 Index Register ILSB)1 0 1 Index Register IMSB)1 0 1 Accumulator A1 0 1 Accumulator B1 0 1 Conditional Code Register0 1 1 Next Op Code1 1 1 Restart Address ILSB)0 1 1 Conditional Code Register0 1 1 Accumulator B0 1 1 Accumulator A0 1 1 Index Register IMSB)0 1 1 Index Register ILSB)0 1 1 Return Address IMSB)0 1 1 Return Address ILSB)0 1 0 First OpCode of Return Routine0 1 1 Next Op Code1 1 1 Restart Address ILSB)1 0 1 Return Address ILSB)1 0 1 Return Address IMSB)1 0 1 Index Register (LSB)1 0 1 Index Register (MSB)1 0 1 Accumulator A1 0 1 Accumulator B1 0 1 Conditional Code Register0 1 1 Address of SWI Routine (MSB)0 1 1 Address of SWI Routine (LSB)0 1 0 First Op Code of SWI Routine0 1 1 Next Op Code1 1 1 Restart Address ILSB)1 1 1 I1 1 1 Restart Address ILSB)0 1 0 Next Op CodeRELATIVEBCC BCSBEQ BGEBGT BHIBLE BLSBLT BMTBNE BPLBRA BRNBVC BVSBSR3512312345Op Code Address + 1 I 1FFFF 11 Branch Address······Test=·1·1OpCode Address+1···Test=·O··IOp Code Address + 1 1FFFF 1Stack Pointer 0. Stack Pointer-l 0Branch Address 10 1 1 Branch Offset1 1 1 Restart Address (LSB)0 1 0First Op Code of Branch RoutineNext Op Code0 1 1 Offset1 1 1 Restart Address (LSB)1 0 1 Return Address (LSB)1 0 1 Return Address (MSB)0 1 0 First Op Code of Subroutine320$ HITACHI

HD6301 YO,HD63A01 YO,--­HD63B01YOCMOS MCU (Microcomputer Unit)-ADVANCE INFORMATION-The HD6301 YO is a CMOS 8-bit single-chip microcomputerunit which contains a CPU compatible with the CMOS 8-bitmicrocomputer HD6301Vl, 16k bytes of ROM, 256 bytes ofRAM, 53 parallel I/O pins, Serial Communication Interface(SCI) and two timers.• FEATURES• Instruction Set Compatible with the HD6301 Family• Abundant On-chip Resources• 16k Bytes of ROM, 256 Bytes of RAM• 53 Parallel I/O Pins (48 I/O Pins, 5 Output Pins)• Handshake I nterface (Port 6)• Darlington Transistor Direct Drive (Port 2, 6)• 16-bit Programmable Timer1 I nput Capture Register1 Free Running Counter2 Output Compare Registers• 8-Bit Reloadable Timer1 8·bit Up Counter1 Time Constant Register• Serial Communication InterfaceAsynchronous Mode8 Transmit FormatsHardware ParityClocked Synchronous Mode• Interrupts - 3 External, 7 Internal• CPU Functions• Memory Ready, Auto Memory Ready• Halt• Error Detection(Address Trap, Op-code Trap)• Operation Mode• Mode 1; Expanded Mode(Internal ROM Inhibited)• Mode 2; ~xpanded Mode(Internal ROM Valid)• Mode 3; Single Chip Mode• Up to 65k Bytes Address Space• Low Power Dissipation Mode• Sleep• Standby (HardWare Set, Software Set)• Wide Range of OperationVee = 3 to 6V (f 0: 1 to 0.5 MHz)f = 0.1 to 1.0 MHz; HD6301YO )Vee = 5V ± 10% f = 0.1 to 1.5MHz; HD63A01YO(f = 0.1 to 2.0 MHz; HD63BOl YO• Minimum Instruction Cycle Time; 0.5 J1.s (f = 2.0 MHz)HD6301YOP, HD63A01YOP,HD63B01YOP(DP-64S)HD6301YOF, HD63A01YOF,HD63B01YOF(FP-64)@HITACHI 321

• PIN ARRANGEMENT• HD6301YOP.HD63A01YOP.HD63B01YOPV .. 1 0XTAL ~EXTAL 3MPoMP,RES 8SfiY~;mJ~Pzo 9P"1llP22 IIPu 1p •• 1p .. 1p •• ,P27 ,PIO 1P" ,PI2 1PI3p .. 1p ..p ..P., •PIOP.,p .. 7Pu 8p ..p ..PH~P"(TopViewlP70P711 P72P"P74p.P3,PI2PnP34P3•PH, P"P,OP"PI27 P'3P,.P,.P ..P"V ..1 P40P.,3 P ••3 P'3~P ..p.,~ p ••3 P47gj Vee• HD6301YOF.HD63A01YOF.HD63B01YOF(Top Viewl• BLOCK DIAGRAMP20(Ti" )P2I(TOUI,)P,,(SClK)P23(R. )P2.(T. )P20(Tout.)P2.(Tou!3)P,,(TClK)P30100P3'/O,P32/0.P33/03P3.tO.P35/0.P,./o.P,,/o,Poo(imI, )P5I(imI2 )P02(MR )P03(RArT)Po.OS )Poo(OS )Po.Po,p.op.,p,.p ..p ..P ••p ••P.,P.oIA.P.,jA.P'2/A,oP'3/A"P • .tA,.P.o/A"P •• /A,.P.,/A,.322$ HITACHI

HD6303R, HD63A03R,---­HD63B03RCMOS MPU (Micro Processing Unit)The HD6303R is an 8-bit CMOS micro processing unitwhich has the completely compatible instruction set with theHD6301Vl. 128 bytes RAM, Serial Communication Interface(SCI), parallel I/O ports and multi function timer are incorporatedin the HD6303R. It is bus compatible with HMCS6800 andcan be expanded up to 65k words. Like the HMCS6800 family,I/O levels is TTL compatible with +5.0V single power supply.As the HD6303R is CMOS MPU, power dissipation is extremelylow. And also HD6303R has Sleep Mode and Stand-by Modeas lower power dissipation mode. Therefore, flexible low powerconsumption application is possible.• FEATURES• Object Code· Upward Compatible with the HD6800, HD6801,HD6802• Multiplexed Bus (Do-D 7 /Ao-A 7 ), Non Multiplexed Bus• Abundant On-Chip Functions Compatible with theHD6301V1; 128 Bytes RAM, 13 Parallel I/O Lines, 16-bitTimer, Serial Communication Interface (SCI)• Low Power Consumption Mode; Sleep Mode, Stand-By Mode• Minimum Instruction Execution Time11'5 (f=1MHz), 0.67ps (f=1.5MHz), 0.51ls (f=2.0MHz)• Bit Manipulation, Bit Test Instruction• Error Detecting Function; Address Trap, Op Code Trap• Up to 65k Words Address Space• TYPE OF PRODUCTSType No.HD6303RHD63A03RHD63B03RBus Timing1.0 MHz1.5 MHz2.0 MHzHD6303RP, HD63A03RP,HD63B03RPHD6303RF, HD63A03RF,HD63B03RF(DP-40)(FP-54)H D6303RCG, H D63A03RCG,HD63B03RCG~.~.>•(CG-40)~HITACHI323

HD6303R,HD63A03R,HD63B03R -----------------------• PIN ARRANGEMENT• HD6303RP, HD63A03RP,HD63B03RP0(Top View)EASRMDo/AoD,/A,D,/A,D,/A,D,/A,D./A.D./A.D,/A,A.A.A,oAllA"AllA .. AJ/PI3 22A ..Vee• HD6303RF, HD63A03RF,HD63B03RF....Ii Ii ~ ~ ::l",I~ ~_ z w X > w~~~~u««O,/A,O,/AJO./A.D./A.D./A.• HD6303RCG, HD63A03RCG,HD63B03RCGL~J L;J L~J ~~J Lc:;J ~~ L~ l;: t~J :"~JD,/A, ~~ [~~ A'2~~ A13[2~ A'4[2:2 A,s[~1 Vee[~O A7/P17[I,? As/P,sD:S As/P,s~J [lz A4/p'4~J D~ Aa/P13r~i r':::'l r~l r~1 r~l f=1 r~l r~l r:!~ r~1~ ~ f f l f f ~ i {en ~ ~

-----------------------HD6303R,HD63A03R,HD63B03R• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee -0.3 ~ +7.0 VInput Voltage Yin -0.3 ~ Vee+0.3 VOperating Temperature Top. O~ +70 °cStorage Temperature Tstg -55 ~+150 °c(NOTE)This product has protection circuits in input terminal from high static electricity voltage and high electric field.But be careful not to apply overvoltage more than maximum ratings to these high input impedance protectioncircuits. To assure the normal operation, we recommend Vin, V out : VSS ;:;; (Vin or V out) ~ Vee.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vcc = 5.0V±10%, Vss = OV, Ta = O~+70°C, unless otherwise noted.)Item Symbol Test Condition min typ maxRES, STBY Vee-0.5 -VeeInput "High" Voltage EXTAL V 1H VeexO.7 -+0.3Other Inputs 2.0 -Input "Low" Voltage All Inputs V 1L -0.3 - 0.8Input Leakage Current NMI, IRQ" RES, STBY II in I Yin =0.5~Vee-0.5V - - 1.0Three State (off-state)Leakage CurrentPlO~P17' P20~P24'Do~D7. A8~A'5Output "High" Voltage All Outputs V OHilTSli Yin =0.5~Vee-0.5V - - 1.0IOH = -200p.A 2.4 - -IOH = -10p.A Vee- 0.7 - -Output "Low" Voltage All Outputs VOL IOL = 1.6mA - - 0.55Input Capacitance All Inputs CinVin=OV, f=1.0MHz,Ta = 25°C- - 12.5St

• AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)BUS TIMINGTest HD6303R HD63A03R HD63B03RItem Symbol Con- Unitdition min typ max min typ max min typ maxCycle Time t cvc 1 - 10 0.666 - 10 0.5 - 10 IlSAddress Strobe Pulse WidthPWASH 220 150 110"High" - - - - - - nsAddress Strobe Rise Time tASr - - 20 - - 20 - - 20 nsAddress Strobe Fall Time tASf - - 20 - - 20 - - 20 nsAddress Strobe Delay Time tASO 60 - - 40 - - 20 - - nsEnable Rise Time tEr - - 20 - - 20 - - 20 nsEnable Fall Time tEf - - 20 - - 20 - - 20 nsEnable Pulse Width "High" Level PWEH 450 - - 300 - - 220 - - nsEnable Pulse Width "Low" Level PWEL 450 - - 300 - - 220 - - nsAddress Strobe to Enable DelayTimeAddress Delay Timet ASEO60 - - 40--- - 20 - - nst A01 - - 250 - - 190 - - 160 nst Ao2 Fig. 1 - - 250 - - 190 - - 160 nsAddress Delay Time for Latch tAOL Fig. 2 - - 250 - - 190 - - 160 nsData Set-up TimeData Hold TimeWrite tosw 230 - - 150 - - 100 - - nsRead tOSR 80 - - 60 - - 50 - - nsRead tHR 0 - - 0 - - 0 - - nsWrite tHW 20 - - 20 - - 20 - - nsAddress Set-up Time for Latch tAS L 60 - - 40 - - 20 - - nsAddress Hold Time for Latch tAHL 30 - - 20 - - 20 - - nsAddrtss Hold Time tAH 20 - - 20 - - 20 - - nsAo ..... A7 Set-up Time Before E tASM 200 - - 110 - - 60 - - nsI Non-Multiplexed (tACCN) - - 650 - - 395 - - 270 nsPeripheral ReadBusAccess Time IMultiplexed Bus (tACCM) - - 650 - - 395 - - 270 nsOscillator stabilization Time tRC Fig.8 20 - - 20 - - 20 - - msProcessor Control Set-up Time tpcs Fig.9 200 - - 200 - - 200 - - nsPERIPHERAL PORT TIMINGPeripheral Data.Set-up TimePeripheral DataHold TimeTest HD6303R HD63A03R HD63B03RItem Symbol Con- Unitdition min typ max min typ max min typ maxPort 1,2 tposu Fig. 3 200 - -200 - - 200 - - nsPort 1,2 tpOH Fig. 3 200 - - 200 - - 200 - - nsDelay T;me. Enable Neg'-I Port 1tive Transition to Peri- 2* ' tpwo Fig. 4 - - 300 - - 300 - - 300 nspheral Data Valid* Except P21326 $ HITACHI

-----------------------HD6303R,HD63A03R,HD63B03RTIMER. SCI TIMINGItemTest HD6303R HD63A03R HD63B03RSymbol Conditionmin typ max min typ max min typUnitmaxTimer Input Pulse Width tPWT 2.0 - - 2.0 - - 2.0 - -Delay Time, Enable PositiveTransition to Timer Outt TOD Fig. 5 - - 400 - - 400 - - 400SCI Input Clock Cycle t Scye 2.0 - - 2.0 - - 2.0 - -SCI Input Clock Pulse Width tPWSCK 0.4 - 0.6 0.4 - 0.6 0.4 - 0.6teyensteyetScyeMODE PROGRAMMINGItemTest HD6303R HD63A03R HD63B03RSymbol Conditionmin typ max min typ max min typUnitmaxRES "Low" Pulse Width PW RSTL 3 - - 3 - - 3 - -Mode Programming Set-up Time tMPs Fig.6 2 - - 2 - - 2 - -Mode Programming Hold Time tMPH 150 - - 150 - - 150 - -teye!eyensI+----------------------t~c------------------------IAddress Strobe(AS)2.4V2.4VEnable(E)MPUWriteOo-O"A.-A,MPU Read0.-0,. A.-A,Figure 1 Multiplexed Bus Timing~ Not Valid_HITACHI327

HD6303R.HD63A03R.HD63B03R~~~~~~~~~~~~~~~~~~~~~~~teveEnablelEIR/W2.4VO.sVMPUWrite0.-0, ---1------+------(,MPU Read0.-0, -------r---------r----------------------(IA.-A, (Port 11 2.4VO.SVp. o - P.,p •• - p ••InputsrMPUReadr MPUWriteFigure 2 Non-Multiplexed Bus TimingrzzI Not ValidO.BVE~_tpwoAll Data2.4V Data ValidPort Outputs ______________-' I\..;.;O';;.;8V~ __Figure 3 Port Data Set-up and Hold Times(MPU Read)Notel Port 2: Except p ••Figure 4 Port Data Delay Times(MPU Write)TimerCounter ------' '----t------ '-------Mode InpulS ______ (1(Pzo, P21. pzz)P"OutputFigure 5 Timer Output TimingFigure 6 Mode Programming Timing328 $ HITACHI

~~~~~~~~~~~~~~~~~~~~~~HD6303R,HD63A03R,HD63B03RVeeTest PointRL = 2.2kSl(4.0kSl for E)1S2074 ®or Equiv.C=90pF for AS, R/W, Do/Ao - D7/A" and A. - AIS=30pF for P,O - P,. and Ao /PIO - A7/P 17=40pF for ER=12kQInterruptTestFigure 7 Bus Timing Test Loads (TTL Load)InternalAddress Bus --I\..~~~-:J~-:=--I'--=~~:::::-A.~-:-I"~:-::-I\..::-::-:-:-"~~~~J\..=-~~~~:::,!J'::=:"r:f''---''-NMI.IRQ.Internal --"',..-_J ........... ,_-"'-__ -...,..-_. __ -\.~-""'\.J-.....D8ta&s ___ ~ _InternalReadInternalWrite._-_-_.__...... v_-_-_.r_-v__A~__ ~_~_-J~-~_~~_I\.._~~~~~~~~~~~~~~~~-~______....1/Figure 8 Interrupt SequenceRES~~I ____________ ~~ ____ JV CC -O·5V:!dr... _)\\\\\\\\\\.\\\\\l----i~~~~1 ~ ____FFFF FFFE FFFF New PC::,ternal _ )\\\\\\\\\\\\\\\\\\\\\\\~ternM _~\\\\\\\\\\\\\\\\\\\\\I~\~~~I-------------RfN _~\\\\\\\\\\\\\\\\\\\\\\,~:·.:\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'---------_I:}\\\\\\\\\\\\\\\\~~;\-\ -----Figure 9 Reset Timing• FUNCTIONAL PIN DESCRIPTION• Vee. VssThese two pins are used for power supply and GND.Recommended power supply voltage is 5V ± 10%. 3 to 6V canbe used for low speed operation (100 - 500 kHz).mental crystal, AT cut. For instance, in order to obtain the.system clock I MHz, a 4MHz resonant fundamental crystal isused because the devide by 4 circuitry is included. EXT ALaccepts an external clock input of duty 50% (±IO%) to drive.For external driving XTAL pin should be open. An exampleof connection circuit is shown in Fig. 10. The crystal andcapacitors should be mounted as close as possible to the pins.• XTAL. EXTALThese two pins are connected with parallel resonant fundaeHITACHI329

AT Cut Parallel Resonance CrystalCo = 7 pF maxRs = 60 n maxXTAL~--~-----'CJEXTAL 1---............(a) Crystal InterfaceXTAL r-- N.C._______ E_X_T_A_L.......J~(b) External ClockC L1z C L2 -1O-22pF ± 20%(3.2-SMHz)Figure 10 Connection CircuitExternal Clock• Standby (STBY)This pin is used to place the MPU in the standby mode.If this goes to "Low" level, the oscillation stops, the internalclock is tied to VSS or Vee and the MPU is reset. In order toretain information in RAM during standby, write "0" into RAMenable bit (RAME). RAME is bit 6 of the RAM Control Registerat address $0014. This disables the RAM, so the contents ofRAM is guaranteed. For details of the standby mode, see theStandby section.• Reset (RES)This input is used to reset the MPU. lffiS must be held"Low" for at least 20ms when the power starts up. It should benoted that, before clock generator stabilize, the internal stateand I/O ports are uncertain, because MPU can not be resetwithout clock. To reset the MPU during system operation, itmust be held "Low" for at least 3 system clock cycles. Fromthe third cycle, all address buses become "high-impedance"and it continues while RF$ is "Low". If lffiS goes to "High",CPU does the following.(1) I/O Port 2 bits 2,1,0 are latched into bits PC2, PC I, PCO ofprogram control register.(2) The contents of the two Start Addresses, $FFFE, $FFFFare brought to the program counter, from which programstarts (see Table 1).(3) The interrupt mask bit is set. In order to have the CPUrecognize the maskable interrupts IRQ. and IRQ2, clear itbefore those are used.• Enable (E)This output pin supplies system clock. Output is a singlephase,TTL compatible and 1/4 the crystal oscillation frequency.It will drive two LS TTL load and 40pF.• Non Maskable Interrupt (NMI)When the falling edge of the input signal of this pin is recognized,NMI sequence starts. The current instruction is continuedto complete, even if NMI signal is detected. Interruptmask bit in Condition Code Register has no effect on NMIdetection. In response to NMI interrupt, the information of330 ~HITACHIProgram Counter, Index Register, Accumulators, and ConditionCode Register are stored on the stack. On completion of thissequence, vectoring address $FFFC and $FFFD are generatedto load the contents to the program counter. Then the CPUbranch to a non maskable interrupt service routine.• Interrupt Request (lRQI)This level sensitive input requests a maskable interruptsequence. When IRQ! goes to "Low", the CPU waits until itcompletes the current instruction that is being executed. Then,if the interrupt mask bit in Condition Code Register.is not set~PU begins interrupt sequence; otherwise, interrupt requestIS neglected.Once the sequence has started, the information of ProgramCounter, Index Register, Accumulator, Condition Code Registerare stored on the stack. Then the CPU s.ets the interrupt maskbit so that no further maskable interrupts may be responded.Table 1 Interrupt Vectoring memory mapHighestPriorityVectorM5B L5BFFFE FFFFFFEEFFFCFFFAFFFBFFF6FFF4FFEFFFFOFFFeFFF9FFF7FFF5Interrupt"lSTRAPIiiMiSoftwtor. Interrupt (5WIIiRQ, (or 1531ICF (Time, Input CapturelOCF (Ti .... ' Output CompereFFF2 FFF3 TOF (Timer OverflowlLowest FFFO FFF1 SCI (RORF + ORFE + TORE!PriorityAt the end of the cycle, the CPU generates 16 bit vectoringaddresses indicating memory addresses $FFF8 and $FFF9, andloads the contents to the Program Counter, then branch to aninterrupt service routine.The Internal Interrupt will generate signal (IRQ2) which isquite the same as IRQl except that it will use the vector address$FFFO to $FFF7.When IRQ! and IRQ2 are generated at the same time, theformer precede the latter. Interrupt Mask Bit in the conditioncode register, if being set, will keep the both interrupts off.On occurrence of Address error or Op-code error, TRAPinterrupt is invoked. This interrupt has priority next to RES.Regardless of the interrupt Mask Bit condition, the CPU willstart an interrupt sequence. The vector for this interrupt will be$FFEE, $FFEF.• Read/Write (RIW)This TTL compatible output signal indicates peripheral andmemory devices whether CPU is in Read ("High"), or in Write("Low"). The normal stand-by state is Read ("High"). Itsoutput will drive one TTL load and 90pF.• Address Strobe (AS)In the multiplexed mode, address strobe signal appears at thispin. It is used to latch the lower 8 bits addresses multiplexedwith data at Do/Ao - D7/A7. The 8-bit latch is controlled byaddress strobe as shown in Figure 15. Thereby, Do/Ao - D7/A7can become data bus during E pulse. The timing chart of thissignal is shown in Figure l.Address Strobe (AS) is sent out even if the internal addressis accessed.• PORTSThere are two I/O ports on HD6303R MPU (one 8-bit portsand one 5-bit port). Each port has an independent write-onlydata direction register to program individual I/O pins for

input or output.·When the bit of associated Data Direction Register is "I",I/O pin is programmed for output, if "0", then programmed foran input.There are two ports: Port I, Port 2. Addresses of eachport and associated Data Direction Register are shown inTable 2.• Only one exception is bit I of Port 2 which becomes either adata input or a timer output. It cannot be used as an outputport.Table 2 Port and Data Direction Register AddressesPortsI/O Port 1I/O Port 2Port Address$0002$0003Data DirectionRegister Address$0000$000190 pF. After reset, these pins become output for upper orderaddress lines (As - AI5).• MODE SELECTIONThe operation mode after the rest must be determined by theuser wiring the P20, P21, and P22 externally. These three pins arelower order bits; I/O 0, I/O I, I/O 2 of Port 2. They are latchedinto the control bits PCO, PC I, PC2 ofI/O Port 2 register whenRES goes "High". I/O Port 2 Register is shown below.Port 2 DATA REGISTER4 1 0$00031 pc21 PC1 I PCO 11/0411/0 311/0 211/0 1 1110 0 I• I/O Part 1This is an 8-bit port, each bit being defined individually asinput or outputs by associated Data Direction Register. The8-bit output buffers have three-state capability, maintaining inhigh impedance state when they are used for input. In order tobe read accurately, the voltage on the input lines must be morethan 2.0V for logic" 1" and less than 0.8V for logic "0".These are TTL compatible. After the MPU has been reset, allI/O lines are configured as inputs in Multiplexed mode. In NonMultiplexed mode, Port 1 will be output line for lower orderaddress lines (Ao - A7), which can drive one TTL load and30 pF.• I/O Port 2This port has five lines, whose I/O direction depends on itsdata direction register. The 5-bit output buffers have three-statecapability, going high impedance state when used as inputs. Inorder to be read accurately, the voltage on the input lines mustbe more than 2.0V for logic "I" and less than 0.8V for logic"0". After the MPU has been reset, I/O lines are configured asinputs. These pins on Port 2 (P20 - P22 of the chip) are usedto program the mode of operation during reset. The values ofthese three pins during reset are latched into the upper 3 bits(bit 7, 6 and 5) of Port 2 Data Register which is explained inthe MODE SELECTION section.In all modes, Port 2 can be configured as I/O lines. This portalso provides access to the Serial I/O and the Timer. However,note that bit I (P21 ) is the only pin restricted to data input orTimer output.• BUS• Do/A.o - D7/A7This TTL compatible three-state buffer can drive one TTLload and 90 pF.An example of external hardware used for Mode Selectionis shown in Figure 11. The HD14053B is used to separate theperipheral device from the MPU during reset. It is necessary ifthe data may conflict between peripheral device and Modegeneration circuit.No mode can be changed through software because the bits5, 6, and 7 of Port 2 Data Register are read-only. The modeselection of the HD6303R is shown in Table 3.The HD6303R operates in two basic modes: (1) MultiplexedMode, (2) Non Multiplexed Mode.• Multiplexed ModeThe data bus and the lower order address bus are multiplexedin the Do / Ao - D7 / A 7 and can be separated by the AddressStrobe.Port 2 is configured for 5 parallel I/O or Serial I/O, or Timer,or any combination thereof. Port 1 is configured for 8 parallelI/O.• Non Multiplexed ModeIn this mode, the HD6303R can directly address HMCS6800peripherals with no external logic. Do/Ao - D7/A7 become adata bus and Port 1 becomes Ao - A7 address bus.In this mode, the HD6303R is expandable up to 65k w9rdswith no external logic.• Lower Order Address Bus LatchBecause the data bus is multiplexed with the lower orderaddress bus in Do/Ao - D7/A7 in the multiplexed mode, addressbits must be latched. It requires the 74LS373 Transparent octalD-type to latch the LSB. Latch connection of the HD6303Ris shown in Figure 15.Non Multiplexed ModeIn this mode, these pins become only data bus (Do - D7 ).Multiplexed ModeThese pins becomes both the data bus (Do - D7) and lowerbits of the address bus (Ao - A7). An address strobe output is"High" when the address is on the pins .• A 8 "" A. 15Each line is TTL compatible and can drive one TTL load and$ HITACHI331

VeeRV.Z.P,. --'~--+-4-""---4 X,P" V,P" ~~--+-4-""---4 Z,ModeControlSwitchInhx:~-----fP"(PCOIV 1------1 P" (PClIZ I------IP" (PC21H014053BNote 1) Figure of Multiplexed Mode2) RC"'Reset Constant3) R, =10knFigure 11Recommended Circuit for Mode SelectionInhABCXoO----------------4C+~1_~--­X 10---------­Y oO-------------------II+---1-+-­y,o-------------------~~~ZoO----------------~;;?H--,Z,O----------------------~Qr~XZControl InputInhibitC0 00 00 00 00 10 10 10 11 XTruth TableSelectB A0 00 11 01 10 00 11 01 1X XOn SwitchH014053BZ. Y. X.Z. Y. X,Z. Y, X.Z. Y, X,Z, YoX.Z, Yo X,Z, Y, X.Z, Y, X,-Figure 12 HD14053B Multiplexers/De-MultiplexersVeeVeeEnablePort 181/0 linesPort 25110 LinesSCITimerMultiplexedDatalAddressPort 1To 8 Address LinesAo -A7Port 25 Parallel 1/0A. -Au SCI8 Address TimerLinesVssDo - 0,80eta LinesA. -Au8 Add" ..LinesVssFigure 13 HD6303R MPU Multiplexed ModeFigure 14 HD6303R MPU Non Multiplexed Mode332 e HITACHI

GNDASD./A. - Q,/A, [Address/DataIIG OC0, a,74LS373D. a.I A,", •• A. -A,Function TableOutput Enable OutputControltOCI G 0 aL H H HL H L LL L X a.H x X z) 0 ... 0,-0,Figure 15Latch ConnectionTable 3 Mode SelectionTable 4 Internal Register AreaOperating ModeMultiplexed ModeNon Multiplexed ModeL: logiC "0"H: logic "1"• MEMORY MAPThe MPU can provide up to 6Sk byte address space. Figure16 shows a memory map for each operating mode. The first 32locations of eacn map are for the CPU's internal register only,as shown in Table 4.P20LLHP 21 P 22H LL HL LRegisterPort 1 Data Direction Register··Port 2 Data Direction Register··Port 1 Data RegisterPort 2 Data RegisterTimer Control and Status RegisterCounter (High Byte)Counter (Low Byte)Output Compare Register (High Byte)Output Compare Register (Low Byte)Input Capture Register (High Byte)Input Capture Register (Low Byte)Rate and Mode Control RegisterTransmit/Receive Control and Status RegisterReceive Data RegisterTransmit Data RegisterRAM Control RegisterReserved• External address in Non Multiplexed Mode1 = Output, 0 = InputAddress00·0102·030809OAOBOC00OE101112131415·1FNon-Multiplexed$0000SOOIF$0080SOOFFInternal RegistersE x:ternal Memorv SpaceInlernalRAMInte,nal RegistersExternal Memorv SpaceInternal RAMExternal Memorv SpaceExternal Memotv SpaceSFFFF '-__....IJ[NOiE)Excludes the following addresses which may beused externally; $00, $02.SFFFF~ __....I'Figure 16 HD6303R Memory Maps$ HITACHI333

HD6303R,HD63A03R,HD63B03R-----------------------• PROGRAMMABLE TIMERThe HD6303R contains 16-bit programmable timer whichmay be used to make measurement of input waveform. Inaddition to that it can generate an output waveform by itself.For both input and output waveform, the pulse width may varyfrom a few microseconds to several seconds.The timer hardware consists of• an 8-bit control and status register• a 16-bit free running counter• a 16-bit output compare register, and• a 16-bit input capture registerA block diagram of the timer is shown in Figure 17.H06303R Internal Bus8111Pori 2OOR- - - - - -~ Output InputLtv.' EdgeBill BIIOPon 2 Port2Figure 17 Programmable Timer Block Diagram• Free Running Counter ($0009: $OOOA)The key element in the' programmable timer is a J6-bit freerunning counter, that is driven by an E (Enable) clock toincrement its values. The counter value will be read out by theCPU software at any time with no effects on the counter.Reset will clear the counter.When the MSB of this counter is read, the LSB is storedin temporary latch. The data is fetched from this latch by thesubsequent read of LSB. Thus consistent double byte data canbe read from the counter.When the CPU writes arbitrary data to the MSB ($09), thevalue of $FFF8 is being pre-set to the counter ($09, $OA)regardless of the write data value. Then the CPU writes arbitrarydata to the LSB ($OA), the data is set to the "Low" byteof the counter, at the same time, the data preceedingly writtenin the MSB ($09) is set to "High" byte of the counter.When the data is written to this counter, a double bytestore instruction (ex. STD) must be used. If only the MSB ofcounter is written, the counter is set to $FFF8.The counter value written to the counter using the doublebyte store instruction is shown in Figure 18.To write to the counter can disturb serial operations, so itshould be inhibited during using the SCI. If external clockmode is used for SCI, this will not disturb serial operations.(SAFJ written to the counterlFigure 18 Counter Write Timing• Output Compare Register ($OOOB:$OOOC)This is a 16-bit read/write register which is used to control anoutput waveform. The contents of this register are constantlybeing compared with current value of the free running counter.When the contents match with the value of the free runningcounter, a flag (OCF) in the timer control/status register(TCSR) is set and the current value of an output level Bit(OLVL) in the TCSR is transferred to Port 2 bit 1. When bit Iof the Port 2 data direction register is "I" (output), the OLVLvalue will appear on the bit I of Port 2. Then, the value of OutputCompare Register and Output level bit may be changedfor the next compare.The output compare register is set to $FFFF during reset.The compare function is inhibited at the cycle of writing tothe high byte of the output compare register and at the cyclejust after that to ensure valid compare. It is also inhibited insame manner at writing to the free running counter.In order to write a data to Output Compare Register, adouble byte store instruction (ex.STD) must be used.• Input Capture Register ($0000: $OOOE)The input capture register is a 16-bit read-only register usedto hold the current value of free running counter captured whenthe proper transition of an external input signal occurs.The input transition change required to trigger the countertransfer is controlled by the input edge bit (IEDG).To allow the external input signal to go in the edge detectunit, the bit of the Data Direction Register corresponding to bito of Port 2 must have been cleared (to zero).To insure input capture in all cases, the width of an inputpulse requires at least 2 Enable cycles.• Timer Control/Status Register (TCSR) ($0008)This is an 8-bit register. All 8-bits are readable and the lower5 bits may be written. The upper 3 bits are read-only, indicatingthe timer status information as is shown below.(1) A proper transition has been detected on the input pin(ICF).(2) A match has been found between the value in the freerunning counter and the output compare register (OCF).(3) When counting up to $0000 (TO F).Each flag has an individual enable bit in TCSR whichdetermines whether or not an interrupt request may occur(IRQ2). If the I-bit in Condition Code Register has beencleared, a priority vectored address occurs correspondingto each flag. A description of each bit is as follows.Timer Control I Status Register7654 J 210I'CF I OCF I TOF I EICI I EOCI I ETOII'EOG I OLVL I s0008Bit 0334 ~HITACHIOLVL (Output Level); When a match is found in thevalue between the counter and the output com-

Bit 1pare register, this bit is transferred to the Port 2bit 1. If the DDR corresponding to Port 2 bit 1 isset "1", the value will appear on the output pin ofPort 2 bit 1.IEDG (Input Edge): This bit control which transitionof an input of Port 2 bit 0 will trigger the datatransfer from the counter to the input captureregister. The DDR corresponding to Port 2 bit 0must be clear in advance of using this function.When IEDG = 0, trigger takes place on a negativeedge ("High':"to-"Low" transition). When IEDG =1, trigger takes place on a positive edge ("Low"-to­"High" tranSition).Bit 2 ETOI (Enable Timer Overflow Interrupt); When set,this bit enables TOF interrupt to generate theinterrupt request (lRQz). When cleared, the interruptis inhibited.Bit 3 EOCI (Enable Output Compare Interrupt); When set,this bit enables OCF interrupt to generate theinterrupt request (1RQ2). When cleared, the interruptis inhibited.Bit 4 EICI (Enable Input Capture Interrupt); When set, thisbit enables ICF interrupt to generate the interruptrequest (IRQi). When cleared, the interrupt isinhibited.Bit 5 TOF (Timer Over Flow Flag); This read-only bit is setat the transition of $FFFF to $0000 of thecounter. It is cleared by CPU read of TCSR (withTOF set) followed by a CPU read of the counter($0009).Bit 6 OCF (Output Compare Flag); This read-only bit is setwhen a match is found in the value between theoutput compare register and the counter. It iscleared by a read of TCSR (with OCF set) followedby a CPU write to the output compare register($OOOB or $OOOC).Bit 7 ICF (Input Capture Flag); The read-only bit is set by aproper transition on the input, and is cleared bya read of TCSR (with ICF set) followed by aCPU read of Input Capture Register ($OOOD).Reset will clear each bit of Timer Control and StatusRegister.• SERIAL COMMUNICATION INTERFACEThe HD6303R contains a full-duplex asynchronous SerialCommunication Interface (SCI), SCI may select the severalkinds of the data rate. It consists of a transmitter and a receiverwhich operate independently but with the same data formatand the same data rate. Both of transmitter and receiver communicatewith the CPU via the data bus and with the outsideworld through Port 2 bit 2, 3 and 4. Description of hardware,software and register is as follows.• Wake-Up FeatureIn typical multiprocessor applications the software protocolwill usually have the designated address at the initial byte of themessage. The purpose of Wake-Up feature is to have the nonselectedMPU neglect the remainder of the message. Thusthe non-selected MPU can inhibit the all further interruptprocess until the next message begins.Wake-Up feature is re-enabled by a ten consecutive "l"swhich indicates an idle transmit line. Therefore software protocolmust put an idle period between the messages and mustprevent it within the message.With this hardware feature, the non-selected MPU is reenabled(or "waked-up") by the next message.• Programmable Options'The HD6303R has the following programmable features.• data format; standard mark/space (NRZ)• clock source; external or internal• baud rate; one of 4 rates per given E clock frequency or1/8 of external clock• wake-up feature; enabled or disabled• interrupt requests; enabled or masked individually fortransmitter and receiver.c1ock output; internal clock enabled or disabled to Port2 bit 2·Port 2 (bits 3, 4); dedicated or not dedicated to serialI/O individually• Serial Communication HardwareThe serial communications hardware is controlled by 4regis.ters as shown in Figure 19. The registers include:• an 8-bit control/status register• a 4-bit rate/mode control register (write-only)• an 8-bit read-only receive data register• an 8-bit write-only transmit data registerBesides these 4 registers, Serial I/O utilizes Port 2 bit 3(input) and bit 4 (output). Port 2 bit 2 can be used when anoption is selected for the internal-clock-out or the externalclock-in.• Transmit/Receive Control Status Register (TRCSR)TRCS Register consists of 8 bits which all may be read whileonly bits 0 to 4 may be written. The register is initialized to $20on RES. The bits of the TRCS Register are explained below.Transmit I Receive Control Status Register76543210I AOAF I ORFE I TORE I RIE I RE I TIE I TE I wu IADDR10011Bit 0 WU (Wake Up); Set by software and cleared by hardwareon receipt of ten consecutive "I "s. While this bitis "I", RDRF and ORFE flags are not set evenif data are received or errors are detected. Thereforereceived data are ignored. It should be notedthat RE flag must have already been set in advanceofWU flag's set.Bit 1 TE (Transmit Enable); This bit enables transmitter. Whenthis bit is set, bit 4 of Port 2 DDR is also forcedto be set. It remains set even if TE is cleared.Preamble of ten consecutive "I "s is transmittedjust after this bit is set, and then transmitterbecomes ready to send data. If this bit is cleared,the transmitter is disabled and serial I/O affectsnothing on Port 2 bit 4.Bit 2 TIE (Transmit Interrupt Enable); When this bit is set,TDRE (bit 5) causes an IIDh interrupt. Whencleared, TDRE interrupt is masked.Bit 3 RE (Receive Enable); When set, Port 2 bit 3 can be usedas an input of receive regardless of DDR value forBit 4this bit. When cleared, the receiver is disabled.RIE (Receive Interrupt Enable); When this bit is set,RDRF (bit 7) or ORFE (bit 6) cause an TlUJ2interrupt. When cleared, this interrupt is masked._HITACHI 335

Bit 5 TORE (Transmit Data Register Empty); When the datais transferred from the Transmit Data Registerto Output Shift Register, this bit is set by hardware.The bit is cleared by reading the status registerfollowed by writing the next new data intothe Transmit Data Register. TDRE is initializedto 1 by RES.Bit 6 ORFE (Over Run Framing Error); When overrun orframing error occurs (receive only), this bit is setby hardware. Over Run Error occurs if the attemptis made to transfer the new byte to the receivedata register while the RDRF is "1". FramingError occurs when the bit counter is not synchronizedwith the boundary of the byte in the receIVmgbit stream. When Framing Error is detected,RDRF is not set. Therefore Framing Errorcan be distinguished from Overrun Error. That is,if ORFE is "1" and RDRF is "1", Overrun Erroris detected. Otherwise Framing Error occurs.The bit is cleared by reading the status registerfollowed by reading the receive data register, orby REs.Bit 7 RDRF (Receive Data Register Full); This bit is set byhardware when the data is transferred from thereceive shift register to the receive data register.It is cleared by reading the status register followedby reading the receive data register, or by RES.Bit 7 Rat. and Mode ConHol Register Bit 0I I cc, I cco I ss, I sso IS, 0Transmit/Receive Control and Status RegisterPOll '1Receive Shift RegisterCloCk 10Bit ... --'-------.... .... ---E2~------------6Figure 19 Serial 1/0 Registerox x CCl CCO 551 550 ADDR $0010Transfer Rate I Mode Control RegisterTable 5 SCI Bit Times and Transfer RatesSS1 : SSO0 00 11 01 1XTAL 2.4576 MHz 4.0 MHz 4.9152MHzE 614.4 kHz 1.0MHz 1.2288MHzE.;. 16 26 ~s/38.400 Baud 16 ~s/62.500 Baud 13 /ls/76.8oo8audE.;. 1282081Js/4.800 Baud 128 ~s/7812.5 Baud 104.2/ls/ 9.6ooBaudE.;. 1024 1.67ms/600 Baud 1.024ms/976.6 Baud 833.3/ls/ 1.2oo8audIE.;. 4096 6.67ms/150 Baud 4.096ms/244.1 Baud 3.333ms/ 300Baud336~HITACHI

-----------------------HD6303R,HD63A03R,HD63B03RTable 6 SCI Format and Clock Source ControlCC1:CCO Format Clock Source0 0 - I -0 1 NRZ Internal1 0 NRZ Internal1 1 NRZ External• Clock output is available regardless of values for bits RE and TE .•• Bit 3 is used for serial input if RE = "1" in TRCS.Bit 4 is used for serial output if TE= "'" in TRCS.HO This pin can be used as I/O port.Port 2 Bit 2 Port 2 Bit 3 Port 2Bit 4- - -Not Used *** ." ..Output" .. ..Input .. . • Transfer Rate/Mode Control Register (RMCR)The register controls the following serial I/O functions:• Bauds rate ·data format • clock source• Port 2 bit 2 featureIt is 4-bit write-only register, cleared by RES. The 4 bits areconsidered as a pair of 2-bit fields. The lower 2 bits control thebit rate of internal clock while the upper 2 bits control theformat and the clock select logic.Bit 0 SSO} Speed SelectBit 1 SSIThese bits select the Baud rate for the internal clock. Therates selectable are function of E clock frequency of the CPU.Table 5 lists the available Baud Rates.Bit2 CCO }Bit 3 CCl Clock Control/Format SelectThey control the data format and the clock select logic.Table 6 defines the bit field.• Internally Generated ClockIf the user wish to use externally an internal clock of theserial I/O, the following requirements should be noted.'CCl, CCO must be set to "10".'The maximum clock rate must be E/I6.• The clock rate is equal to the bit rate.• The values of RE and TE have no effect.• Externally Generated ClockIf the user wish to supply an external clock to the SerialI/O, the following requirements should be noted.• The CC 1 , CCO must be set to "11" (See Table 6).• The external clock must be set to 8 times of the desiredbaud rate.• The maximum external clock frequency is E/2 clock.• Serial OperationsThe serial I/O hardware must be initialized by the softwarebefore operation. The sequence will be normally as follows.'Writing the desired operation control bits of the Rate andMode Control Regi8ter.• Writing the desired operation control bits of the TRCSregister.If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may bekept set. When TE, RE bit are cleared during SCI operation,and subsequently set again, it should be noted that TE, REmust be kept "0" for at least one bit time of the current baudrate. If TE, RE are set again within one bit time, there may bethe case where the initialiZing of internal function for transmitterand receiver does not take place correctly.• Transmit OperationData transmission is enabled by the TE bit in the TRCSregister. When set, the output of the transmit shift registeris connected with Port 2 bit 4 which is unconditionally configuredas an output.After RES, the user should initialize both the RMC registerand the TRCS register for desired operation. Setting the TE bitcauses a transmission of ten-bit preamble of" 1 "s. Following thepreamble, internal synchronization is established and the transmitteris ready to operate. Then either of the following statesexists.(1) If the transmit data register is empty (TDRE = 1), theconsecutive "I"s are transmitted indicating an idlestates.(2) If the data has been loaded into the Transmit DataRegister (TDRE = 0), it is transferred to the outputshift register and data transmission begins.During the data transfer, the start bit ("0") is !lrst trans·ferred. Next the 8·bit data (beginning at bit 0) and finally thestop bit ("1 "). When the contents of the Transmit D.Ha Registeris transferred to the output shift register, the hardware sets theTDRE flag bit: If the CPU fails to respond to the flag withinthe proper time, TDRE is kept set and then a continuous stringof 1 's is sent until the data is supplied to the data register.• Receive OperationThe receive operation is enabled by the RE bit. The serialinput is connected with Port 2 bit 3. The receiver operationis determined by the contents of the TRCS and RMC register.The received bit stream is synchronized by the first "0" (startbit). During IO-bit time, the data is strobed approximately atthe center of each bit. If the tenth bit is not "1" (stop bit),the system assumes a framing error and the ORFE is set.If the tenth bit is "1 ", the data is transferred to the rec'eivedata register, and the RDRF flag is set. If the tenth bit of thenext data is received and still RDRF is preserved set, thenORFE is set indicating that an overrun error has occurred.After the CPU read of the status register as a response toRDRF flag or ORFE flag, followed by the CPU read of thereceive data register, RDRF or ORFE will be cleared.• RAM CONTROL REGISTERThe register aSSigned to the address $0014 gives a statusinformation about standby RAM.Bit 0 Not used.Bit 1 Not used.RAM Control Register8 5 4 320Bit 2 Not used.~HITACHI 337

Bit 3 Not used.Bit 4 Not used.Bit 5 Not used.Bit 6 RAM Enable.Using this control bit, the user can disable the RAM. RAMEnable bit is' set on the positive edge of RES and RAM isenabled. The program can write "I" or "0". If RAME iscleared, the RAM address becomes external address and theCPU may read the data from the outside memory.Bit 7 Standby BitThis bit can be read or written by the user program. It iscleared when the Vee voltage is removed. Normally this bitis set by the program before going into stand·by mode. Whenthe CPU recovers from stand·by mode, this bit should bechecked. If it is "I ", the data of the RAM is retained duringstand·by and it is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD6303R has an upward object code compatible withthe HD6801 to utilize all instruction sets of the HMCS6800.The execution time of the key instruction is reduced to increasethe system through·put. In addition, the bit operation instruc·tion, the exchange instruction between the index and theaccumulator, the sleep instruction are added. This sectiondescribes:• CPU programming model (See Fig. 20)• Addressing modes• Accumulator and memory manipulation instructions (SeeTable 7)• New instructions• Index register and stack manipulation instructions (SeeTable 8)• Jump and branch instructions (See Table 9)• Condition code register manipulation instructions (SeeTable 10)·Op-code map (See Table 11)• Cycle-by-cycle operation (See Table 12)• CPU Programming ModelThe programming model for the HD6303R is shown in Figure20. The double accumulator is phYSically the same as theaccumulator A concatenated with the accumulator B, so thatthe contents of A and B is changed with executing operation ofan accumulator D.E ----A____ 0:U: ___ .! ___ 38·Bit Accumulators A and B,!t 0 ~ Or 16·81t Double Accumulator 0every instruction is shown along with execution time given interms of machine cycles (Table 7 to 11). When the clockfrequency is 4 MHz, the machine cycle will be microseconds.Accumulator (ACCX) AddressingOnly the accumulator (A or B) is addressed. Either accumulatorA or B is specified by one-byte instructions.Immediate AddressingIn this mode, the operand is stored in the second byte of theinstruction except that the operand in LDS and LDX, etc arestored in the second and the third byte. These are two orthree-byte instructions.Direct AddressingIn this mode, the second byte of instruction indicates theaddress where the operand is stored. Direct addressing allowsthe user to directly address the lowest 256 bytes in the machine;locations zero through 255. Improyed execution times areachieved by storing data in these locations. For systemconfiguration, it is recommended that these locations should beRAM and be utilized preferably for user's data realm. These aretwo-byte instructions except the AIM, OIM, ElM and TIMwhich have three-byte.Extended AddressingIn this mode, the second byte indicates the upper 8 bitaddresses where the operand is stored, while the third byteindicates the lower 8 bits. This is an absolute address inmemory. These are three-byte instructions.I ndexed AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the Index Register. For each of AIM, OIM, ElMand TIM instructions, the contents of the third byte are addedto the lower 8 bits in the Index Register. In addition, the result·ing "carry" is added to the upper 8 bits in the Index Register.The result is used for addressing memory. Because the modifiedaddress is held in the Temporary Address Register, there is nochange to the Index Register. These are two-byte instructionsbut AIM, OIM, ElM, TIM have three-byte.Implied AddressingIn this mode, the instruction itself gives the address; stackpointer, index register, etc. These are. I-byte instructions .Relative AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the program counter. The resulting carry orborrow is added to the upper 8 bits. This helps the user toaddress the data within a range of -126 to + 129 bytes of thecurrent execution instruction. These are two-byte instructions.1.51.51,501 Index Register (XISl'01 Stack Pointer (SP)PCo 1 Program Coun ter (PC), 0~' HI'" Z V C condit. ion Code Re9.iSter (CCR)Carry/Borrow from MSBOverflowZeroNegativeInterruptHalf Carry (From Bit 3)Figure 20 CPU Programming Model• CPU Addressing ModesThe HD6303R has seven address modes which depend onboth ofthe·instruction type and the code. The address mode for338 ~HITACHI

Table 7 Accumulator, Memory Manipulation InstructionsCondition Code()peretions MnemonicAddressing ModesRegisterBoolean/IMMED DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - • OP - • OP - • OP - .OP - •H I N Z V CAdd Doab .. ADDD C3 3 3 03 4 2 E3 5 2 F3 5 3 A:B+M:M+l-A:B·. , , I IAdd Accumuletors ABA lB 1 1 A+B-A I I I IAdd With Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A ,I·Add ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-A,· , , I IADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B,· , , I It t IADCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-B t ,· t t IAND ANDA B4 2 2 94 3 2 A4 4 2 B4 4 3 A'M-A t I R AN DB C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M-B t t R Bit Test BITA 85 2 2 95 3 2 AS 4 2 B5 4 3 A·M I I R BIT B C5 2 2 05 3 2 E5 4 2 F5 4 3 B'M·. , , R ·C .... CLR 6F 5 2 7F 5 3 OO-M·CLRA 4F 1 1 OO-A·CLRB SF 1 1 OO-B ~ CMPA 81 2 2 91 3 2 Al 4 2 81 4 3 A-M CMPB Cl 2 2 01 3 ,2 El 4 2 Fl 4 3 8-M·CompereAccumuletorlceA 11 1 1 A-8·Complement. I'. COM 63 6 2 73 6 3 M-M·· COMA 43 1 1 A-ACOMB 53 1 1 8 -8Complement, 2', NEG 60 6 2 70 6 3 OO-M-M·(Negate' NEGA 40 1 1 OO-A-ANEG8 50 1 1 OO-B-BDecimal Adjust, A DAA 19Converts binary add of BCD2 1 characters into 8CD formatDec_nt DEC SA 6 2 7A 6 3 M-l-M·DECA 4A 1 1 A -1-A·R S R RR S R RR S R R, I I II , , t· , I t t. t t R St I R St t R S, , (j)~I (ii·(~, t (l)tlJ, t I ~t t 00 •. , t @ •DECB SA 1 1 B-l-B • • I t @ •ExcluliwOR EORA 8B 2 2 98 3 2 AI 4 2 B8 4 3 A@M ... A·EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 B@M ... B·Increment INC 6C 6 2 7C 6 3 M+l-M·INCA 4C 1 1 A+ l"'A·I I R I I R I I·(J) •I I (J).I I R •I I R I I R ·· • I{j),. t RI' I R ·•INCB 5C 1 1 8 + 1'" B • • I I (J) •Loed LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M ... AAccumuletorLDAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M-B·Load Doub ..AccumulatorLDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M+ I"'B,M ... A·Multiply UnlilMd MUL 3D 7 1 AxB ... A:B··OR,lnclusiw ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+M"'AORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B +M- B. · • · •Push 0 ... PSHA 36 4 1 A ... Mil», SP - 1 ... SP PSHB 37 4 1 B ... Mil», SP - 1 ... SP • • PuIiDIta PULA 32 3 1 SP+l-SP,MIP-A·. • PULl 33 3 1 SP+l"'SP,MIP-B • • ·• • •Rotat. L.tt ROL 69 6 2 79 6 3 M ' - ·I I @ tI I.@IIROLA 49 1 1 Al C9f! Ii I " no! • • I I @ IROLB 59 1 1 • " 'IiO·=1 Gf}fl II I " I~I I @I'RORA ~ 1 1 I I (j) I• 1»7 IiORORB 5& 1 1• • , I (I) IRotet. Rieht ROR 66 6 2 76 6 3Note) Condition Code Register will be explained in Note of Table 10,Ito be continued)eHITACHI 339

HD6303R,HD63A03R,HD63B03R-----------------------Table 7 Accumulator, Memory Manipulation InstructionsAddre.inG ModesOperltions Mnemonic IMMED DIRECT INDEX EXTEND IMPLIEDOP -BooI .. n'Arithmetic OperltionCondition CodeRegi,ter5 4 3 2, 0" OP - " OP - " OP - "OP - "H I N Z V CShift Left ASl 68 6 2 78 6 3M} _ I It> IArithmeticASlA 48 1 A '?1lllllllt-o I II!) IASlB 58 1 ..,7 110• • I I~Doub/eShiftASlD 06 , ,left. Arithmetic 9"'IA7 mJ ~ • rJ-O • • I I~ •Shift Right ASR 67 6 2 77 6 3Arithmetic:J cg 1!Iii tn • • I I II IASRA 47 , ,·· IlSf'B 54, , ..,7 110R·· ASRB 57 1,· , I IShift RiGht lSR 64 6 2 74 6 3 M} _ R I lOOicellSRA 44 , , A~IIIIIIIK;I • • •, R•Double ShiftRight looicel °i7 ACCAOAJI~~' eo~ • •, R (i).lSRD 04 1,·Store STAA 97 3 2 A7 4 2 B7 4 3 A .... MAccumulltorI,·R·STAB 07 3 2 E7 4 2 F7 4 3 B .... M • • I R STD DO 4 2 ED 5 2 FDA-M5 3• • , , R·Store DoubleAccumulltor8- M+'SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 8 -M .... I• ·IDouble Subtract SUBD 83 3 3 93 4 2 A3 5 2 B3 5 3 A:I-M:M+' .... A:8·Subtract SUBA 80 2 2 90 3 2 AO 4 2 80 4 3 A-M .... A • • I I , ISubtract SBA 10 , 1 A-I .... A·Accumulltors• I •I · • • • IISubtract SICA 82 2 2 92 3 2 A2 4 2 82 4 3 A-M-C-A • • , , , IWith ClrrvS8CB C2 2 2 02 3 2 E2 4 2 F2 4 3 8-M-C .... I·I I I· •I· • R RTren,fer TA8 16 1 1 A .... 8 I I R AccumulltorsT8A 17 1 1 8 .... A• • • I R •·Test Zero or TST 60 4 2 70 4 3 M-OOMinusTSTA 40 , 1 A -00 • • I I R RTSTI 50 1 1 8 - 00 • · • I R RAnd Immedilte AIM 71 8 3 81 7 3 M·IMM .... M : : R OR Imrnedilte OlM 72 8 3 82 7 3 M+IMM .... M : % R •EDR lnimec!ilte ElM 75 6 3 85 7 3 MIMM .... M : t R •THt Immedilte TIM 78 4 3 88 5 3 M·IMM• • : 1 R •Note) Condition Code' Register will be explained in Nota of Tabla 10.• New InstructionsIn addition to the H06801 Instruction Set, the HD6303Rhas the following new instructions:AIM----(M)· (IMM)-+(M)Evaluates the AND of the immediate data and thememory, places the result in the memory.OIM---- (M) + (IMM) -+ (M)Evaluates the OR of the immediate data and thememory, places the result in the memory.EIM----(M)(!) (IMM)-+ (M)Evaluates the EOR of the immediate data and thecontents of memory, places the result in memory.TIM----(M) • (IMM)Evaluates the AND of the immediate data and thememory, changes the flag of associated condition coderegisterEach instruction has three bytes; the fust is op-code, thesecond is immediate data, the third is address modifier.XGDX--(ACCD) .. (IX)Exchanges the contents of accumulator and the indexregister.'SLP----The MPU is brought to the sleep mode. For sleepmode, see the "sleep mode" section.340 eHITACHI

Table 8 Index Register, Stack Manipulation InstructionsPointer Operation,MnemonicAddressing ModesCondition CodeBooleanlRegisterIMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - - - - - # OP # OP # OP # OP # H I N Z V CCompere Inde. Reg CPX 8C 3 3 9C 4 2 AC 5 2 BC 5 3 'X-M:M+1 • • t, t,Decrement Inde. Reg DEX 09 1 1 X-1 .... X• , •Decrement Steck Pntr DES 34 1 1 SP-1 .... sP--• · •Increment Inde. Reg INX 08 1 1 X + , .... X tIncrement Stack Pntr INS 31 1 1 sP+1 .... SP · · · • • •Load Inete. Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M .... XH.IM+ 1) .... XL (i)· ·t R•·(])Load Stack Pntr L-os--f&E 3 3 9E 4 2 AE 5 2 BE 5 3 M .... sPH.IM+1) .... sPL R(])Store Inde. Reg STX OF 4 2 EF 5 2 FF 5 3 X H .... M. XL .... 1M + 11• ·(]) R ·Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SP H .... M. SP L .... IM+ 11,·R•Inde. Reg .... Stack Pn_~ TXS 35 1 1 X-1 .... sP· • • · • Push Data PSHX 3C 5 1 XL .... M •• sP - 1 .... SP·· · • •XH .... M •• sP - 1 .... SPPull Data PULX 3B 4 1 sP + , .... SP. M ..... XH• • • ·· •sP+ 1 .... SP.M ..... XLExchange XGDX 18 2 1 ACCD~IX• • • • • •Notel Condition Code Register will be explained in Note of Table 10.Steck Pntr .... Inde. Reg -T's-X--- 30 1 1 sP+ , .... XAdd ABX 3A 1 1 B+X .... X -------·Operation,MnemonicTable 9 Jump, Branch InstructionAddressing ModesBranch TestCondition CodeRegi'terRELATIVE DIRECT INDEX EXTEND IMPLIED5 4 3 2 1 0OP - # OP - - # OP - # OP - # OP # H I N Z V CBranch Always BRA 20 3 2 None • • Branch Never BRN 21 3 2 None Branch If Carry CI .. r BCC 24 3 2 c-o • • · • Branch If Carry Set BCS 25 3 2 C - 1 Branch If - Zero BEQ 27 3 2 Z -1 • • • Branch If > Zero BGE 2C 3 2 N(f) V-OBranch If > Zero 8GT 2E 3 2 Z + IN (f) VI- 0 • •Branch If Higher BHI 22 3 2 C+Z-O-- • Branch If " Zero BLE 2F 3 2 f-- . Z +-IN (f) VI- 1 • Branch If L_ OrBLS 23 3 2 C+Z-1SemeBranch If < Zero BLT 20 3 2 N (f) V-1 • Branch If Minus BMI 2B 3 2 N -1·· • •Branch If Not EqualBNEZaro26 3 2 Z·O • • · · ·Branch If Oll8rflowBVC 28 3 2 V-O · • • · •ClearBranch If Oll8rflow Set BVS 29 3 2 V-1·· • • • •Branch To Subroutine 8SR 80 5 2 • Jump JMP 6E 3 2 7E 3 3· • · Jump To Subroutln. JSR 90 5 2 AD 5 2 BD 6 3 • • · • • •Advances Prog. Cntr.No ()peretlon NOP 01 1 1Only • • • • • •Branch If Plus BPL 2A 3 2 N-O • ·• • • ·Retum From Interrupt RT! 38 10 1 -(1)-R.tum FromRTS 39 5 1Subroutine• • • • •Softwere Interrupt SWI 3F 12 1 • S • · Weit for InterruPt- WAI 3E 9 1 (j) SMO SLP 1A 4 1• • • • • •Notel ·WAI putl R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.Condition Code Register will be explained in Note of Table 10.eHITACHI 341

HD6303R,HD63A03R,HD63B03R-----------------------Table 10 Condition Code Register Manipulation InstructionsAdd,euintMoclesCondition Code Regiller• · · ·R()pt'ltion, Mnemonic IMPLIED 800lean Ope,at,on 5 4 3 2 I 0OP H I N Z V C- •C ..... Car,y ClC OC 1 1 O .... C Cle .. Intl"upt Mesk Cli OE 1 , 0-1 R---CIM,Ow,fl_ ClV OA 1 1 0"" V R Set c.r,y SEC oq 1 1 1 -C · S$It Inte,rupt Me,k SEI OF t 1 1 .... 1 5 · · · ·Sat Ow,flow SEV 08 t 1 I .... V·•5 · · · · ·Accumullto, A .... CCR TAP 06 1 1 A .... CCR ---- It ---CCR .... Accumuleto' A TPA 07 1 1 CeR-A·[NOTE 11[NOTE 21Condition Code Register Notes: (Bit set if test is true and cleared otherwise)(1) (Bit V) Test: Result = 10000000?~ (Bit C) Test: Result, OOOOOOOO?~) (Bit C) Test: BCD Character of high-order byte greater than 9? (Not cleared if previously setl@ (Bit V) Test: Operand = 10000000 prior to execution?@ (Bit V) Test: Operand = 01111111 prior to execution?@ (Bit V) Test: Set equal to NeC=1 after the execution of instructions(j) (Bit N) Test: Result less than zero? (Bit 15=1)@ (All Bit) load Condition Code Register from Stack.c§) (Bit I) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the waitstate.(All Bitl Set according to the contents of Accumulator A.(Bit C) Result of Multiplication Bit 7= 1 of ACCB?Cli instruction and interrupt.If interrupt mask-bit is set 0="1") and interrupt is requested (TAO;' = "a" or iFiQ; = "0"),and then CLI instruction is executed, the CPU responds as follows.CD The next instruction of CLI is one-machine cycle instruction.Subsequent two instructions are executed before the interrupt is responded.That is, the next and the next of the next instruction are executed.~ The _next instruction of Cli is two-machine cycle (or more) instruction.Only the next instruction is executed and then the CPU jump to the interrupt rou~ine.Even if TAP instruction is used, instead of CLI, the same thing occurs.Table 11OP-Code MapDIR IMM I DIR I INO J EXT IMM T OIR I INO I EXT0000 0001 0010 0011 0100 0101 0110 0111 1000 I 1001 I 1010 I 1011 1100 I 1101 I 1110] 1111OPACC ACC A.CCA or SP ACC8 or XINOCODE A 8 1%~LO 0 I 2 3 4 5 6 7 8 I 9 I A I B C I o I E I F0000----O~ SIA 8RA TSX NEG SU80001 I NOP CIA BRN INSAIMCMP0010 2 ~ /"'" BHI PULA ~ OIM SBC0011 S ~ /"'" BLS PULB COM SUBD ADDD---0100 4 LSRD .,/ BeC DES LSR ANO0101 5 ASLD ......- BCS TXS ElM BIT0110 6 TAP TAB BNE PSHA ROR LOA1000 8 INX XGDX BVC PULX ASL EOR1001 9 -DEX OM BVS RTS ROL AOC1010 A CLV SLP BPL ABX DEC ORATIM ADD1100 C CLC ~ BGE PSHX INC CPX LOD01" 7 TPA TIA BEQ PSHB ASR~ISTA ............... l STA1011 B SEV AlA BMI RTI----1101 D SEC ......- ILT MUL TST BSR I JSR ~ STD"1O E CLI /"'" BGT WAI .............................. JMP LOS LOX1111 F SEI ~ BLE SWI CLR ..............- STS ~ STX0 I 2 S 4 5 8 7 8 I 9 I A I B C I D ] E ] FUNDEFINED OP CODE ~• Only for instructions of AIM, OIM, ElM, TIM0I23456789ABCDEF342$ HITACHI

Immediate~~~~~~~~~~~~~~~~~~~~~~~HD6303R,HD63A03R,HD63B03R• Instruction Execution CyclesIn the HMCS6800 series, the execution cycle of each instructionis the number of cycles between the start of the currentinstruction fetch and just before the start of the subsequentinstruction fetch.The HD6303R uses a mechanism of the pipeline controlfor the instruction fetch and the subsequent instruction fetchis performed during the current instruction being executed.Therefore, the method to count instruction cycles used inthe HMCS6800 series cannot be applied to the instructioncycles such as MULT, PULL, DAA and XGDX in the HD6303R.Table 12 provides the information about the rela!!onshipamong each data on the Address Bus, Data Bus, and R/W statusin cycle-by-cycle basis during the execution of each instruction.Address Mode &InstructionsTable 12 Cycle-by-Cycle OperationAddress BusData BusIMMEDIATEADC ADDAND BITCMP EORLOA ORASBC SUBADDD --CP)C --LDD LOS 3LOX SUBD2--~---1 Op Code Address+ 1 1 Operand Data2 Op Code Address+2, Next Op Code---r-~--~---~------Op Code Address+'---,- 1---Operand Data (MSB)2 Op Code Address+2, Operand Data (LSB)3 Op Code Address+3, Next Op CodeDIRECTADC ADD ! I' Op Code Address+' , I Address of Operand (LSB)AND BIT Ii I 2 Address of Operand , Operand DataCMP EOR 3 3 Op Code Address+2 1 Next Op Code~ ~~f- -~ ~~~ ..~ ---- ,. ~ -op Code Add,ess+'-- --L,_I Destination Add,es,3 2 Destination Address 0 1 Accumulator Data3 Op Code Address+2 ~ Next Op Code-AODO-----tpX-- ------ , Op Code Address+ ,-----c---; I Adcfress of Operand (LSBj-LDD LOS 4 2 Address of Operand , Operand Data (MSB)LOX SUBD 3 Address of Operand +' , Operand Data (LSB)4 Op Code Address+2 , Next Op Code--Sfo---sTS --- -- --- ----r---,-- Op Code Address+' C Destination Address (LSB)iSTX 4 2 Destination Address 0 Register Data (MSB)3 Destination Address + , 0 Register Data (LSB)4 Op Code Address + 2 , Next Op Code- JS-R- - -------- ---- -,-~ode Address+, '. Jump Ad-;-d:-r-es-s--c('"O"L--;;;SC;;;:B:-) ---[2 FFFF , Restart Address (LSB)5 I 3 Stack Pointer ,0 Return Address (LSB)4 Stack Pointer-, 11 0 Return Address (MSB)5 Jump Address , I First Subroutine Op Code---tlrvC------------ ----1---,--- Op Code Address+ 1 --, Data42 Op Code Address+2 , I Address of Operand (LSB)3 Address of Operand i 1 I Operand Data4 Op Code Address + 3 , I Next Op Code-ATfl.1--ETrVf---I---I----11-- Op Code Address+ 1 ----,-- -Immediate Data ~-~----OIM 2 Op Code Address+2 , Address of Operand (LSB)63 Address of Operand , Operand Data4 -FFFF , Restart Address (LSB)5 Address of Operand 0 New Operand Data6 Op Code Address+3 , Next Op Code- Continued -eHITACHI 343

Address Mode &InstructionsTable 12 Cycle-by-Cycle Operation (Continued)Address BusData BusINDEXEDJMPADCANDCMPLDASBCTSTSTAADDBITEORORASUB341231234Op Code Address + 1 1 OffsetFFFF 1 Restart Address (LSB)Jump Address _____ 1::-_--+--::;F:-:;irs::;-t_o...:...p_C_od_e_o_f_J __ u_m_-'-p_R __ ou_tin_e_Op Code Address + 1 1 OffsetFFFF 1 Restart Address (LSB)IX + Offset 1 Operand DataOp Code Address+2 1 Next Op Code1 Op Code Address + 1 --f-- 1 Offset4 I 2 FFFF 1 Restart Address (LSB)3 IX+Offset 0 Accumulator Data4 Op Code Address + 2 1 Next Op CodeAOOO--------1 Op Code Address+ 1 1 OffsetCPX LDD 2 FFFF 1 Restart Address (LSB)LOS LOX 5 3 IX + Offset 1 Operand Data (MSB)SUBD 4 IX + Offset+ 1 1 Operand Data (LSB)5 Op Code_Address+~ ____ ~_ Next Op Code ____________ _- -oS=T=D,.--------::S=T=S,.------STX1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)5 3 IX + Offset 0 Register Data (MSB)4 IX + Offset + 1 0 Register Data (LSB)I-JSR-----[---+--}--- -g~ ~~:: ~~~::: ~}-------0~1~~::tOP Code12 FFFF Restart Address (LSB)5 3 Stack Pointer Return Address (LSB)4 Stack Pointer-1 0 Return Address (MSB)-----;--..-;-----co-==----t---I_~-f--~±Offset---------- First Subroutine Op CodeASL ASR1 Op Code Address + 1 1 Offset - -----COM DEC I 2 FFFF 1 Restart Address (LSB)INC LSRI3 IX + Offset 1 I Operand Data6NEG ROL4 I FFFF 1 Restart Address (LSB)ROR5 IX + Offset 0 New Operand DataI 6IOp Code Address+ 1 1 Next Op Code-----TIM1 Op Code Address+1 ----'Immediate Data2 Op Code Address+2 1 Offset5 3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 Op Code Address + 3 1 Next Op Code------,;;C';-L-;;;cR--------+--------1- Op Code Address + 1 1 Offset ---AIMOIMElMI2 FFFF 1 Restart Address (LSB)5 3 IX + Offset 1 Operand Data74 IX + Offset 0 005 Op Code Address+2 1 Next Op Code1 Op Code Address+ 1 1 Immediate Data2 Op Code Address+2 1 Offset3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 FFFF 1 Restart Address (LSB)6 I IX + Offset -0 New Operand Data7 Op Code Address+3 1 Next Op Code- Continued -344$ HITACHI

II . 2I 424OpAddressDestination1-------Aijcfress- 1.•NextTable 12 Cy.cle-by-Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusEXTENDJMP1 Op Code Address + 1 ,1 Jump Address (MSB)3 2 I Op Code Address+2 ! 1 I Jump Address (LSB)3 I Jump Address Next Op Code-ADC-ADD-rsrT - - --,'- Op Code Address+,-----r---,-r Address of Operan(f(~rSBr-ACNMDp BEOITR 4 ! I Op Code Address+2 1! Address of Operand (LSB)I 3 'I of Operand I Operand DataLOA ORA I I Op Code Address+3 i 1 i Op CodeSBC SUB : I I :- STA-----------r----t---'--Top Code AddressIT----~---i Destination Address (rinSB)ADDDCPXLOS'SUBDSTDSTXJ5RASLCOMINCNEGRORCLRLDDLOXSTSASRDECLSRROLi! Op Code Address+2 1 Destination Address (LSB)I 4 3 Address 0 Accumulator Data: : 4 I Op Code Address +3 Next Op Code-r---t-,-t--op CodeAdCfress+ 1 --.- I of Operand (MSSf2 ! Op Code Address+2 Address of Operand (LSB)5 3 I Address of Operand Operand Data (MSB)I Address of Operand + 1 1 Operand Data (LSB)-'------r-}---~g~-~~~: :~~*~~~------; --}- -~--~:::i~!i~~~dreSS(MSBri-j---III----------.1. tiIII2 : Op Code Address+2 1 Destination Address (LSB)5 3 Destination Address 0 Register Data (MSB)4 Destination Address+ 1 0 Register Data (LSB)5 Code Address+3 Next Op Code- f - top CodeAddress+ 1 - - - >-- 1 ----Jump Address(~.,rS-Br2 Op Code Address+2 1 Jump Address (LSB)3 FFFF 1 ! Restart Address (LSB)6 I 4 Stack Pointer . 0 i Return Address (LSB)'5 Stack Pointer-1 i 0 I Return Address (MSB)I 6 Jump Address ! " 1 n: Fi;rst Subroutine Op Code-r --1-- - Op Code Address + 1 -r --,- Address of Operand (MSB)-! 2 Op Code Address+2 i 1 Address of Operand (LSB)6 I 3 Address of Operand : 1 ,Operand DataI 4rFFFF 1 i Restart Address (LSB)I 5 Address of Operand I 0 I New Operand Data6 Op Code Address+3 ! Next Op Code---,- -Op-Code Address+ 1---I --l-i Address of Operand (MSB)i 2 Op Code Address+2 i 1 I Address of Operand (LSB)5 I 3 I Address of Operand ! 1 'Operand Data, Address of Operand 0 00OJ) Code Address+3 1 Next Op Code- Continued -_HITACHI 345

i I 3I 4FFFF1--~-L1HD6303R,HD63A03R,HD63B03R----------------------Table 12 Cycle-by-Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusIMPLIEDABA ABX Op Code Address+ 1 Next Op CodeASL ASLDASR CBACLC CLICLR CLVCOM DECDES DEXINC INSINX LSRLSRD ROLROR NOPSBA SECSEI SEVTAB TAPTBA TPA-- 6~! ------xGDx-t ----+-, 0" Code-Adcrress + 1 --~T-T--+-NextOP Code ----------TST TSX I Ii 2 I 2 FFFF !'Restart Address (LSB)-POIA-PULEf---r--;- T 2 ~:F~ode Address + 1 ~ ~::t~~PA~~~:SS~~-~)----Stack Pointer + 1 i 1 Data from StackPSHA PSHB t-~+-i- Op Code Address + 1 t---,- Next Op CodeI 4 I 2 FFFF 1 Restart Address (LSB)I I 3 Stack Pointer 0 Accumulator DataI ---L- 4 Op Code Address + 1 1 Next Op Code-PUCX------~ I -, Op Code Address + 1--[' Next Op Code --------------i 2 I FFFF Restart Address (LSB)' 3 Stack Pointer + 1 Data from Stack (MSB)l___._ .___ ._______.._ :. 4 1_ Stack Pointer + 2L, Data from Stack (LSB)PSHX+--------r--r- Op Code Address+ 1 i 1 I Next Op CodeI I 2 FFFF i I Restart Address (LSB)5 3 I Stack Pointer :, 0 ,Index Register (LSB)I 4, Stack Pointer-1 ! 0 _~Index Register (MSB)rI 5 Op Code Address + 1 : 1 Next Op CodeNext Op CodeRTS~~-~- ----if Op Code Address+-1 ----r-,-I 2 FFFF I 1 I Restart Address (LSB)5 I 3 Stack Pointer + 1 I 1 Return Address (MSB)4 Stack Pointer+2 ! 1 Return Address (LSB)MUC-~-----t----I}-- ~~t~:d~d:~~~:ss+ 1 !~ +1 ~:~~6~~d:d~ Return R~ir1~II2 FFFF I Restart Address (LSB)3 Restart Address (LSB)7 4 FFFF Restart Address (LSB)5 FFFF Restart Address (LSB)6 FFFF Restart Address (LSB)7 FFFF Restart Address (LSB)- Continued -346eHITACHI

---.....--------------------HD6303R,HD63A03R,HD63B03RTable 12 Cycle-by·Cycle Operation (Continued)Address Mode 8tInstructionsAddress BusData BusIMPLIED-WAIRTISWISlPII9101241 Op Code Address + 1 12 FFFF 13 Stack Pointer 04 Stack Pointer - 1 0Stack Pointer - 2 0~Stack Pointer - 3 0Stack Pointer-4 0Stack Pointer-5Stack Pointer - 6Op Code Address+ 1t-~FFFF3 Stack PointerI ~4 Stack Pointer + 1 15 Stack Pointer+2 16 Stack Pointer + 3 17 Stack Pointer+4 18 Stack Pointer + 5 19 Stack Pointer + 6 110 Return Address 11 Op Code Address+ 1 12 FFFF 13 Stack Pointer 04 Stack Pointer - 1 05 Stack Pointer - 2 06 Stack Pointer - 3 07 Stack Pointer - 4 0I 8 Stack Pointer - 5 0I 9 Stack Pointer - 6 010 Vector Address FFFA 111 Vector Address FFFB 112 i Address of SWI Routine 1I Op Code Address + 1 1~ I FFFF 1FFFF5J.P I! I FFFFOp Code Address+ 1Next Op CodeRestart Address (lSB)Return Address (lSB)Return Address (MSB)Index Register (lSB)Index Register (MSB)Accumulator. AAccumulator BConditional Code RegisterNext Op CodeRestart Address (lSB)Conditional Code RegisterAccumulator BAccumulator AIndex Register (MSB)Index Register (lSB)Return Address (MSB)Return Address (lSB)First Op Code of Return _~utineNext Op CodeRestart Address (lSB)Return Address (lSB)Return Address (MSB)Index Register (lSB)Index Register (MSB)Accumulator AAccumulator BConditional Code RegisterAddress of SWI Routine (MSB)Address of SWI Routine (lSB)First Op Code of SWI RoutineNext Op CodeRestart Address (lSB)High Impedance· Non MPX Mod eAddress Bus -MPX Mode1Restart Address (lSB)Next Op Code- Continued -eHITACHI347

Table 12 Cycle-by-Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusRELATIVEBCC BCS1 Op Code Address + 1 1 Branch Offset!BEQ BGE I 3 2 FFFF I 1 Restart Address (lSB)BGT BHI { Branch Address· ....·Test="'" I First Op Code of Branch Routine31BlE BlSOp Code Address+ ''''Test="O''Next Op CodeBlT BMT IBNE BPlBRA BRNBVC BVS- BSR----- ~f-----1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (lSB)5 3 Stack Pointer 0 Return Address (lSB)4 Stack Pointer-1 0 Return Address (MSB)5 Branch Address1 First Op Code of Subroutine• LOW POWER CONSUMPTION MODEThe HD6303R has two low power consumption modes; sleepand standby mode .• SleepMocleOn execution of SLP instruction, the MPU is brought to thesleep mode. In the sleep mode, the CPU sleeps (the CPU clockbecomes inactive), but the contents of the registers in the CPUare retained. In this mode, the peripherals of CPU will remainactive. So the operations such as transmit and receive of theSCI data and counter may keep in operation. In this mode,the power consumption is reduced to about 1/6 the value of anormal operation.The escape from this mode can be done by interrupt, RES,S'fIlY. The RES resets the MPU and the STBY brings it into thestandby mode (This will be mentioned later). When interrupt isrequested to the CPU and accepted, the sleep mode is released,then the CPU is brought in the operation mode and jumps tothe interrupt routine. When the CPU has masked the interrupt,after recovering from the sleep mode, the next instruction ofSLP starts to execute. However, in such a case that the timerinterrupt is inhibited on the timer side, the sleep mode cannotbe released due to the absence of the interrupt request to theCPU.This sleep mode is available to reduce an average powerconsumption in the applications of the HD6303R which maynot be always running.• Standby,..Bringing "STBY "Low", the CPU becomes reset and allclocks of the HD6303R become inactive. It goes into thestandby mode. This mode remarkably reduces the power consumptionsof the HD6303R.In the standby mode, if the HD6303R is continuously suppliedwith power, the contents of RAM is retained. The standbymode should escape by the reset start. The foUowina is thetypical application of this mode.First, NMi routine stacks the CPU's internal information andthe contents of SP in RAM, disables RAME bit of RAM controlregister, sets the standby bit, and then goes into the standbymode. If the standby bit keeps set on reset start, it means thatthe power has been kept during stand-by mode and the contentsof RAM is normally guaranteed. The system recovery may bepossible by returning SP and bringing into the condition beforethe standby mode has started. The timing relation for each linein this application is shown in Figure 2l.VeeiiMiHD6303RSTivINMII \~,RESI2STBY~~IIII I II--of ~~~jlll~~~~ I\ Stack registers, RAM controlregister setFigure 21. Standby Mode Timingtime ~restart348 _HITACHI

-----------------------HD6303R,HD63A03R,HD63B03R• ERROR PROCESSINGWhen the HD6303R fetches an undefmed instruction orfetches an instruction from unusable memory area, it generatesthe highest priority internal interrupt, that may protect fromsystem upset due to noise or a program error.• Op-Code ErrorFetching an undefmed op-code, the HD6303R will stack theCPU register as in the case of a normal interrupt and vector tothe TRAP (SFFEE. SFFEF). that has a second highest priority(RB is the highest).• AcId,... ErrorWhen an instruction is fetched from other than a residentRAM, or an external memory area, the CPU starts the sameinterrupt as op-code error. In the case which the instruction isfetched from external memory area and that area is not usable,the address error can not be detected.The address which cause address error are shown in Table13.This feature is applicable only to the instruction fetch. not tonormal read/write of data acceuinJ.Transitions among the active mode, sleep mode. standbymode and reset are shown in Figure 22.Figures 23, 24 show a system configuration.The system flow chart of HD6303R is shown in Figure 25.Figure 22 Transitions among Active Mode, Standby Mode,Sleep Mode, and ResetTable 13 Address ErrorAddress Error$0000 - $001 FHD6303R MPU1e 8Address BusOlla BusAddress Bus011. BusFigure 23 HD6303R MPU Multiplexed ModeFigure 24 HD6303R MPU Non-Multiplexed ModeeHITACHI 349

HD6303R,HD63A03R,HD63B03R----------------------PCL~MSPPCH ~MSP-lIXL -~MSP-2IXH ~MSP-3ACCA·MSp·4ACCB ·MSp·5CCR ··MSP-6AFigure 25 HD6303R System Flow Chart350 eHITACHI

• PRECAUTION TO THE BOARD DESIGN OF OSCILLA­TION CIRCUITAs shown in Fig. 26, there is a case that the cross talk disturbsthe normal oscillation if signal lines are put near theoscillation circuit. When designing a board, pay attention tothis. Crystal and CL must be put as near the HD6303R aspossible.~ ~OJ OJc: c:iii '" iii '"CL ;~ ~-..--''-O XTAL• PIN CONDITIONS AT SLEEP AND STANDBY STATE• Sleep StateThe conditions of power supply pins, clock pins, input pinsand E clock pin are the same as those of operation. Refer toTable 14 for the other pin conditions.• Standby StateOnly power supply pins and STBY are active. As for theclock pin EXTAL, its input is fixed internally so the MPU isnot influenced by the pin conditions. XTAL is in "}" output.All the other pins are in high impedance.~~~~~EXTALmCLHD6303RDo not use this kind of print board design.Figure 26 Precaution to the boad designof oscillation circuitTable 14 Pin Condition in Sleep StatePinNon Multiplexed ModeMultiplexed Mode~Function I/O Port I/O PortP20"" P24Condition Keep the condition just before sleep ---....--AO/PIO - Function Address Bus (Ao-A,) I/O PortA,/P17- -ConditionOutput "1"Keep the condition just before sleepFunction Address Bus (As -A1S ) Address Bus (As -Au)As - AlSCondition Output "1"-Do/Ao - Function Data Bus (Do -07) E: Address Bus (Ao -A7), E: Data BusD7/A7 Condition High Impedance E: Output "1", E: High ImpedanceFunction RM Signal RIW SignalR/W-ConditionOutput "1"-- AS - Output ASPin~Table 15 Pin Condition during RESETNon-Multiplexed ModeP20 '" P24 High Impedance ..AO/PIO '" A7/P17 High Impedance ..As'" Au High Impedance ..Do/Ao '" D7/A,High ImpedanceR!W "1" Output ..ASE-: "1" Output..E : "0" OutputMultiplexed ModeE : "1" OutputE : High Impedance_HITACHI 351

HD6303R,HD63A03R,HD63B03R-----------------------• DIFFERENCE BETWEEN HD6303 AND HD6303RThe 806303R is an upgraded version of the 806303. Thedifference between H06303 and HD6303R is shown in Table16.Table 16 Difference between HD6303 and HD6303RItemOperatingModeElectricalCharacteristicsTimerHD6303Mode 2: Not definedHD6303RMode 2: MultiplexedMode(Equivalent to Mode 4)The electrical character- Some characteristicsistics of 2MHz version are improved.(B version) are not spec- The 2MHz version isified.guaranteed.Has problem in outputcompare function.(Can be avoided by software.)The problem is solved.352 $ HITACHI

HD6303X, H D63A03X,HD63B03XCMOS MPU (Micro Processing Unit)-PRELIMINARY-The HD6303X is a CMOS 8·bit microprocessing unit (MPU)which includes a CPU compatible with the HD630IVl, 192bytes of RAM, 24 parallel I/O pins, a Serial CommunicationInterface (SCI) and two timers on chip.HD6303XP, HD63A03XP,HD63B03XP• FEATURES• Instruction Set Compatible with the HD6301V1• Abundant On-chip Functions192 Bytes of RAM24 Parallel 1/0 Portsl6·Bit Programmable Timer8-Bit Reloadable TimerSerial Communication InterfaceMemory ReadyHaltError·Detection (Address Trap, Op Code Trap)• Interrupts ••. 3 External, 7 Internal.0 Up to 65k Words Address Space• Low Power Dissipation ModeSleepStandby• Wide Range of OperationVee = 3 - 6V (f = 0.1 - 0.5MHz).f = 0.5 -1.0MHz; HD6303X )Vee· 5V±10%(f = 0.5 -1.5MHz; HD63A03Xf = 0.5 - 2.0MHz; HD63B03X• PIN ARRANGEMENT• HD6303XP, HD63A03XP, HD63B03XPHD6303XF, HD63A03XF,HD63B03XF(DP-64S)(FP..sO)• HD6303XF, HD63A03XF, HD63B03XFV. EXTAL to 1m'EXTAL 3\WfMI'.R/'RMI',IJII'mBA'i'fI'l o.mii 0,.... I 0,1' .. 0,1'" 1 D.Pn t D.1',. D,1'" I D.1'" A.1'" A,1'" A,1' .. A,Pit A.Pit A,1'" I A,I'll A,1'"1'"VuI A •.... A.1'"A,.1'"All1' .. All1' .. Anpo. A ..1' .. 1 All1'"Vee(Top View)(Top View)$ HITACHI 353

HD6303X,HD63A03X,HD63B03X----------------------__• BLOCK DIAGRAMP2o(Tin)P21(Tout1)P22(SCLK)P23(Rx)P24(Tx)P2s(Tout2)P26(Tout3)P27(TCLK)Pso(iRIT1 1)PS1(TFm2i 2)PS2(M R)PS3(RAIT ALT)P S4P S5P SSP S7v cc--VssVssP SS -P 6S -~L--~~10cf-Ncf"--.....QjEi=Ur.nNQjE.=r---1.000..a:0010cfrDl ii 11 J J I II..J ..Joa:NO0..~ ~0 X XwI~ a:~ 0O'6,aa:l~00 a:a:a::E:x:A'IIAV1\ '4~A~~AVr-vCPU~I~ I~I~~III:lII)r---- 160AV~RAMJ192 BytesIII:lII)IIIIIIQ)-0'C---= e r--'0'0 t--« r--""'"--RDSAP S7 -354$ HITACHI

------------------------HD6303X,HD63A03X,HD63B03X• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee -0.3 - +7.0Input Voltage Yin -0.3 - Vee+0.3Operating Temperature Topr 0-+70Storage Temperature Tstg -55 - +150(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.But be careful not to apply overvoltage more than maximum ratings to these high input impedance protectioncircuits. To assure the normal operation, we recommend Vln, Vout: VSS ~ (Vin or Vout) ~ Vee.UnitVV°c°c• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee" 5.OV±10%, Vss" OV, Ta - O-+70°C, unless otherwise noted.)Item Symbol Test Condition minRES, STBY Vee-0 .5Input "High" Voltage EXTAL V IH VeexO.7Other Inputs 2.0Input "Low" Voltage All Inputs V IL -0.3I nput Leakage CurrentNMI, RES, STBY,MPo , MP 1 , Port 5lIinl Yin = 0.5-Vee-0.5V -Three State (off·state) Ao-A 1s , 0 0 -0 7 , RD,Leakage Current WR, R/IN ,Port 2,Port 6 IITsl1 Yin = 0.5-Vee-0.5V -IOH = -200IJA 2.4Output "High" Voltage All OutputsVOHIOH = -10IJA Vee-0 .7Output "Low" Voltage All Outputs VOL IOL -= 1.6mA -Darlington DriveCurrentInput Capacitance All Inputs CinPorts 2, 6 -IOH Vout = 1.5V 1.0Yin = OV, f = 1MHz,Ta = 25°CStandby Current Non Operation ISTB -Sleeping (f = 1MHz**) -Current Dissipation*ISLP Sleeping (f = '1.5MHz**) -Sleeping (f = 2MHz**) -Operating (f = 1MHz**) -Icc Operating (f = 1.5MHz**) -Operating (f = 2MHz**) -RAM Standby Voltage V RAM 2.0• V IH min = V ee-1,OV, V IL max = O.8V , All output terminals are at no load .•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.values about Current Dissipations at x MHz operation are decided according to the following formula;typo value (f = x MHz) = typo value (f = 1 MHz) x xmax. value (f = x MHz) = max. value (f = 1 MHz) x x(both the sleeping and operating)-typ max Unit--VeeV+0.3- 0.8 V- 1.0 IJA- 1.0 IJA- - V- - V- 0.4 V- 10.0 mA- 12.5 pF3.0 15.0 IJA1.5 ;3.0 mA2.3 4.5 mA3.0 6.0 mA7.0 10.0 mA10.5 15.0 mA14.0 20.0 mA- - V$ HITACHI355

HD6303X,HD63A03X,HD63B03X------------------------• AC CHARACTERISTICS (Vee" 5.0V±10%, Vss· OV, Ta· O-+70°C, unlen otherwise noted.)BUS TIMINGItemSymbolTest HD6303X HD63A03X HD63B03XCondition min typ max min typ max min ty!'> maxCycle Time tCYc 1 - 10 0.666 - 10 0.5 - 10Enable Rise Time tEr - - 25 - - 25 - - 25E;nable Fall Time tEf - - 25 - - 25 - - 25Enable Pulse Width "High" Level· PWEH 450 - - 300 - - 220 - -Enable Pulse Width "Low" Level· PWEL 450 - - 300 - - 220 - -Address, R/W Delay Time· tAD - - 250 - - 190 - - 160Data Delay Time I Write toow - - 200 - - 160 - - 120Data Set-up Time I Read tOSA 80 - - 70 - - 70 - -Fig. 1Address, RM Hold Time·tAH 80 - - 50 - - 35 - -I Write· tHW 80 - - 50 - - 40 - -Data Hold TimeI Read tHA 0 - - 0 - - 0 - -RD, WR Pulse Width· PWAW 450 - - 300 - - 220 - -RD, WR Delay Time tAWO - - 40 - - 40 - - 40A'l), WIf Hold Time tHAW - - 30 - - 30 - - 25OR Delay Time tOLA - - 200 - - 160 - - 120LI R Hold Time tHLA 10 - - 10 - - 10 - -MR Set·up Time· tSMA 400 - - 280 - - 230 - -MR Hold Time· tHMA Fig. 2 - - 90 - - 40 - - 0E Clock Pulse Width at MR PWEMA - - 9 - - 9 - - 9Fig. 3,Processor Control Set-up Time tpcs200 - - 200 - - 200 - -10 11Processor Control Rise Time tpcr - - 100 - - 100 - - 100Fig. 2,3Processor Control Fall Time tPCf- - 100 - - 100 - - 100BA Delay Time tBA Fig. 3 - - 250 - - 190 - - 160Oscillator Stabilization Time tAC Fig. 11 20 - - 20 - - 20 - -Reset Pulse Width PWAST 3 - - 3 - - 3 - -* These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum(. in the highest speed operation).UnitI.lsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsI.lsnsnsnsnsmstCYCPERIPHERAL PORT TIMINGPeripheral DataSet·upTimePeripheral DataHold TimeDeIaV T;me (Enabl.Test HD6303X HD63A03X HD63B03XItemSymbolCondition min typ max min typ max min typ maxPorts 2, 5, 6 tposu Fig. 5 200 - - 200 - - 200 - -IPorts 2,5,6 tpOH Fig. 5 200 - - 200 - - 200 - -Negative Transition to Ports 2, 6 tpwo Fig. 6 - - 300 - - 300 - - 300Peripheral Data Valid)Unitnsnsns356 _HITACHI

------------------------HD6303X,HD63A03X,HD63B03XTIMER SCI TIMINGItemSymbolTest HD6303X HD63A03X HD63B03XCondition min tyJl_ max min t'lP max min tYQ maxUnitTimer 1 Input Pulse Width tPWT Fig.8 2.0 - - 2.0 - - 2.0 - - tCycDelay Time (Enable PositiveTransition to Timer Output)tTOD Fig. 7 - - 400 - - 400 - - 400 nsSCI Input Async. Mode Fig.8 1.0 - - 1.0 - - 1.0 - - tCYCClock Cycle I tSCYCClock Sync.Fig. 4. 8 2.0 - - 2.0 - - 2.0 tcycSCI Transmit Data DelayTime (Clock Sync. Mode)SCI Receive Data Set-upTime (Clock Sync. Mode)SCI Receive Data Hold Time(Clock Sync. Mode)tTXD - - 200 - - 200 - - 200 nstSRx Fig.4 290 - - 290 - - 290 - - nstHRX 100 - - 100 - - 100 - - nsSCI Input Clock Pulse Width tpwSCK 0.4 - 0.6 0.4 - 0.6 0.4 - 0.6 tscyCTimer 2 Input Clock Cycle ttcvc 2.0 - - 2.0 - - 2.0' - - t cvcTimer 2 Input Clock PulseWidthTimer 1·2. SCI Input ClockRise TimeTimer 1·2. SCI Input ClockFall TimetpwTCK 200 - - 200 - - 200 - - nsFig.8tCKr - - 100 - - 100 - - 100 nstCKf - - 100 - - 100 - - 100 ns~HITACHI 357

HD6303X,HD63A03X,HD63B03X-----------------------1-----------tCyC-----------"IEt------PWEL---........!-----PW£H----o-42.4VO.BVt£,MPU Write00-07MPU Read00-07Figure 1 Bus Timingt------PW£MR-----........EMR-t---+--tHMR\\\'-----O.BVFigure 2 Memory Ready and E Clock Timing358_HITACHI

------------------------HD6303X,HD63A03X,HD63B03XInstruction ExecutionCycleEBAFigure 3 HALT and BA TimingSynchronous ClockTransmit DataReceive DataFigure 4 SCI Clocked Synchronous Timing* 2.0V is high level when clock input.2.4V is high level when clock output.EI MPU WriteP20-P27PSO-PS7 _______..I I\o'::";':;~--(Outputs)Figure 5 Port Data Set-up and Hold Times (MPU Read)Figure 6 Port Data Delay Times (MPU Write)~HITACHI 359

\~ _______________________HD6303X,HD63A03X,HD63B03X.---------------~--------ETimer 1 ----- ,....., ...... -.;..;=~ ,----FRCP2I, P 25 ------....:..-... ~-,:-:~--­Outputs ---------' 'Jt~:.l:...---ET2CNTPH Output _____-'TCONR = N(a) Timer 1 Output Timing(b) Timer 2 Output TimingFigure 7 Timer Output Timing• *.htCKf• Timer 2; ttcycSCI ; tscyc**•• Timer 1; tPWTTimer 2; tPWTCKSCI ;tPWSCKFigure 8 Timer 1·2, SCI Input Clock TimingVeemRl =2.2kQTest Point152074(8)C R or Equiv .C =90pF for 0 0 -0 7 , Ao-A I 5, E=30pF for Port 2, Port 6, RO, WR, R/W, BA, LI RR=12kil for 0 0 -0 7 , Ao-A I 5, E, Port 2, Port 6,RO, W"R, R/W, BA, LI RFigure 9 Bus Timing Test Loads (TTL Load)InterruptTestInternalAddress Bus -_J,-+ ...... "-_-" __ "-_..J'~_"'-_...J'-_J'\_....J"__J'\ ___ "__..r. _ _'''-_..r. __NMi. iRQ..iRih. IRQ,''__..J''_InternalDataBus ___ J'\_ ......"__..r.__......"-_..J'~_~_...J~_J'\_ _J"__~_....J"__..r._....J"__~_~"__..r.~IXO - IX8 - ACCA ACCB CCR Vector Vector Forst Inst. ofIX 7 IX 15 MSB LSB Interrupt RoutineInlernalReadInternalWrite-JI______ -.J 1,Figure 10 Interrupt Sequence360$ HITACHI

------------------------HD6303X,HD63A03X,HD63B03X~~,.ss .. *\\\\\\\\\\\\\IC:X=::::x::r-----r~FFFF FFFF FFH FFFF FFFF FFFf FFFF _ PC • "'-nFF FFFF FFFFW,omo' 1\\S»_,\\\\i\\.'~\~~~r___________Woma' ~lm'ltl+I"I'I;.14.1l\'l.--_J----_-_-_-_~:,~~.1--____ _AllWR_)\«\\\\\\\\\\\1\­_~\»»§\\\\\\\\~\\\\\\.!~~~'II J~~'l-J ----~aJIII'l"lrl;IIIIIIIIII;~------~~J,II PC8- PCO- FirstPC1S PC7 Instructiont~r~!--------Figure 11 Reset Timing• FUNCTIONAL PIN DESCRIPTION• Vee, VssVee and Vss provide power to the MPU with 5V±IO% supply.In the case of low speed operation (fmax = 500kHz), theMPU can operate with three through six volts. Two Vss pinsshould be tied to ground.• XTAL,EXTALThese two PulS interface with an AT -cut parallel resonantcrystal. Divide-by-four circuit is on chip, so if 4MHz crystaloscillator is used, the system clock is IMHz for example.AT Cut Parallel Resonant Crystal OscillatorCo=7pF maxRs=60Q maxXTAL~--~----~CJEXTALt---..-..,J- CL2 .J,.CL1(a)Crystal InterfaceCL 1 =CL2= 10pF-22pF+ 20%(3.2-SMHzlXTAL~N.C.EXTAL External Clock(b) External ClockFigure 12 Connection CircuitEXT AL pin is drivable with the external clock of 45 to50% duty, and one fourth frequency of the external clockis produced in the LSI. The external clock frequency shouldbe less than four times of the maximum operable frequency.When using the external clock, XT AL pin should be open.Fig. 12 shows examples of connection circuit. The crystal andC l1 , C l2 should be mounted as close as possible to XT ALand EXT AL pins. Any line must not cross the line between thecrystal oscillator and XT AL, EXT AL.• STiiYThis pin makes the MPU standby mode. In "Low" level, theoscillation stops and the internal clock is stabilized to makereset condition. To retain the contents of RAM at standby,"0" should be written into RAM enable bit (RAME). RAMEis the bit 6 of the RAM/port 5 control register at $0014. RAMis disabled by this operation and its contents is sustained.Refer to "LOW POWER DISSIPATION MODE" for thestandby mode.• Reset (RES)This pin is used to reset the MPU from power OFF stateand to provide a startup procedure. During power-on, RESpin must be held "Low" level for at least 20ms.The CPU registers (accumulator, index register, stack pointer,condition code register except for interrupt mask bit), RAMand the data register of a port are not initialized during reset,so their contents are unknown in this procedure.To reset the MPU during operation, RES should be held"Low" for at least 3 system-clock cycles. At the 3rd cycleduring "Low" level, all the address buses become "High". WhenRES remains "Low", the address buses keep "High". If RESbecomes "High", the MPU starts the next operation.(I) Latch the value of the mode program pins;MPo and MP t •~HITACHI 361

HD6303X,HD63A03X,HD63B03X--------------------__ _(2) Initialize each internal register (Refer to Table 3).(3) Set the interrupt mask bit. For the CPU to recognize themaskable interrupts IRQ\ , IRQ2 and IRQ3, this bit shouldbe cleared in advance.(4) Put the contents (= start address) of the last two addresses($FFFE, $FFFF) into the program counter and start theprogram from this address. (Refer to Table 1).*The MPU is usable to accept a reset input until the clockbecomes normal oscillation after power on (max. 20ms). Duringthis transient time, the MPU and I/O pins are undefined. Pleasebe aware of this for system designing.• Enable (EIThis pin provides a TTL-compatible system clock to externalcircuits. Its frequency is one fourth that of the crystal oscillatoror extemal clock. This pin can drive one TTL load and 90pFcapacitance.• Non·Maskable Interrupt (NMI)When the falling edge of the input signal is detected at thispin, the CPU begins non-maskable interrupt sequence internally.As well as the IRQ mentioned below, the instruction beingexecuted at NMI signal detection will proceed to its completion.The interrupt mask bit of the condition code register doesn'taffect non-maskable interrupt at all.When starting the acknowledge to the NMI, the contents ofthe program counter, index register, accumulators and conditioncode register will be saved onto the stack. Upon completionof this sequence, a vector is fetched from $FFFC and $FFFDto transfer their contents into the program counter and branchto the non-maskable interrupt service routine. After reset start,the stack pointer should be initialized on an appropreate memoryarea and then the falling edge be input to NMT pin.• Interrupt Request (lRQ\, IRQ2)These are level-sensitive pins which request an internalinterrupt sequence to the CPU. At interrupt request, the CPUwill complete the current instruction before its request acknowledgement.Unless the interrupt mask in the condition coderegister is set, the CPU starts an interrupt sequence; if set, theinterrupt request will be ignored. When the sequence starts, thecontents of the program counter, index register, accumulatorsand condition code register will be saved onto the stack, thenthe CPU sets the interrupt mask bit and will not acknowledgethe maskable request. During the last cycle, the CPU fetchesvectors depicted in Table 1 and transfers their contents to theprogram counter and branches to the service routine.The CPU uses the external interrupt pins, IRQ\ and IRQ2also as port pins P 50 and P 5), so it provides an enable bit toBit 0 and I of the RAM port 5 control register at $0014. Referto "RAM/PORT 5 CONTROL REGISTER" for the details.When one of the internal interrupts, ICI, OCI, TOI, CMI orSIO' is generated, the CPU produces internal interrupt signal(IRQ3)' IRQ3 functions just the same as IRQ\ or IRQ2 exceptfor its vector address. Fig. 13 shows the block diagram of theinterrupt circuit.PriorityMSBTable 1 Interrupt Vector Memory MapVectorLSBHighest FFFE FFFF RESFFEE FFEF TRAPFFFC FFFD NMIInterruptFFFA FFFB SWI (Software Interrupt)FFF8 FFF9 IRQ\FFF6 FFF7 ICI (Timer 1 Input Capture)FFF4 FFF5 OCI (Timer 1 Output Compare 1, 2)FFF2 FFF3 TOI (Timer 1 Overflow)FFEC FFED CM I (Timer 2 Counter Match)FFEA FFEB IRQ 2Lowest FFFO FFFl SIO (RDRF+ORFE+TDRE)362~HITACHI

------------------------HD6303X,HD63A03X,HD63B03XiRQ,1FiQ2ICFOCF'Each Register's InterruptEnable Flag"'''; Enable, "0"; DisableConditionCode---+-~ 0-+----1 RegisterI·MASK---HY" o-+-.......;.::~~· .. O ..;Enable"''';DisablIRQ3OCF2TOFCMFRDRFORFETOREInterruptRequestSignalSleepCancelSignalTRAPSWIFigure 13 Interrupt Circuit Block Diagram• Mode Program (MPo, MP.)To operate MPU, MP o pin should be connected to "High"level and MP. should be connected to "Low" level (refer toFig. 15).• Read/Write (R/W)This signal, usually be in read state ("High"), shows whetherthe MPU is in read ("High") or write ("Low") state to theperipheral or memory devices. This can drive one TTL loadand 30pF capacitance.• RD,WRThese signals show active low outputs when the CPU isreading/writing to the peripherals or memories. This enablesthe CPU easy to access the peripheral LSI with RD and WRinput pins. These pins can drive one TTL load and 30pF capacitance.• Load Instruction Register (lIR)This signal shows the instruction opecode being on databus (active low). This pin can drive one TTL load and 30pFcapacitance.• Memory Ready (MR; PS2 )This is the input control signal which stretches the systemclock's "High" period to access low-speed memories. Duringthis Signal being in "High", the system clock operates in normalsequence. But this signal in "Low", the "High" period of thesystem clock will be stretched depending on its "Low" levelduration in integral multiples of the cycle time. This allows theCPU to interface with low·speed memories ,see Fig. 2). Up to9 p.s can be stretched.During internal address space access or nonvalid memoryaccess, MR is prohibited internally to prevent decrease of operationspeed. Even in the halt state, MR can also stretch "High"period of system clock to allow peripheral devices to accesslow-speed memories. As this signal is used also as P 52 , an enablebit is provided at bit 2 of the RAM/port 5 control register at$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" formore details.• Halt(HALT;P 53 )This is an input control signal to stop instruction executionand to release buses free. When this signal switches to "Low",the CPU stops to enter into the halt state after haVing executedthe present instruction. When entering into the halt state, itmakes BA (P 74 ) "High" and also an address bus, data bus, RD,WR, R/W in high impedance. When an interrupt is generatedin the halt state, the CPU uses the interrupt handler after thehalt is cancelled. When halted during the sleep state, the CPUkeeps the sleep state, while BA is "High" and releases the buses.Then the CPU returns to the previous sleep state when theHALT signal becomes "High". The same thing can be said whenthe CPU is in the interrupt wait state after having executed theWAI instruction.• Bus Available (BA)This is an output control signal which is normally "Low"but "High" when the CPU accepts HALT and releases the buses.The H06800 and H06802 make BA "High" and release thebuses at WAI execution, while the HD6303X doesn't make_HITACHI 363

HD6303X,HD63A03X,HD63B03X------------------------BA "High" under the same condition. But if the HALT becomes"Low" when the CPU is in the interrupt wait state after havingexecuted the WAI, the CPU makes BA "High" and releases thebuses. And when the HALT becomes "High", the CPU returnsto the interrupt wait state.• PORTThe HD6303X provides three I/O ports. Table 2 gives theaddress of ports and the data direction register and Fig. 14the block diagrams of each port.Table 2 Port and Data Direction Register AddressPort Port Address Data Direction RegisterPort 2 $0003 $0001Port 5 $0015 -Port 6 $0017 $0016• Port2An g·bit input/output port. The data direction register(DDR) of port 2 is responsible for I/O state. It provides twobits; bit 0 decides the I/O direction of P 20 and bit I the I/Odirection of P 2I to P 27 ("0" for input, "I" for output).Port 2 is also used as an I/O pin for the timers and theSCI. When used as an I/O pin for the timers and the SCI, port2 except P 20 automatically becomes an input or an outputdepending on their functions regardless of the data directionregister's value.Port 2 Data Direction Register654 3 210A reset clears the DDR of port 2 and configures port 2 as aninput port. This port can drive one TTL and 30pF. In addition,it can produce I rnA current when Vout = 1.5V to drive directlythe base of Darlington transistors.Port Write SignalData BusData BusTimer 1. 2.~+-___ ....SCI OutputPort Read Signal-L.Tri·stateControlTimer 1. 2. _________

~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03Xinterrupt or a sleep cancellation by the external interrupt.These bits become "0" during reset.Bit 2 Memory Ready Enable Bit (MRE)When using P S2 as an input for Memory Ready signal, write"I" in this bit. When "0", the memory ready function is prohibited.This bit becomes "I" during reset.Bit 3 Halt Enable bit (HL TE)When using P S3 as an input for Halt signal, write "I" in thisbit. When "0", the halt function is prohibited. This bit becomes"I" during reset.Bit 4, Bit 5 Not Used.Bit 6 RAM Enable (RAME)On-chip RAM can be disabled by this control bit. TheMPlJ Reset sets "1" at this bit and enables on-chip RAMavailable. This bit can be written "1" or ''0'' by software.When RAM is in disable condition (=logic ''0''), on-chip RAMis invalid and the CPU can read data from external memory.This bit should be "0" at the beginning of standby mode toprotect on-chip RAM data.CJPort 281/0 LinesTimer 1.2p~ftl58:m;~~MR. HAIiPort 681/0 LinesFigure 15 Operation ModeEm5WRR/WORBA8 Data Bus16 AddressBusBit 7 Standby Power Bit (STBY PWR)When Vee is not provided in standby mode, this bit iscleared. This is a flag for both read/write by software. If this bitis set before standby mode, and remains set even after returningfrom standby mode, Vee voltage is provided during standbymode and the on-chip RAM data is valid.Table 3 Internal Register• MEMORY MAPThe MPU can address up to 65k bytes. Fig. 16 gives memorymap of HD6303X. 32 internal registers use addresses from "00"as shown in Table 3.Address000102*0304*0506*07*0809OAOBOC00OEOF10111213141516Registers RIW*** Initialize at RESET- - -Port 2 Data Direction Register W $FC- - -Port 2 RIW Undefined- - -- --- - -- - -Timer Control/Status Register 1 RIW SOOFree Running Counter ("High") RIW $00Free Running Counter ("Low") RIW $00Output Compare Register 1 ("High") RIW $FFOutput Compare Register 1 ("Low") R/W $FFInput Capture Register ("High") R $00Input Capture Register ("Low") R SOOTimer Control/Status Register 2 RIW $10Rate. Mode Control Register RIW $00Tx/Rx Control Status Register RIW $20Receive Data Register R $00Transmit Data Register W $00RAM/Port 5 Control Register RIW $7C or $FCPort 5 R -Port 6 Data Direction Register W SOO(continued)~HITACHI 365

HD6303X,HD63A03X,HD63B03X-----------------------Table 3 Internal RegisterAddress Registers RIW*** Initialize at RESET17 Port 6 RIW Undefined18* - - -19 Output Compare Register 2 ("High") RIW $FF1A Output Compare Register 2 ("Low") RIW $FF1B Timer Control/Status Register 31CTime Con.stant Register10 Timer 2 Up Counter1E -1F** Test Register• External Address .•• Test Register. Do not access to this-register .••• R : Read Only RegisterW : Write Only RegisterRIW: Read/Write RegisterRIW $20W$FFRIW $00----H06303XExpanded ModeInternal·Registers$001F ""~~~~< Externalm"""":I"7'!~H MemorySpaceInternalRAM$OOFF F-'"'~~~:h'and incremented by system clock. The counter value is readableby software without affecting the counter. The counter iscleared by reset.When writing to the MSB byte ($09), the CPU writes thepreset value ($FFF8) into the counter (address $09, $OA)regardless of the write data value. But when writing to theLSB byte ($OA) after MSB byte writing, the CPU write notonly LSB byte data into lower 8 bit, but also MSB byte datainto higher 8 bit of the FRC.The counter will be as follows when the CPU writes to itby double store instructions (STD, STX etc.).$09 Write $OA WriteExternalMemorySpaceCounter value $FFF8 $5AF3$FFFF &-.___.J'• Excludes the following addresseswhich may be used externally:$02, $04, $06, $07, $18.Figure 16 H06303X Memory MapIn the case of the CPU write ($5AF31 to the FRCFigure 17 Counter Write Timing• Output Compare Register (OCR)($OOOB,SOOOC; OCR1) (S0019,$O01A ;OCR2)The output compare· register is a 16-bit read/write registerwhich can control an output waveform. It is always comparedwith the FRC.When data matches, output compare flag (OCF) in the timercontrol/status register (TCSR) is set. If an output enable bit(OE) in the TCSR2 is "1", an output level bit (OLVL) in theTCSR will be output to bit 1 (Tout 1) and bit 5 (Tout 2) ofport 2. To control the output level again by the next compare, achange is necessary for the OCR and OLVL. The OCR is set to$FFFF at reset. The compare function is inhibited for a cyclejust after a write to the OCR or to the upper byte of theFRC. This is to set the 16-bit value valid in the register forcompare. In addition, it is because $FFF8 is set at the nextcycle of the CPU's MSB byte write to the FRC.* For data write to the FRC or the OCR, 2-byte transferinstruction (such as STX etc.) should be used.• TIMER 1The HD6303X provides a 16-bit programmable timer whichcan measure an input waveform and generate two independentoutput waveforms. The pulse widths of botlt input/outputwaveforms vary from microseconds to seconds.Timer 1 is configurated as follows (refer to Fig. 18).• Control/Status Register 1 (8 bit)• Control/Status Register 2 (7 bit)• Free Running Counter (16 bit)• Output Compare Register 1 (16 bit)• Output Compare Register 2 (16 bit)• Input Capture Register ( 16 bit)• Input Capture Register (lCR) ($0000: ooOE)• Free·Running Counter (FRC) ($0009 : OOOA)The input capture register is a 16-bit read only register whichThe key timer element is a 16-bit free-running counter driven stores the FRC's value when external input signal transition366 ~ HITACHI

-----------------------HD6303X,HD63A03X,HD63B03Xgenerates an input capture pulse. Such transition is defined byinput edge bit (IEDG) in the TCSRI.In order to input the external input signal to the edgedetecter, a bit of the DDR corresponding to bit 0 of port 2should be cleared ("0"). When an input capture pulse occuresby input transition at the next cycle of CPU's high-byte read ofthe ICR, the input capture pulse will be delayed by one cycle.In order to ensure the input capture operation, a CPU read ofthe ICR needs 2-byte transfer instruction. The input pulse widthshould be at least 2 system cycles. This register is cleared($0000) during reset.• Timer Control/Status Register 1 (TCSR1) ($0008)The timer control/status register 1 is an 8-bit register. All bitsare readable and the lower 5 bits are also writable. The upper 3bits are read only which indicate the following timer status.Bit 5 The counter value reached to $0000 as a result ofcounting-up (TOF).Bit 6 A match has occured between the FCR and the OCR 1(OCFl).Bit 7 Defined transition of the timer input signal causes thecounter to transfer its data to the ICR (ICF).The followings are each bit descriptions.Timer Control/Status Register 16 5 3the OCRI ($OOOB or $OOOC) folloWing the TCSRI orTCSR2 read.Bit 7 ICF Input Capture FlagThis read only bit is set when an input signal ofport 2, bit 0 makes a transition as defined by IEOO andthe FRC is transferred to the ICR. Cleared when readingthe MSB byte ($OOOOD) of the ICR following theTCSRI or TCSR2 read.• Timer Control/Status Register 2 (TCSR2) ($OOOF)The timer control/status register 2 is a 7-bit register. All bitsare readable and the lower 4 bits are also writable. But theupper 3 bits are read-only which indicate the follOWing timerstatus.Bit 5 A match has occured between the FRC and the OCR2Bit 6(OCF2).The same status flag as the OCFI flag of the TCSRI,bit 6.Bit 7 The same status flag as the ICF flag of the TCSRl, bit 7.The followings are each bit descriptions.Timer Control/Status Register 276543210ICF IOCF110CF21 -~OC'fLVL21 OE21 O~$OOOFBit 0 OEl Output Enable 1This bit enables the OLVLl to appear at port 2, bitBit 0 OLVL1 Output Levell 1 when a match has occurred between the counter andOLVLI is transferred to port 2, bit 1 when a matchthe output compare register 1. When this bit cleared, bitoccurs between the counter and the OCRI. If OEI,1 of port 2 will be I/O port. When set, it will be annamely, bit 0 of the TCSR2, is set to "1", OLVLl willoutput ofOLVLl automatically.appear at bit 1 of port 2. Bit 1 OE2 Output Enable 2Bit 1 IEDG Input Edge This bit enables the OLVL2 to appear at port 2, bitThis bit determines which rising edge or falling of5 when a match has occurred between the counter andinput signal of port 2, bit 0 will trigger data transferthe output compare register 2. When this bit cleared,from the counter to the ICR. For this function, theport 2, bit 5 will be I/O port. When set, it will be anDDR corresponding to port 2, bit 0 should be clearedoutput of OLVL2 automatically.beforehand. Bit 2 OL VL2 Output Level 2IEOO=O, triggered on a falling edgeOLVL2 is transferred to port 2, bit 5 when a match("High" to "Low")has occurred between the counter and the OCR2. IfIEDG= 1, triggered on a rising edgeOE2, namely bit 5 of the TCSR2, is set to "1", OLVL2("Low" to "High") will appear at port 2, bit 5.Bit 2 ETOI Enable Timer Overflow Interrupt Bit 3 EOCI2 Enable Output Compare Interrupt 2When this bit is set, an internal interrupt (IRQ3) byWhen this bit is set, an internal interrupt (IRQ3) byTOI interrupt is enabled. When cleared, the interrupt isOCI2 interrupt is enabled. When cleared, the interruptinhibited.is inhibited.Bit 3 EOCll Enable Output Compare Interrupt 1 Bit 4 Not UsedWhen this bit is set, an internal interrupt (IRQ3) by Bit 5 OCF2 Output Compare Flag 2OCII interrupt is enabled. When cleared, the interruptThis read-only bit is set when a match has occurredis inhibited.between the counter ·and the OCR2. Cleared whenBit 4 EICI Enable Input Capture Interrupt writing to the OCR2 ($0019 or $OOIA) following theWhen this bit is set, an internal interrupt (IRQ3) byTCSR2 read.ICI interrupt is enabled. When cleared, the interrupt is Bit 6 OCFl Output Compare Flag 1inhibited. Bit 7 ICF Input Capture FlagBit 5 TOF Timer Overflow Flag OCFl and ICF addresses are partially decoded.This read only bit is set when the counter incre-CPU read of the TCSRl/TCSR2 makes it possible toments from $FFFF by 1. Cleared when the counter's read OCFl and ICF into bit 6 and bit 7.MSB byte ($0009) is ready by the CPU following the Both the TCSRI and TCSR2 will be cleared during reset.TCSR 1 read.(Note) If OEI or OE2 is set to "1" before the first outputBit 6 OCF 1 Output Compare Flag 1 compare match occurs after reset restart, bit I or bit 5This read only bit is set when a match occurs be-of port 2 will produce "0" respectively.tween the OCRI and the FRC. Cleared by writing to$ HITACHI 367

HD6303X,HD63A03X,HD63B03X------------------------Figure 18 Timer 1 Block Diagram(Note) Because the set condition of ICF precedes its resetcondition, ICF is not cleared when the set conditionand the reset condition occur simultaneously. Thesame phenomenon applies to OCF I, OCF2 or TOFrespectively.• TIMER2In addition to the timer I, the HD6303X provides an 8·bitreloadable timer, which is capable of counting the externalevent. This timer 2 contains a timer output, so the MPU cangenerate three independent waveforms (refer to Fig. 19).The timer 2 is configured as follows:Control/Status Register 3 (7 bit)8·bit Up CounterTime Constant Register (8 bit)• Timer 2 Up Counter (T2CNT) ($0010)This is an 8·bit up counter which operates with the clockdecided by CKSO and CKSI of the TCSR3. The counter isalways readable without affecting itself. In addition, any valuecan be written to the counter by software even during counting.The counter is cleared when a match occurs between thecounter and the TCONR or during reset.If a write operation is made by software to the counter at thecycle of counter clear, it does not reset the counter but put thewrite data to the counter.• Time Constant Register (TCONR) ($001C)The time constant. register is an 8·bit write only register. Itis always compared with the counter.When a match has occurred, counter match flag (CMF) ofthe timer control status register 3 (TCSR3) is set and the valueselected by TOSO and TOSI of the TCSR3 wiD appeal'at port 2,bit 6. When CMF is set, the counter will be cleared simultane·ously and then start counting from $00. This enables regularinterrupts and waveform outputs without any software support.The TCONR is set to "$FF" during reset.• Timer Control/Status Register 3 (TCSR3) ($001 B)The timer control/status register 3 is a 7·bit register. AU bitsare readable and 6 bits except for CMF can be written.The followings are each pin descriptions.Timer Control/Status Register 376543210I CMF IECMI\ - I T2E \TOS1\TOsoICKSlICKsol $0018368 $ HITACHI

-----------------------HD6303X,HD63A03X,HD63B03X,..----Timer1 FRC.... ----- Port 2Bit 7t-+---I------'i~ Port 2Bit 6Figure 19 Timer 2 Block DiagramBit 0 CKSO Input Clock Select 0Bit 1 CKS1 Input Clock Select 1Input clock to the counter is selected as shown inTable 4 depending on these two bits. When an externalclock is selected, bit 7 of port 2 will be a clock inputautomatically. Timer 2 detects the rising edge of theexternal clock and increments the counter. The externalclock is countable up to half the frequency of thesystem clock.Table 4 Input Clock SelectCKS1 CKSO Input Clock to the Counter0 0 E clock0 1 E clock/S*1 0 E clock/128*1 1 External clock• These clocks come from the FAC of the timer 1. If one of these clocksis selected as an input clock to the up counter, the CPU should notwrite to the FAC of the timer 1.Bit 2 TOSO Timer Output Select 0Bit 3 TOS1 Timer Output Select 1When a match occurs between the counter and theTCONR timer 2 outputs shown in Table 5 will appear atport 2, bit 6 depending on these two bits. When bothTOsa and TOSI are "0", bit 6 of port 2 will be an I/Oport.Table 5 Timer 2 Output SelectTOS1 TOSO Timer Output0 0 Timer Output Inhibited0 1 Toggle Output *1 0 Output "0"1 1 Output "1"• When a match occurs between the counter and the TCONA, timer 2output level is reversed. This leads to production of a square wave with50% duty to the external without any software support.Bit 4 T2E Timer 2 Enable BitWhen this bit is cleared, a clock input to the upcounter is prohibited and the up counter stops. When setto "I"', a clock selected by CKS) and CKSO (Table 4)is input to the up counter.(Note) P26 produces "0" when T2E bit cleared and timer 2 setin output enable condition by TOSI or TOsa. It alsoproduces "0" when T2E bit set "I" and timer 2 set inoutput enable condition before the first counter matchoccurs.Bit 5 Not UsedBit 6 ECMI Enable Counter Match InterruptWhen this bit is set, an internal interrupt (IRQ3) byCMI is enabled. When cleared, the interrupt is inhibited.Bit 7 CMF Counter Match FlagThis read only bit is set when a match occuts betweenthe up counter and the TCONR. Cleared by a softwarewrite (unable to write "I" by software).Each bit of the TCSR3 is cleared during reset._HITACHI 369

HD6303X,HD63A03X,HD63B03X------------------------• SERIAL COMMUNICATION INTERFACE (SCt)The HD6303X SCI contains two operation modes; one is anasynchronous mode by the NRZ format and the other is aclocked synchronous mode which transfer data synchronizingwith the serial clock.The serial interface is configured as follows:• Control/Status Register (TRCSR)• Rate/Mode Control Register (RMCR)• Receive Data Register (RDR)• Receive Data Shift Register (RDSR)• Transmit Data Register (TDR)• Transmit Data Shift Register (TDSR)The serial I/O hardware requires an initialization by softwarefor operation. The procedure is usually as follows:I) Write a desirable operation mode into each correspondingcontrol bit of the RMCR.2) Write a desirable operation mode into each correspondingcontrol bit of the TRCSR.When using bit 3 and 4 of port 2 for serial I/O only, there isno problem even if TE and RE bit are set. But when setting thebaud rate and operation mode, TE and RE should be "0". Whenclearing TE and RE bit and setting them again, more than I bitcycle of the current baud rate is necessary. If set in less than Ibit cycle, there may be a case that the internal transmit/receiveinitialization fails.• Asvnchronous ModeAn asynchronous mode contains the folloWing two dataformats:I Start Bit + 8Hit Data + I Stop BitI Start Bit + 9 Bit Data + I Stop BitIn addition, if the 9th bit is set to "I" when making 9bit data format, the format ofI Start bit + 8 Bit Data + 2 Stop Bitis also transferred.Data transmission is enabled by setting TE bit of the TRCSR,then port 2, bit 4 will become a serial output independently ofthe corresponding DDR. .For data transmit, both the RMCR and TRCSR shOUld beset under the desirable operating conditions. When TE bit isset during this process, 10 bit preamble will be sent in 8-bit dataformat and II bit in 9-bit data format. When the preamble isproduced, the !nternal synchronization will become stable andthe transmitter is ready to act.The conditions at this stage are as follows.1) If the TDR is empty (TDRE=I), consecutive I's areproduced to indicate the idle state.2) If the TDR contains data (TDRE=O), data is sent to thetransmit data shift register and data transmit starts.During data transmit, a start bit of "0" is transmitted first.Then 8-bit or 9-bit data (starts from bit 0) and a stop bit of "I"are transmitted .When the TDR is "empty", hardware sets TDRE flag bit. Ifthe CPU doesn't respond to the flag in proper timing (the TDREis in set condition till the next normal data transfer starts fromthe 'transmit data), "I" is transferred instead of the start bit "0"and continues to be transferred till data is provided to the dataregister. While the TDRE is "1", "0" is not transferred.Data receive is possible by setting RE bit. This makes port 2,bit 3 be a serial input. The operation mode of data receive isdecided by the contents of the TRCSR and RMCR. The first"0" (space) synchronizes the receive bit flow. Each bit of thefollowing data will be strobed in the middle. If a stop bit is not"1", a framing error assumed and ORFE is setWhen a framing error occurs, receive data is transferred tothe receive data register and the CPU can read error-generatingdata. This makes it possible to detect a line break.If the stop bit is .. 1", data is transferred to the receive dataregister and an interrupt flag RDRF is set. If RDRF is stillset when receiving the stop bit of the next data, ORFE is set toindicate overrun generation.When the CPU read the receive data register as a response toRDRF flag or ORFE flag after having read TRCS, RDRF orORFE is cleared.(Note) Clock Source in Asynchronous ModeWhen using an internal clock for serial I/O, the fonowingsshould be kept in mind.• Set CC 1 and CCO to "1" and "0" respectively.• A clock is generated regardless of the value of TE,RE.• Maximum clock rate is E+ 16.• Output clock rate is the same as bit rate.When using an external clock for serial I/O, the followingsshould be kept in mind.• Set CCI and CCO in the RMCR to "I" and "I" respectively.• The external clock frequency should be set 16 timesof the applied baud rate.• Maximum clock frequency is that of the systemclock.• Clocked Synchronous Mode .In the clocked synchronous mode, data transmit issynchronized with the clock pulse. The HD6303X SCIprovides functionally independent transmitter and receiverwhich makes fun duplex operation possible in the asynchronousmode. But in the clocked synchronous mode an SCI clock I/Opin is only P 22 , so the simultaneous receive and transmitoperation is not available. In this mode, TE and RE shouldnot be in set condition ("1") simultaneously. Fig. 21 gives asynchronous clock and a data format in the clocked synchronousmode.370 _HITACHI

------------------------HD6303X,HD63A03X,HD63B03XHD6303X Internal Data BusTransmit/Receive Control and Status RegisterTimerl FAC.Timer2Up CounterData transmit is realized by setting TE bit in the TRCSR.Port 2, bit 4 becomes an output unconditionally independentof the value of the corresponding DDR.Both the RMCR and TRCSR should be set in the desirableoperating condition for data transmit.When an external clock input is selected, data transmit isSynchronousclockFigure 20 Serial Communication Interface Block Diagram

HD6303X,HD63A03X,HD63B03X------------------------Transmit/Receive Control Status Register76543 10IRORF'ORFE'TORE' RIE 'RE 'TIE I TE I WU 1$0011Bit 0 WU Wake·upIn a typical multi-processor configuration, thesoftware protocol provides the destination address atthe first byte of the message. In order to make un·interested MPU ignore the remaining message, a wake-upfunction is available. By this, uninterested MPU can inhibitall further receive processing till the next messagestarts.Then wake-up function is triggered by consecutiveI's with I frame length (IO bits for 8·bit data, II for9-bit). The software. protocol should provide the idletime between messages.By setting this bit, the MPU stops data receive till thenext message. The receive of consecutive" I" with oneframe length wakes up and clears this bit and then theMPU restarts receive operation. However, the RE flagshould be already set before setting this bit. In theclocked synchronous mode WU is not available, so thisbit should not be set.Bit 1 TE Transmit EnableWhen this bit is set, transmit data will appear at port2. bit 4 after one frame preamble in asynchronous mode,while in clocked synchronous mode appear immediately.This is executed regardless of the value of the correspondingOOR. When TE is cleared, the serial I/Odoesn't affect port 2, bit 4.Bit 2 TIE Transmit Interrupt EnableWhen this bit is set, an internal interrupt (lRQ3) isenabled when TORE (bit 5) is set. When cleared, theinterrupt is inhibited.Bit 3 RE Receive EnableWhen set, a signal is input to the receiver from port2, bit 3 regardless of the value of the OOR. When REis cleared, the serial I/O doesn't affect port 2, bit 3.Bit 4 RIE Receive Interrupt EnableWhen this bit is set, an internal interrupt. IRQ3 isenabled when RDRF (bit 7) or ORFE (bit 6) is set.When cleared, the interrupt is inhibited.Bit 5 TORE Transmit Data Register EmptyTORE is set when the TOR is transferred to thetransmit data shift register in the asynchronous mode,while in clocked synchronous mode when the TOSR is"empty". This bit is reset by reading the TRCSR andwriting new transmit data to the transmit data register.TORE is set to "I" during reset.Bit 6 ORFE Overrun Framing ErrorORFE is set by hardware when an overrun or a framingerror is generated (during data receive only). Anoverrun error occurs when new receive data is ready tobe transferred to the ROR during RORF still being set.A framing error occurs when a stop bit is "0". But inclocked synchronous mode, this bit is not affected. Thisbit is cleared when reading the TRCSR, then the ROR,or during reset.Bit 7 RDRF Receive Data Register FullRORF is set when the RDSR is transferred to theRDR. Cleared when reading the TRCSR, then the RDR.or during reset.(Note) When a few bits are set between bit 5 to bit 7 in theTRCSR, a read of the TRCSR is sufficient for clearingthose bits. It is not necessary to read the TRCSR every·time to clear each bit.• Transmit Rate/Mode Control Register (RMCR)The RMCR controls the following serial I/O:• Baud Rate• Clock Source• Data Format• Port 2, Bit 2 FunctionIn addition, if 9·bit data format is set in the asynchronousmode, the 9th bit is put in this register. All bits are readable andwritable except bit 7 (read only). This register is set to $00during reset.Transfer Rate/Mode Control Register76543210cco I SSl I sso 1$0010I ROB I TDBI SS21 CC2' CCl IBitOBit 1Bit 5SSO}SSlSS2Speed SelectThese bits control the baud rate used for the SCI. Table6 lists the available baud rates. The timer I FRC (SS2=O) andthe timer 2 up counter (SS2=1) provide the internal clock to theSCI. When selecting the timer 2 as a baud rate source, it func·tions as a baud rate generator. The timer 2 generates the baudrate listed in Table 7 depending on the value of the TCONR.(Note) When operating the SCI with internal clock, do notperform write operation to the timer/counter which isthe clock source of the SCI.Bit 2Bit 3CCO}CCl Clock Control/Format Select*Bit 4 CC2These bits control the data format and the clock source(refer to Table 8).• CCO, CC I and CC2 are cleared during reset and the MPUgoes to the clocked synchronous mode of the externalclock operation. Then the MPU forces port 2, bit 2in the clock input state. When using port 2, bit 2 as anoutput port, the DDR of port 2 should be set to "I" andCCI and CCO to "0" and "I" respectively.372 ~HITACHI

------------------------HD6303X,HD63A03X,HD63B03XTable 6 SCI Bit Times and Transfer Rates(1) Asynchronous ModeXTAL 2.4576MHz 4.0MHz 4.9l52MHzSS2 SSl SSO E 6l4.4kHz 1.0MHz 1.22BBMHz0 0 0 E+16 26Jls/3B400Baud l6ps/62500Baud l3ps/76BOOBaud0 0 1 E+12B 20Bps/4BOOBaud l2BJls/7B12.5Baud 104.2 ps/9600Baud0 1 0 E+1024 1.67ms/600Baud 1.024ms/976.6Baud B33.3ps/1200Baud0 1 1 E+4096 6.67ms/150Baud 4.096ms/244.l Baud 3.333ms/300Baud1 - - -* * ** When SS2 is "1", Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N.Baud Ratef32 (N+l)(f: input clock frequency to the)timer 2 counterN = 0"'" 255(2) Clocked Synchronous Mode *XTAL 4.0MHz 6.0MHz 8.0MHzSS2 SS1 SSO E 1.0MHz 1.5MHz 2.0MHz0 0 0 E+2 2t/Sibit 1.33,us/bit 1ps/bit0 0 1 E+16 l6ps/bit 10.7ps/bit Bps/bit0 1 0 E+128 12Bps/bit B5.3,uSibit 64ps/bit0 1 1 E+512 512ps/bit 341 pslbit 256ps/bit1 - - -** ** *** Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock isopera table up to DC ..... 1/2 system clock.** The bit rate is shown as follows with the TCONR as N.Bit Rate (J.ls/bit) = 4 (~+ 1 )f: input clock frequency to the)timer 2 counter(N = 0"'" 255Table 7 Baud Rate and Time Constant Register Example~.~ XTALBaud~----......2.4576MHz 3.6B64MHz 4.0MHz 4.9152MHz110 21- 32- 35- 43-150 127 191 207 255300 63 95 103 127600 31 47 51 631200 15 23 25 312400 7 11 12 154800 3 5 79600 1 2 319200 0 13B400 0* E/8 clock is input to the timer 2 up counter and E clock otherwise.8.0MHz70-51-207103512512~HITACHI373

H06303X,H063A03X,H063B03X-----------------------Table aSCI Format and Clock Source ControlCC2 CC1 CCO Format Mode0 0 0 a-bit data Clocked Synchronous0 0 1 8-bitdata Asynchronou s0 1 0 a-bit data Asynchronous0 1 1 a-bit data Asynchronous1 0 0 a-bit data Clocked Synchronous1 0 1 9-bit data Asynchronous1 1 0 9-bit data Asynchronous1 1 1 9-bit data Asynchronous* Clock output regardless of the TRCSR, bit RE and TE.** Not used for the SCI.Clock SourceExternalInternalInternalExternalInternalInternalInternalExternalPort 2, Bit 2 Port 2, Bit 3 T Port 2, Bit 4InputNot Used**When the TRCSR, RE bit is "1",Output*bit 3 is used as a serial input.Input>OutputNot Used**Output*InputWhen the TRCSR, TE bit is "1",bit 4 is used as a serial output.Bit 6 TD8 Transmit Data Bit aWhen selecting 9-bit data format in the asynchronou'Smode, this bit is transmitted as the 9th data. Intransmitting 9-bit data, write the 9th data into this bitthen write data to the receive data register.Bit 7 RDa Receive Data Bit aWhen selecting 9-bit data format in the asynchronousmode, this bit stores the 9th bit data. In receiving 9-bitdata, read this bit then the receive data register.• TIMER, SCI STATUS FLAGTable 9 shows the set and reset conditions of each statusflag in the timer I , timer 2 and SCI.Table 9Timer 1, Timer 2 and SCI Status FlagSet ConditionReset ConditionICF FRC -4 ICR by edge input to P 20 • 1. Read the TCSR 1 or TCSR2 then ICRH,when ICF= 12. RES=OOCF1 OCR1=FRC 1. Read the TCSR1 or TCSR2 then write to theOC R 1 H or OC R 1 L, when OCF 1 = 12. J{£S=OTimer1 OCF2 OCR2=FRC 1. Read the TCSR2 then write to the OCR2H orOCR2L, when OCF2= 12. m=OTOF FRC=$FFFF+1 cycle 1. Read the TCSR1 then FRCH, when TOF=12. ifES=oTimer CMF T2CNT=TCONR 1. Write "0" to CM F , when CM F = 12 2. RES=oRDRF Receive Shift Register -4 RDR 1. Read the TRCSR then RDR, when RDRF= 12. R"ES=OORFE 1. Framing Error (Asynchronous Mode) 1. Read the TRCSR then RDR, when ORFE = 1Stop Bit = 02. Overrun Error (Asynchronous Mode)2. RES=OReceive Shift Register -4 RDR whenSCIRDRF=1TORE 1. Asynchronous Mode Read the TRCSR then write to the TOR,TOR -4 Transmit Shift Registerwhen TDRE=12. Clocked Synchronous ModeTransmit Shift Register is "empty"3. RES=O(Note) 1 .... ; transfer2. For example; "ICAH" means High byte of ICA.374 $ HITACHI

~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X• LOW POWER DISSIPATION MODEThe HD6303X provides two low power dissipation modes;sleep and standby.• Sleep ModeThe MPU goes t,o the sleep mode by SLP instruction execution.In the sleep mode, the CPU stops its operation, while theregisters' contents are retained. In this mode, the peripheralsexcept the CPU such as timers, SCI etc. continue their functions.The power dissipation of sleep-condition is one fifth thatof operating condition.The MPU returns from this mode by an interrupt, RES orSTBY; it goes to the reset state by RES and the standby modeby STBY. When the CPU acknowledges an interrupt request, itcancels the sleep mode, returns to the operation mode andbranches to the interrupt routine. When the CPU masks thisinterrupt, it cancels the sleep mode and executes the nextinstruction. However, for example if the timer 1 or 2 prohibitsa timer interrupt, the CPU doesn't cancel the sleep mode becauseof no interrupt request.This sleep mode is effective to reduce the power dissipationfor a system with no need of the HD6303X's consecutiveoperation.• Standby ModeThe HD6303X stops all the clocks and goes to the resetstate with STBY"Low". In this mode, the power dissipation isreduced conspicuously. All pins except for the power supply,the STBY and XT AL are detached from the MPU internallyand go to the high impedance state.In this mode the power is supplied to the HD6303X, sothe contents of RAM is retained. The MPU returns from thismode during reset. The followings are typical usage of thismode.Save the CPU information and SP contents on RAM by NMI.Then disable the RAME bit of the RAM control register and setthe STBY PWR bit to go to the standby mode. If the STBYPWR bit is still set at reset start, that indicates the power issupplied to the MPU and RAM contents are retained properly.So system can restore itself by returning their pre-standby informationsto the SP and the CPU. Fig. 22 depicts the timing ateach pin with this example.VeeHD6303X14)I puu...11111_----'H~ -----fl: III1~11111_---41r:-I ~:I I I~ ~Save registersOscillatorRAM/Port 5 ControlStart TimeRegister Set ~RestartFigure 22 Standby Mode Timing• TRAP FUNCTIONThe CPU generates an interrupt with the highest priority(TRAP) when fetching an undefined instruction or an instructionfrom non-memory space. The TRAP prevents the systemburstcaused by noise or a program error.• Op Code ErrorWhen fetching an undefined op code, the CPU saves CPUregisters as well as a normal interrupt and branches to the TRAP($FFEE. $FFEF). This provides the priority next to reset.• Address ErrorWhen an instruction fetch is made from internal register($0000-$001 F), the MPU generates an interrupt as well as anop code error. But on the system with no memory in its externalmemory area, this error processing is not applicable ifan instruction fetch is made from the external non-memoryarea.This processing is available only for an instruction fetch andis not applicable to the access of normal data read/write.(Note) The TRAP interrupt provides a retry function differentlyfrom other interrupts. This is a program flow returnto the address where the TRAP occurs when a sequencereturns to a main routine from the TRAP interruptroutine by RTI. The retry can prevent the system burstcaused by noise etc.However, if another TRAP occurs, the program repeatsthe TRAP interrupt forever, so the consideration isnecessary in programming.• INSTRUCTION SETThe HD6303X provides object code upward compatiblewith the HD6801 to utilize all instruction set of theHMCS6800. It also reduces the execution times of key instruc-~HITACHI 375

HD6303X,HD63A03X,HD63B03X-----------------------tions for throughput improvement.Bit manipulation instruction, change instruction of theindex register and accumulator and sleep instruction are alsoadded.The followings are explained here.CPU Programming Model (refer to Fig. 23)• Addressing Mode• Accumulator and Memory Manipulation Instruction(refer to Table 10)• New Instruction• Index Register and Stack Manipulation Instruction(refer to Table II)• Jump and Branch Instruction (refer to Table 12)• Condition Code Register Manipulation(refer to Table 13)• Op Code Map (refer to Table 14)• Programming ModelFig. 23 depicts the HD6303X programming model. Thedouble accumulator 0 consists of accumulator A and B, sowhen using the accumulator 0, the contents of A and Baredestroyed.f.----"- ___ o~g 8·8"Accu .. u ...... A .... 81, DOOr 16·8,1 OoubW Accumulator 01. 5 01Indr-Regl".IXI1. 5 SP 01SI.k Po,n'", ISP,1. 5 PC 01PrOW"" Coun .... IPCI7 0~' H I N Z V C Cond.t,onCode Ret,"" leCA,Carty/Borrow hom MS8-av-rtaowZ ...,.,.... v.In ••"uptH,,' c.r'v IF rom 81t 31Figure 23 CPU Programming Model• CPU Addressing ModeTIle HD6303X provides 7 addressing modes. The addressingmode is decided by an instruction type and code. Table 10through 14 show addressing modes of each instruction withthe execution times counted by the machine cycle.When the clock frequency is 4 MHz, the machine cycle timebecomes microseconds directly.Accumulator (ACCX) AddressingOnly an accumulator is addressed and the accumulator A orB is selected. This is a one-byte instruction.Immediate AddressingThis addressing locates a data in the second byte of aninstruction. However, LOS and LOX locate a data in the secondand third byte exceptionally. This addressing is a 2 or 3-byteinstruction.Direct AddressingIn this addressing mode, the second byte of an instructionshows the address where a data is stored. 256 bytes (SOthrough $255) can be addressed directly. Execution timescan be reduced by storing data in this area so it is recommendedto make it RAM for users' data area in configurating a system.This is a 2-byte instruction, while 3 byte with regard to AIM,OIM, ElM and TIM.Extended AddressingIn this mode, the second byte shows the upper 8 bit of thedata stored address and the third byte the lower 8 bit. Thisindicates the absolute address of 3 byte instruction in thememory.Indexed AddressingThe second byte of an instruction and the lower 8 bit of theindex register are added in this mode. As for AIM, OIM, ElMand TIM, the third byte of an instruction and the lower 8 bitsof the index register are added.This carry is added to the upper 8 bit of the index registerand the result is used for addressing the memory. The modifiedaddress is retained in the temporary address register, so the contentsof the index register doesn't change. This is a 2-byteinstruction except AIM, OIM, ElM and TIM (3-byte instruction).Implied AddressingAn instruction itself specifies the address. That is, theinstruction addresses a stack pointer, index register etc. This is aone-byte instruction.Relative AddressingThe second byte of an instruction and the lower 8 bits ofthe program counter are added. The carry or borrow is added tothe upper 8 bit. So addressing from -126 to + 129 byte of thecurrent instruction is enabled. This is a 2-byte instruction.(Note) CLI, SEI Instructions and Interrupt OperationWhen accepting the IRQ at a preset timing with the helpof CLI and SEI instructions, more than 2 cycles arenecessary between the CLI and SEI instructions. Forexample, the following program (a) (b) don't accept theIRQ but (c) accepts it.CLISEI(a)CLINOPSEI(b)CLINOPNOPSEIThe same thing can be said to the TAP instructioninstead of the CLI and SEI instructions.(c)376 _HITACHI

Table 10 Accumulator, Memory Manipulation InstructionsCondition CodeAddressing ModesRegisterOperations Mnemonic Boolean/- IMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Operation5 4 3 2 1 0OP - - # OP # OP - - - # OP # OP # H I N Z V CAdd ADDA 18B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M~ A I I I 1 1ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M~B 1 1 t t tAdd Double ADDD C3 3 3 03 4 2 E3 5 2 F3 5 3· A:B+M:M+l~A:B t t t tAdd Accumulators ABA lB 1 1 A + B~ A t t t t tAdd With Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C~A t : 1 t tAD~~_ C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C~B t t t t tAND2 94 3 2 A4 2 B4 4 3 A'M~A~-- ~~~~ --- -_._-i r t t R ANDB C4 2 D4 3 2 E4 4 2 F4 4 3 B'M~B----t 1 R Bit Test BIT A 85 2 3 2 A5 4 2 B5 4 3 A·M~5 .. 1 t R BIT B C5 2 2 05 3 2 E5 4 2 F5 4 3 B·M 1 1 RClear CLR 6F 5 2 7F 5 3 00- M R S R · R~_A 4F 1 1 00- A R S R RCLRB 5F 1 1 00 - B R S R RCompare CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3 A-M 1 1 I ICMPB Cl '2 2 01 3 2 El 4 2 Fl 4 3 B-M t 1 1 ICompareCBA 11 1 1 A-BAccumulatorst t 1 1Complement,l's COM 63 6 2 73 6 3 M-M t t R SCOMA 43 1 1 A ~A t 1 R SCOMB 53 1 1 B -B t 1 R SComplement, 2's NEG 60 6 2 70 6 3 OO-M-M 1 1 (I) '2)INeptel NEGA 40 1 1 OO-A-A t 1 ,'I; '2;NEG8 50 1 1 OO-B-B t t (1') (2)-- --Converts binary add of BCDDecimal Adjust, A DAA19 2 11Icharacters into BCD format 1 t (3)-------Decrement DEC SA 6 2 7A 6 3 M-l -M t 1 (.)DECA 4A 1 1 A-I - A 1 1 (.) .DECB 5A 1 1 B-1 - B 1 1 lot) •Exclusive OR EORA 88 2 2 98 3 2 AS 4 2 B8 4 3 A@M-A t 1 R EORB CB 2 2 08 3 2 E8 4 2 F8 4 3 B@M- B ·t t R Increl'/)8nt INC 6C 6 2 7C 6 3 M+l-M 1 1 .~)INCA 4C 1. 1 A + 1 - A 1 1 @.INCB 5C 1 1 B + 1- B t I (5, •Load LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-A 1 I RAccumulatorLDAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M~B I t RLoad DoubleLDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1 - B. M~ A t AccumulatorI R Multiply Unsigned MUL 3D 7 1 ·· A.B~A:B • iltOR, Inclusive ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+M- A I t RORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B +M- B 1 t RPush Data PSHA 36 · ·4 1 A - Msp, SP - 1 ~ SPPSHB 37 4 1 B - M,p, SP - 1 ~ SP·PULB 33 3 1 SP + 1 - SP, Msp ~ B · I · I (6.' ··tROLA 49 1 1 :)~IIIIII liJ · I t ~8; 1B C b7 bOROL8 59 1 1·Pull Data PULA 32 3 1 SP + 1 - SP, Msp ~ A·Rotate Left ROL 69 6 2 79 6 3Rotate Right ROR 66 6 2 76 6 3·RORA 46 1 1·RORB 56 1 1·(Note) Condition Code Register will be explained in Note of Table 13.:) 4J.! I I I I I I I f;lB C b7 bOt 1 ((I It 1 (OJ tI t '$, t· t t '6 t(continued)¢!)HITACHI 377

HD6303X,HD63A03X,HD63B03X-----------------------Table 10 Accumulator, Memory Manipulation InstructionsOperationsMnemonicAddressing ModesIMMED. DIRECT INDEX EXTEND IMPLIEDBooleanlArithmetic OperationCondition CodeRegister5 4 3 2 1 0OP - # op - # OP - # OP - # op - # H I N Z V CShift Left ASL 68 6 2 78 6 3M} _ • S S f)tArithmeticASLA 48 1 1 A ~ I I I I I I I 1+ 0 e S S

------------------------HD6303X,HD63A03X,HD63B03XTable 11Index Register, Stack Manipulation InstructionsPointer Op.rltionsMnemonicAddressing ModesBool •• nlCondition Cod.Regist.rIMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Oper.tion 5 .. 3 2 1 0OP - .. OP - .. OP- .. OP- .. OP - .. H I N Z V CComplre Inde" Reg CPX 8C 3 3 9C 4 2 AC 5 2 BC 5 3 X-M:M+l • • : l : lD.cr.ment Index Reg DEX 09 1 1 X-l- X• l •Decrement Stick Pntr DES 34 1 1 SP - 1- SP • • --- _._---Increment Inde,,-~ INX 08 1 1 X + 1- X • • l Increment Stick Pntr INS 31 1 1 SP+l-SPload Index Reg r-u>x CE 3 3 DE 4 2 EE 5 2 FE 5 3 M - XH. 1M + 11- XL_ ···· • ct l R LOid Stack Pntr LOS 8E 3 3 9E 4 2 2 BE 5 3 lSlore I ndex Reg STX OF 4 2 EF 5 2 FF 5 3 XH - M. XL - 1M + 11 • 17 l RSlore Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH - M.SPL - IM+lI t l R Inriex Reg - Stack Pntr TXS 35 1 1 X-l-SP St.ck Pntr - Index Reg TSX 30 1 1 SP+l-XAdd A8X 3A 1 1 B + X- X Push Data PSHX 3C 5 1 XL - M..,. SP - 1 - SPXH- M IP • SP - 1 - SPPull Oala PULX 38 4 1 SP + 1 - SP. MIP - XHSP + 1- SP.M..,- XL ······-----_._---- --- - - -- --- Ae5 M- SP H. IM+ll-SP L • ',1) R-------r------~Exchange XGDX 18 2 1 ACCD· ·IX• • • • • •(Note) Condition Code Register will be explained in Note of Table 13.OperationsMnemonicTable 12 Jump, Branch InstructionsAddressing ModesCondition CodeRegister- ~--r--- - ----Branch TestRELATIVE DIRECT INDEX EXTEND IMPLIED 5 4 3 2 1 0H I N Z V CBranch Always BRA 20 3 2 NoneBranch Never BRN 21 3 2 None Branch If Carry Clear BCC 24 3 2 c=o Branch If Carry Set BCS 25 3 2 C = 1 Branch If = Zero BEC 27 3 2 Z = 1 Branch If > Zero BGE 2C 3 2 N ct> V = 0 Branch If Higher BHI 22 3 2 C+Z=OBranch If .; Zero BlE 2F 3 2 I Z + (N ct> VI = 1 Branch If lower OrBlS 23 3 2 I IC+Z=1SameI+Branch If < Zero BLT 20 3 2N@V=1-Branch If Minus BMI 2B 3 2-N~l----------Branch If Not Equal--· BNEZero26 3 2 Z=O Branch If OverflOWClearBVC 28 3 2 V=OI · Branch If Overflow Sat BVS 29 3 2 V = 1 ... ... •Branch If Plus BPl 2A 3 2 N=OBranch To Subroutine BSR 80 5 2 Jump JMP 6E 3 2 7E 3 3 •Jump To Subroutine JSR 90 5 2 AD 5 2 BO 6 3 No Operation NOP 01 1 1Advances Prog. Cn~r.Only······Raturn From Interrupti RTI 3B 10 1 --ct --Return FromRTS 39 5 1Subroutine· Software Interrupt SWI 3F 12 1 SWlit for Interrupt· WAI 3E 9 1· · 1) •···OP - .. OP- .. OP - .. OP - # OP -#---"---Branch If > Zero BGT 2E 3 2 Z + IN ct> VI = 0·Sleep SLP lA 4 1• • • • • •(Note) • WAI puts R/Vil high; Address Bus goes to FFFF; Data Bus goes to the three state.Condition Code Register will be explained in Note of Table 13.-~HITACHI 379

HD6303X,HD63A03X,HD63B03X------------------------Table 13 Condition Code Register Manipulation InstructionsjAddreHinllModelCondition Code RegisterOperations Mnemonic IMPLIED Boolean Operation 5 4 3 2 1 0OP - # H I N Z V CClaar Intarrupt Mask Cli OE 1 1 0-1 RCleerOverfiow ClV OA 1 1 O-V a · R Set Carry SEC 00 1 1 l-e a SSet Interrupt Mask SEI OF 1 1 I-I S aSet Overflow SEV OB 1 1 I-V S · · · ·Accumulator A - CCR TAP 06 1 1 A- CCR ---@---CCR ... Accumulator ATPA07 1 1CCR-A·CI_Carry ClC OC 1 1 O ... C· · · · ·RLEGENDOP Operation Code (Hexadecimal INumber of MCU CyclesMsp Contents of memory location pointed to by Stack Pointer# Number of Program Bytes+ Arithmetic PlusArithmetic Minus• Boolean AND+ Boolean Inclusive ORe Boolean Exclusive ORM Complement of M~ Transfer intoOBit = Zero00 Byte = Zero(Notel Condition Code Register Notes: (Bit set if test is true and cleared otherwise)It) (Bit V) Test: Result = 1oo000oo?(21 (Bit C) Test: Result \ 00000000?·CONDITION CODE SYMBOLSH Half-carry from bit 3 to bit 4I Interrupt maskN Negative (sign bitlZ Zero (by telV Overflow, 2's complementC Carry/Borrow from/to bit 7R Reset AlwaysS Set Alwayst Set if true after test or clear• Not Affected·· · ·(3) (Bit C) Test: BCD Character of high-order byte greater than 10? (Not cleared if previously sed(4) (Bit VI Test: Operand = 10000000 prior to execution?~ (Bit VI Test: Operand = 01111111 prior to execution?.'6'. (Bit V) Test: Set equal to N~ C = 1 after the execution of instructions~7) (Bit NI Test: Result less than zero? (Bit 15=11(8) (All Bit) Load Condition Code Register from Stack.(9; (Bit II Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait state.(10) (All Bitl Set according to the contents of Accumulator A.(Ii) (Bit C) Result of Multiplication Bit 7=1? (ACCB)Table 14 OP-Code MapOP ACC ACC Eo/ ACCA or SP ACCB or XCODE A BIND '/DIR' IMM I DIR liND I EXT IMM I DIR T IND I EXT""--LOHII __ ~O __ 0001 0010 0011 0100 0101_~2~1-0~!.!.. ~_~~2~1011 1100j 1101_1 !11~Lll11LO ~ --,-- f---;- -3--4 r---5-- 6 7! 8 I 9 I A I B C I 0 -TE-~-0000 ° ~ SBA BRA TSX NEG SUB °~~~~~N-O-P~~CB-A--~BR-N--~I-N-S--~ _______----~~r---A~I-M----~----------------~C~M~P~-----------------f-I000'001000110100 LSRD ~ BCC DES LSR AND 4j..:...'---+-'---4_A_SLD 0101 ~ BCS TXS ___ ~'.~ _____ f---- ______________. _______ B_I_T _____________ .__._________ ~TAP TAB BNE .i>SHA-- ROR LOA 6--I---+-::T=-P-,--A-+-=T-::"BA--+--B--Eac:---+--p-,-SH-B::--+-----·-----A-=S-R:c--- ---=_=- k2:L~-==~~~,,=_~-=~==_~--STA -=-~-J-~1'001111000 INX XGDX BVe PULX ASL EOR 8~~~·+--D-EX-+--D-A-A-+-BV-S--I---R-T-S-+-----------R-O-L----- .--.------------ ADC. -----------~1001·~:..;+-'-+-=C-:-:LV--+-=-SL:-:P:--+-=-BP:c:L-~A-,-B-=X--~------D'-E--:C:--------·---+-1010 A. ORA ----------- .. ~~~I---+--S-=-EV--+--A-BA--+-BM-' ---+-RT-'--+----____ -----==-r----cT-'-M-- --+-------------A--D=-D::c--------------'a1011 B~-=--=---i~+c:C_=_LC::__¥~______:::;r\__=_BG-E--_I__cPS-H-X+--1100 C___':-:N-=C_____._-t---::c:::-T__C_PX---:-:c-=--_. ___-t___ ~,____---L-D-D--==----- ~_S:~ ______ ~~f ~,---~C-,----I'~""----:;~B-LT-=-+M"C-U-L-+-----=-...---=TS..--T---.--- ~_U __ ~~ ___ ~- _____~ BGT WAf ~ ~~~ ___ Etf-~D-S_----I~-----~-e-!-1111 F SEI ~ BLE SWI CLR STS ~ STX FL-~-1--0--~-~--2-1--3--~--4-.-5-..--6--r,---7--- 8 9 I A I B C I 0 I ElF·UNDEF'NED OP CODE ~• Only each instructions of AIM, OIM, ElM, TIM380~HITACHI

------------------------HD6303X,HD63A03X,HD63B03X• CPU OPERATION• CPU Instruction FlowWhen operating, the CPU fetches an instruction from amemory and executes the required function. This sequencestarts with RES cancel and repeats itself limitlessly if notaffected by a special instruction or a control Signal. SWI, RTI,WAI and SLP instructions are to change this operation, whileNMI, IRQ1, IRQ1, IRQ3, HALT and STBYare to control it.Fig. 24 gives the CPU mode transition and Fig. 25 the CPUsystem flow chart. Table IS shows CPU operating states andport states.• Operation at Each Instruction CycleTable 16 provides the operation at each instruction cycle.By the pipeline control of the HD6303X, MULT, PUL, DAAand XGDX instructions etc. prefetch the next instruction. Soattention is necessary to the counting of the instruction cyciesbecause it is different from the existent one ·····op code fetchto the next instruction opcode.Table 15 CPU Operation State and Port StatePort Reset STBY*** HALTAo -A7 H T TPort 2 T T KeepDo - D7 T T TAs -- AI5 H T TPort 5 T I T T---Port 6 T T Keep-- -ControlSignal* TI **H ; High, L; Low, T; High Impedance• RD, WR, R/iii, OR = H, SA = L•• RD, WR, R/Iii = T, LlR, SA = H*. * E pin goes to high impedance state.SleepHKeepTHTKeep*Figure 24 CPU Operation Mode Transition_HITACHI381

wcoI')INotel 1. The program sequence will come to the RES start fromany place of the flow during RES. When STBY=O, thesequence will go into the standby mode regardless of the CPUcondition.2. Refer to "FUNCTIONAL PIN DESCRIPTION" for moredetails of interrupts.J:Cen~wX":t:cen~owX":t:cenwaJoWX-%~()%-Figure 25 HD6303X System Flow Chart

------------------------HD6303X,HD63A03X,HD63B03XTable 16 Cycle-by-Cycle OperationAddress Mode 81InstructionsAddress BusData BusIMMEDIATEADC ADDAND BITCMP EORLOA ORASBC SUBAD DO CPXLDD LOSLOX SUBD21213 23Op Code Address + 1 1 0Op Code Address + 2 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0Op Code Address+3 1 01 1 Operand Data1 0 Next Op Code1 1 Operand Data (MSB)1 1 Operand Data (LSB)1 0 Next Op CodeDIRECTADCANDCMPLOASBCSTAADDDLDDLOXSTDSTXJSRTIMAIMOIMADDBITEORORASUBCPXLOSSUBDSTSElM123 313 231243412434125 345---,-46234123456Op Code Address + 1 1 0Address of Operand 1 0Op Code Address+ 2 1 0Op Code Address + 1 1 0Destination Address 0 1Op Code Address + 2 1 0Op Code Address + 1 1 0Address of Operand 1 0Address of Operand + 1 1 0Op Code Address + 2 1 0Op Code Address + 1 1 0Destination Address 0 1Destination Address + 1 0 1Op Code Address + 2 1 0Op Code Address + 1 1 0FFFF 1 1Stack Pointer 0 1Stack Pointer - 1 0 1Jump Address 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0Address of Operand 1 0Op Code Address + 3 1 0Op Code Address + 1 1 0Op Code Address + 2 1 0Address of Operand 1 0FFFF 1 1Address of Operand 0 1Op Code Address + 3 1 01 1 Address of Operand (LSB)1 1 Operand Data1 0 Next Op Code1 1 Destination Address0 1 Accumulator Data1 0 Next Op Code1 1 Address of Operand (LSB)1 1 Operand Data (MSB)1 1 Operand Data (LSB)1 0 Next Op Code1 1 Destination Address (LSB)0 1 Register Data (MSB)0 1 Register Data (LSB)1 0 Next Op Code1 1 Jump Address (LSB)1 1 Restart Address (LSB)0 1 Return Address (LSB)0 1 Return Address (MSB)1 0 First Subroutine Op Code1 1 Immediate Data1 1 Address of Operand (LSB)1 1 Operand Data1 0 Next Op Code1 1 Immediate Data1 1 Address of Operand (LSB)1 1 Operand Data1 1 Restart Address (LSB)0 1 New Operand Data1 0 Next Op Code(Continued)_HITACHI383

Address Mode &InstructionsINDEXEDJMPADDDCPXlOSSUBDSTDSTXJSRASLCOMINCNEGRORTIMCLRAIMOIMLDDLOXSTSASRDECLSRROLElM1 Op Code Address + 1 13 2 FFFF 13 Jump Address 1- 1---------,-- --Op Code Address + 1 12 FFFF 13 IX + Offset 144 Op Code Address+2 1----45556557Address Bus-r-- ap- Code-"ddress-H -- ---- -ADC------.--ADDAND BITCMP EORLOA ORASBC SUBTSTlilA----T-2 FFFF 13 IX + Offset 04 Op Code Address+2 11 Op Code Address + 1 12 FFFF 13 IX + Offset 14 IX+Offset+ 1 15 Op Code Address + 2 11 Op Code Address + 1 12 FFFF 13 IX + Offset 04 IX+Offset+1 05 Op Code Address + 2 11 Op Code Address+ 1 12 FFFF 13 Stack Pointer 04 Stack Pointer - 1 05 IX + Offset 11 Op Code Address+ 1 12 FFFF 13 IX + Offset 14 FFFF 15 IX + Offset 06 Op Code Address + 1 11 Op Code Address + 1 12 Op Code Address + 2 13 FFFF 14 IX + Offset 15 Op Code Address + 3 11 Op Code Address + 1 12 FFFF 13 IX + Offset 14 IX + Offset 05 Op Code Address + 2 11 Op Code Address+ 1 12 Op Code Address + 2 13 FFFF 14 IX + Offset 15 FFFF 16 IX + Offset 07 Op Code Address + 3 1Data Bus0 1 1 Offset1 1 1 Restart Address (LSB)0 1 0 First Op Codeo!~ump~t~_0 1 1 Offset1 1 1 Restart Address (LSB)0 1 1 Operand Data0 1 0 Next Op CodeO 1 1-Offset----------------1 1 1 Restart Address (LSB)1 0 1 Accumulator Data0 1 0 Next Op Codeu 1 1 Offset- -~----1 1 1 Restart Address (LSB)0 1 1 Operand Data (MSB)0 1 1 Operand Data (LSB)0 1 0 Next Op Codeu 1 1 Offset1 1 1 Restart Address (LSB)1 0 1 Register Data (MSB)1 0 1 Register Data (LSB)0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (LSB)1 0 1 Return Address (LSB)1 0 1 Return Address (MSB)0 1 0 First Subroutine Op Code0 1 1 Offset1 1 1 Restart Address (LSB)0 1 1 Operand Data1 1 1 Restart Address (LSB)1 0 1 New Operand Data0 1 0 Next Op Code0 1 1 Immediate Data0 1 1 Offset1 1 1 Restart Address (LSB)0 1 1 Operand Data0 1 0 Next Op Code0 1 1 Offset1 1 1 Restart Address (LSB)0 1 1 Operand Data1 0 1 000 1 0 Next Op Code0 1 1 Immediate Data0 1 1 Offset1 1 1 Restart Address (LSB)0 1 1 Operand Data1 1 1 Restart Address (LSB)1 0 1 New Opera!l'f'Data0 1 0 Next OP Code(Continued)384$ HITACHI

------------------------HD6303X,HD63A03X,HD63B03XAddress Mode 8&Instructionsi CyclesCycle:I IAddress BusData BusEXTENDJMP Op Code Address + 1 ! 1 I 0 1 1 Jump Address (MSB)3 ! ! Op Code Address+2 I 1 0 1 1 Jump Address (LSB)!3- "DC'ADD -tsf f12434ANDCMPLOASBC-5TA"ADDDCPXLOSSUBDsrbSTX-ASeCOMINCNEGROR- CLR"BITEORORASUBLDDLOXstsj~~mgo~t:~~ess+j-- +-H~g- ~~- -~ -- --~~-~+e~~-;r~:erand (MSB) -! Op Code Address + 2 ,1 I 0 1 1 Address of Operand (LSB)Address of Operand ! 1 i 0 1 1 Operand DataOp Code Address+3 ! 1 ! 0 1 0 Next Op Codej- L j '--Op'COdeAddreSs+'-- -+ '-j~~I: 0 - '-1-'- Destmation-AddressIMSB)-42 Op Code Addless+2 1. 0 1 1 Destination Address (LSB)3 Destination Address I 0 : 1 0 1 Accumulator Data4 ; Op Code Address + 3 , -1 1 I 0 1 0 Next Op Codet 1 +- Oi)-'COdeAddress+T '~ T - -1------0- -, ----,- -Addrljss~ofOpe':an(nMSB)2 I Op Code Address+2 1: 0 1 1 Address of Operand (lSB)5 3 Address of Operand 1 (j) 1 1 Operand Dafa (MSB)4 Address of Operand + 1 1 0 1 1 Operand Data (LSB)5 ! Op Code Address + 3 1 0 1 0 Next Op Code'~ 1 I--OpCodeAddress+f -,- ~, -0- ,-r--,---- DestmatlOn Address(MSB)2 Op Code Address + 2 1 0 1 1 Destination Address (LSB)5 3 Destination Address 0 1 0 1 Register Data (MSB)4 : Destination Address + 1 0 1 0 1 Register Data (LSB)~ ,-~- -~-r+ ~~~i)~td~~~:-(MSB) --- -+ -~~--~-~ ~~ -g~i-~~~~::: ~ ,+--; 2 i Op Code Address+2 1: 0 1 1 Jump Address (LSB)i 3 FFFF 1 1 1 1 Restart Address (LSB)6 4 Stack Pointer 0 1 0 1 Return Address (LSB)iI 5 ,Stack Pointer-1 0 1 0 1 Return Address (MSB)-ASR ---'ț-- ,-+-{--~-~mgo~~A~~esS+T - --,--1--+-t+ -+-- -~- -~r.:r::~:C;u~~ra~d ~Md;BfDEC I 2 'I' Op Code Address + 2 ! 1 0 1 1 Address of Operand (LSB)LSR i 6 i 3 I Address of Operand 1 0 1 1 Operand DataROL i 45 I AFFdFdFress of Operand 1o I 110 1Restart Address (LSB)New Operand Data6 Op Code Address+3 1 0 1 0 Next Op Code+- 1 +-Op CodeAddress+ j 1 :-O-~ -1- r----,- Add'ress of Operand (M'SB)2 Op Code Address+2 1 0 1 1 Address of Operand (LSB)5 3 I Address of Operand 1 0 1 1 Operand Data4 Address of Operand 0 1 0 1 00I 5 Op Code Address + 3 1 0 1 0 Next Op Code(Continued)_HITACHI 385

HD6303X,HD63A03X,HD63B03X-----------------------Address Mode S.InstructionsAddress BusData BusIMPLIEDABA ABX 1 Op Code Address + 1 1 0 1 0 Next Op CodeASL ASLDASR CBACLC CLICLR CLVCOM DECDES DEXINC INSINX LSR 1LSRD R(l)LROR NOPSBA SECSEI SEVTAB TAPTBA TPATST TSXTXSDAA XGDX1 Op Code Address + 1 1 0 1 0 Next-Op--Code-----------22 FFFF 1 1 1 1 Restart Address_(L_~~!. ___PULA PULB 1 Op Code Address + 1 1 0 1 0 Next Op Code3 2 FFFF 1 1 1 1 Restart Address (LSB)3 Stack Pointer + 1 1 0 1 1 Data from StackPSHA PSHB 1 Op Code Address + 1 1 0 1 1 Next Op Code-42 FFFF 1 1 1 1 Restart Address (lSB)3 Stack Pointer 0 1 0 1 Accumulator Data4 Op Code Address + 1 1 0 1 0 Next Op CodePULX 1 Op Code Address 1 + 1 0 1 0 Next Op Code4Restart Address (LSB)Data from Stack (MSB)23FFFFStack Pointer + 1111011114 Stack Pointer + 2 1 0 1 1PSHX 1 Op Code Address + 1 1 0 1 1Data from Stack (LSBI-Next Op cOdi!------2 FFFF 1 1 1 1 Restart Address (LSBI5 3 Stack Pointer 0 1 0 1 Index Register (LSBI4 Stack Pointer - 1 0 1 0 1 Index Register (MSBI5 Op Code Address + 1 1 0 1 0 Next Op CodeRTS 1 Op Code Address + 1 1 0 1 1 Next Op Code2 FFFF 1 1 1 1 Restart Address (LSBI5 3 Stack Pointer + 1 1 0 1 1 Return Address (MSBI4 Stack Pointer + 2 1 0 1 1 Return Address (LSBI5 Return Address 1 0 1 0 First Op Code of Return RoutineMUL 1 Op Code Address + 1 1 0 1 0 Nexd)pCOde---- - .- - --2 FFFF 1 1 1 1 Restart Address (LSBI3 FFFF 1 1 1 1 Restart Address (LSBI7 4 FFFF 1 1 1 1 Restart Address (LSB)5 FFFF 1 1 1 1 Restart Address (lSBI6 FFFF 1 1 1 1 Restart Address (LSBI7 FFFF 1 1 1 1 Restart Address (LSBI(Continued)386 $ HITACHI

II 7Vector0FFPFFcOde~Adi:tress+T--~------------------------HD6303X,HD63A03X,HD63B03XAddress Mode 8tInstructionsAddress BusData BusIMPLIEDWAII1 ! Op Code Address + 1 1 0 1 1 Next Op Codei, 2 I FFFF 1 1 1 1 Restart Address (LSB)3 [' Stack Pointer 0 1 0 1 Return Address (LSB)I I 4 Star.k Pointer-1 0 1 0 1 Return Address (MSB)9 I 5 'Stack Pointer - 2 0 1 0 1 Index Register (LSB)i 6 ,Stack Pointer-3 0 1 0 1 Index Register (MSB)I! Stack Pointer-4 0 1 0 1 Accumulator Ar8 i Stack Pointer - 5 0 1 0 1 Accumulator BI9 I Stack Pointer - 6 0 1 0 1 Conditional Code Register.. ~ --~ .·-~·21i,I 1-. 11 0 1 1 Next Op Code .1 1 1 Restart Address (LSB)3 I Stack Pointer + 1 1 0 1 1 Conditional Code RegisterII 4 Stack Pointer + 2 1 0 1 1 Accumulator B10 5 Stack Pointer +3 1 0 1 1 Accumulator A, 6 Stack Pointer+4 1 0 1 1 Index Register (MSB)tII7 I Stack Pointer + 5 1 0 1 1 I Index Register (LSB)8 I Stack Pointer+6 1 0 1 1 Return Address (MSB)9 ,Stack Pointer + 7 1 0 1 1 Return Address (LSB)• n --~-- + f-~~-!r-;-10 I Return Address! Op Code Address11001101First Op Code of Return RoutineNext Op Code·---~--=S,.,-L"'P------+---"11---::1 -+-: O ::- P! 2 I FFFF 1 1 1 1 Restart Address (LSB)i 3 ! Stack Pointer 0 1 0 1 Return Address (LSB)I i 4 ,Stack Pointer-1 0 1 0 1 Return Address (MSB), 5 I Stack Pointer - 2 0 1 0 1! Index Register (LSB)! 6 ! Stack Pointer-3 0 1 0 1 Index Register (MSB)12 i 7 i Stack Pointer-4 0 1 0 1 I Accumulator A! 8 i Stack Pointer-5 0 1 0 1 II Accumulator B49 i Stack Pointer -6 0 1 0 1 Conditional Code Register" 10 I Address FFFA 1 0 1 1 ~' Address of SWI Routine (MSB)11 I Vector Address FFFB 1 0 1 1 . Addre .. ss of SWI RO .. u.t.ine.(L.SB)I 12 Address of SWI Routine 1 0 1 0 First Op Code of SWI Routine-=C-od-:"e--:-A-:"dd-:"r-e-ss-+:-1=----+--,1:--+--0"---+-~1-+--'1;-- -Next Op Code- - .~- - -----2 FFFF 1 1 1 1 I Restart Address (LSB)) 1 I 1 11Sleep 1 II13 FFFF 1 1 1 01 i Restart Address (LSB)4 Op Code Address + 1 1 0 1 Next Op CodeRELATIVEBCC BCS 1 Op Code Address + 1 1 0 1 1 Branch OffsetBEQ BGE 3 2 FFFF 1 1 1 1 Restart Address (LSB)BGT BHIr Branch Address'· .... Test=·l"First Op Code of Branch Routine31 0 1BLE0BLS lop Code Address+l .. ·Test=·O" Next Op CodeBLT BMTBNE BPLBRA BRNBVC BVSBSR 1 Op Code Address + 1 1 0 1 1 Offset2 FFFF 1 1 1 1 Restart Address (LSB)I5 3 Stack Pointer 0 1 0 1 Return Address (LSB)4 Stack Pointer - 1 0 1 0 1 Return Address (MSB)5 Branch Address 1 0 1 0 First Op Code of SubroutineI.,.HITACHI 387

HD6303Y ,HD63A03Y ,HD63B03YCMOS MPU (Micro Processing Unit)The HD6303Y is a CMOS 8·bit micro processing unit whichcontains a CPU compatible with the HD6301Vl, 256 bytes ofRAM, 24 parallel I/O Pins, Serial Communication Interface(SCI) and two timers.-ADVANCE INFORMATION-HD6303YP, H D63A03YP,HD63B03YP• FEATURES• Instruction Set Compatible with the HD6301 Family• Abundant On·chip Resources• 256 Bytes of RAM• 24 Parallel I/O Pins• Handshake Interface (Port 6)• Darlington Transistor Direct Drive (Port 2, 6)• l6·bit Programmable Timer1 Input Capture Register1 Free Running Counter(2 Output Compare Registers• 8·Bit Reloadable Timer1 8·bit Up Counter( 1 Time Constant Register• Serial Communication InterfaceAsynchronous Mode8 Transmit Formats(Hardware ParityClocked Synchronous Mode• Interrupt - 3 External, 7 Internal• CPU Functions• Memory Ready, Auto Memory Ready• Halt• Error Detection(Address Trap, Op·code Trap)• Up to 65k Bytes Address Space• Low Power Dissipation Mode• Sleep• Standby (Hardware Set, Software Set)• Wide Range of OperationVee=3t06V (f=O.l to 0.5 MHz)f = 0.1 to 1.0 MHz; HD6303Y )Vee = 5V ± 10% f = 0.1 to 1.5 MHz; HD63A03Y(f = 0.1 to 2.0 MHz; HD63B03Y• Minimum Instruction Cycle Time: 0.5 tJs (f = 2.0 MHz)HD6303YF, HD63A03YF,HD63B03YF(DP-64S)(FP-64)388 $ HITACHI

• PIN ARRANGEMENT•HD6303YP, HD63A03YP, HD63B03YP•H o 6303Y, HD63A03Y, H o 63B03YHD6303YF, HD63A03YF, HD63B03YFVSS-'c(0 -'~ c(XTAl AD I~ III> Ii:4. ~EXTAlWR1 R/WemSTBY 0.BAI~:: I~ I~ r5Iii :t ~ ~ ~ )( w a:c(II>NMi0, 0,0, Pu OJp ..Pez 7OJ Pn O.D. O.Os Pl. 0.D.51 D.A.A.A,Pl. D.p.~ A.p., A,7 A, P'l AJA. P" A.P •• A.p ..P •• A.P 5 ,A. P60 "'-A,.P61 A.P'3 Bp •• A .. uPIS A .. 4. 4. 4. 4. 4. 4. ~ c( « .c .( .( .(P .. 31P'J 32AISVee0.O.A."'-Vss(Top View)(Top View)_HITACHI 389

HD6303Y,HD63A03Y,HD63B03Y'-----------------------• BLOCK DIAGRAMP 10 (Tin)Pl. (Tout.)Pn(SCLK)P 13 (Rx)P'4(Tx)P 15 (Tout,)P l , (Tout])P z7 (TCLK)VCC---­V 55V S5N----'---~a::00.P 5o(lRO.) -P 5dIRO,)P u(MR) - LOP u(HALT)- ~P 54a::(IS) 0P 55(05)0.P 56-P 57 .-,P,o-P,.-P,,-CDP'3- ~a::P'4- 00.P'5-a::00N~a::00.....a::w:Ei=U(I)Na::W:Ei=a::00It)~a::00.a::0O·CDI- a::0Q.A....AV..itI'\.'Iitv1'\ ..I"ii~v~ 11A"rD1 !J J J J J...J ...J~ ~x xa w CPUa::HANDSHAKECONTROLiii:IIIIiiiiiil!!"0"0

HD6305UO ,HD63A05UO ,--­HD63B05UOCMOS MCU (Microcomputer Unit)-ADVANCE INFORMATION-The HD630SUO is a CMOS .single·chip microcomputer unit(MCU) which is the DIP 40 pins version of the HD630SXO, andbuilt in 2k bytes of ROM, 128 bytes of RAM, 31 I/O pins, twoTimers and a Serial Communication Interface (SCI).HD6305UOP. HD63A05UOP.HD63B05UOP• HARDWARE FEATURES• 8·bit based MCU• 2048 bytes of ROM• 128 bytes of RAM• A total of 31 terminals• Two timers- 8·bit timer with a 7·bit prescaler (programmable prescaler;event counter)- 15·bit timl!r (commonly used with the SCI clock divider)• On-chip serial interface circuit (synchronized with clock)• Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation modes - Wait, Stop and StandbyMode• Minimum instruction cycle timeH06305UO ......... 1 J.lS (f = 1 MHz)H063A05UO ....... 0.67 J.lS (f = 1.5 MHz)H063B05UO ......• 0.5 J.lS (f = 2 MHz)• Wide operating rangeVee = 3 to 6V (f = 0.1 to 0.5 MHz)H06305UO ........ f 0.1 to 1 MHz (Vee = 5V ± 10%)H063A05UO ....... f = 0.1 to 1.5MHz (Vee = 5V ± 10%)H063B05UO ....... f = 0.1 to 2 MHz (Vee = 5V ± 10%)• SOFTWARE FEATURES• Similar to H06800 Instruction Set• Byte Efficient Instruction Set• Bit Manipulation• Bit Test and Branch• Versatile Interrupt Handling• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• 10 Powerful Addressing Modes• New Instructions - STOP, WAIT, DAA• Compatible with H06805 Family(DP·40)• PIN ARRANGEMENToHD6305UO(Top View)$ HITACHI 391

HD6305UO,HD63A05UO,HD63B05UO ----------------------~-• BLOCK DIAGRAMXTAl EXTAlTIMERPortAI/OTermlnelsPortSI/OTermlnlls8AccumulltorAIndexRegisterXCondition CodeRegister CCStack6PointerSProgrlmCounter6 "High" PCHProgrlmCounter8 "low" PClCPUCPUControlALUSarillDetlRegisterO.IiATiO.I~O./RxO.lTxO.O.O.Port 0I/OTerminalsPortC1/0Termlnlls392~HITACHI

HD6305VO,HD63A05VO,--­HD63B05VOCMOS MCU (Microcomputer Unit)-ADVANCE INFORMATION-The HD6305VO is a CMOS single.chip microcomputer unit(MCU) which is the DIP 40 pins version of the HD6305XO, andbuilt in 4k bytes of ROM, 192 bytes of RAM, 31 1/0 pins, twoTimers and a Serial Communication Interface (SCI).H D6305VOP, H D63A05VOP,HD63B05VOP• HARDWARE FEATURES• 8-bit based MCU• 4096 bytes of ROM• 192 bytes of RAM• A total of 31 terminals• Two timers- 8-bit timer with a 7-bit prescaler (programmable prescale r ;event counter)- 15-bit timer (commonly used with the SCI clock divider)• On·chip serial interface circuit (synchronized with clock)• Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation modes - Wait, Stop and StandbyMode• Minimum instruction cycle timeHD6305VO . . . . .. 1 iJ.s (f=lMHz)HD63A05VO ..... 0.67 iJ.S (f=1.5MHz)HD63B05VO ..... 0.5 iJ.s (f=2MHz)• Wide operating rangeVcc=3 to 6 V (f=O.l to 0.5MHz)HD6305VO ...... f=O.l to 1MHz (Vcc=5V±10%)HD63A05VO ..... f=O.l to 1.5MHz (Vcc=5V±10%)HD63B05VO ..... f=O.l to 2MHz (Vcc=5V±10%)• SOFTWARE FEATURES• Similar to HD6800 Instruction Set• Byte Efficient Instruction Set• Bit Manipulation• Bit Test and Branch• Versatile Interrupt Handling• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• 10 Powerful Addressing Modes• New Instructions - STOP, WAIT, DAA• Compatible with HD6805 Family(DP-40)• PIN ARRANGEMENTHD6305VO(Top View)_HITACHI 393

HD6305VO,HD63A05VO,HD63B05VO---------------------,----• BLOCK DIAGRAMXTAl EXTAlTIMERPortAI/OTerminlls88AccumulatorAIndexRegisterXCondition Coda5Regilter CCStack6PointerSPCPUCPUControlD,/iJiIT;D./~D./Rx Port 0D./Tx I/OD. TerminalsD.DoPortSI/OTerminllsProgremCounter8 "low" PClSarlllDlteRegisterPortCI/OTerminell394_HITACHI

HD6305XO,HD63A05XO,--­HD63B05XOCMOS MCU(Microcomputer Unit)The HD6305XO is a CMOS version of the NMOS 8-bit singlechipmicrocomputer, HD6805XO. The CMOS unit is upwardcompatible with the HD6805 family in respect to instructions.On the chip of the HD6305Xd, a CPU, a clock generator, a4KB ROM, a 128-byte RAM, 55 I/O terminals, two timers anda serial communication interface (SCI) are built in. Because ofthe CMOS process, the HD6305XO consumes less power thanthe NMOS HD6805XO. In addition, three low power dissipationmodes (stop, wait, and standby) support the low poweroperating.Other distinguished features include enhanced instructioncycle of the main instructions and the use of three additionalinstructions to obtain more improved system throughput.HD6305XOP, HD63A05XOP,HD63B05XOPHD6305XOF, HD63A05XOF,HD63B05XOF(DP-64S)-PRELIMINARY-• HARDWARE FEATURES.8·bit based MCU.4096-bytes of ROM• 128-bytes of RAM.A total of 55 terminals, including 32 I/O's, 7 inputs and 16outputs.Two timers- 8-bit timer with a 7-bit prescaler (programmable prescaler;event counter)- 15-bit timer (commonly used with the SCI clock divider).On-chip serial interface circuit (synchronized with clock).Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation. modes- Wait .••. In this mode, the clock oscillator is on and theCPU halts but the timer/serial/interrupt functionis operatable.- Stop •... In this mode, the clock stops but the RAMdata, I/O status and registers are held.- Standby .. In this mode, the clock stops, the RAM data• is held, and the other internal condition isreset.• Minimum instruction cycle time- HD6305XO ..... 1 /J.s (f = 1 MHz)- HD63A05XO .... 0.67 /J.S (f = 1.5 MHz)- HD63B05XO .... 0.5/J.s (f = 2 MHz)• Wide operating rangeVCC = 3 to 6V (f = 0.1 to 0.5 MHz)- HD6305XO ....• f = 0.1 to 1 MHz (VCC = 5V ± 100;6)- HD63A05XO .... f = 0.1 to 1.5 MHz (VCC = 5V ± 10%)- HD63B05XO .... f = 0.1 to 2 MHz (VCC = 5V ± 10%).System development fully supported by an evaluation kit(FP-64)• Byte efficient instruction set• Powerful bit manipulation instructions (Bit Set, Bit Clear, andBit Test and Branch usable for all RAM bits and all I/O terminals).A variety of interruptDperations• Index addressing mode useful for table processing• A variety of conditional branch instructions• Ten powerful addressing modes• All addressing modes adaptable to RAM, and I/O instructions• Three new instructions, STOP, WA IT! and DAA, added to theHD6805 family instruction set• I nstructions that are upward compatible with those of Motorola'sMC6805P2 and MC146805G2• SOFTWARE FEATURES.Similar to HD6800~HITACHI 395

HD6305XO,HD63A05XO,HD63B05XO~~~~~~~~~·~~~~~~~~~~~~-• PIN ARRANGEMENT• HD6305XOP, HD63A05XOP, HD63B05XOPVssRES ::INTmv.=XTALEXTALNUMTIMERA,A.AliA.A3A2A,Ao8,8,8s8.838 28,8 0C,/TxC./RxCliCKC.C3C20 GoG,G 2G 3G.GsG.G,F,F.FIF.F3F2F,FoE7E,EsE.E3E2E,Eo0 7O./INTz0,O.0,O 20,C,Co -'~____________-J-- Vee(Top View)• HD6305XOF, HD63A05XOF, HD63B05XOFTIMERA7A6C7/TxC6/Rx(Top View)• BLOCK DIAGRAMXTAl EXTAl RES HUM iNT Si'iYTIMERPortACPUCPUControlD,o.,mr,D.D. PortO0, InputD, Terminal,D.Port B1/0TerminalsAlUw.IIEoE.E, Port EE,Eo OutputE. Terminer,E,E,FoF.F, PortFF,OutputF.F, Terminal,F,F,396eHITACHIGoG.Go PortGGo 110Go Terminer.GoGoG,

----------------------HD6305XO,HD63A05XO,HD63B05XO-ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply voltage Vee -0.3- +7.0 VI nput voltage Yin -0.3 - Vee + 0.3 VOperating temperature Topr 0-+70 °cStorage temperature Tstg -55-+150 °c[NOTE]These prod'JCts have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normaloperation, we recommended V In, Vout; V SS ~ (V In or V out ) ~ V cc.- ELECTRICAL CHARACTERISTICS.DC Characteristics (Vee = 5.0V ± 10%, Vss = GND and T. = 0 - +70°C unless otherwise specified)ItemSymbolTestconditionmin typ maxUnitRES,S'fBY Vee- 0.5 - Vee+ 0.3Inputvoltage EXTAL VIHVee x 0.7 - Vee+ 0.3"High"Others 2.0 - Vee+ 0.3Input voltage"Low"All InputsVIL-0.3 - 0.8Operating - 5 10Current * Wait - 2 5IcCf = 1MHz**dissipationStop - 2 10InputleakagecurrentStandby - 2 10TIMER,INT,~BYD7'Ao-A7, Yin = 0,5-ThreestateBo - B7,IITS!! Vee - 0.5VIIILI - - 1current Co -C7,- - 1Go -G7,Eo - E7~**Fo-F7***Input Allcapacity terminals CinYin = OVf = 1MHz,- - 12VVVVmA\mAp.Ap.Ap.Ap.ApF*VIHmin = Vcc-1.0V, VIL max = 0.8 V-*The value .t f • xMHz can be calculated by the following equation:*··At standby modeICC (f" xMHz)" Icc (f .. 1MHz) multiplied by x_HITACHI397

HD6305XO,HD63A05XO,HD63B05XO----------------------• AC CharlCteriltics (Vee = 6.0V ± 10%, Vss = GND and T. = 0 - +70 o C unless otherwise specified)ItemClockfrequencyTest HD6305XO HD63A05XO HD63B05XOSymbolUnitcondition min typ max min typ max min typ maxfel 0.4 - 4 0.4 - 6 0.4 - 8 MHzCycle time tcye 1.0 - 10 0.666 - 10 0.5 - 10 IlSrNT pulsewidth +2 0 +200tlWl te~c - - !.2oo - -tcye- - ns- - t~e - -tcye- - nsINT2 pulseteyewidthtlWl2+250 + 00 +200RES pulsewidthtRWl 5 - - 5 - - 5 - - teyeTIMER pulsetcyeteyewidthtTWl+250 +200 +200OscillationCl = 22pF ±200htcye- -- -- - nsstart time tose Rs = 60n - - 20 - - 20 - - 20 ms(crystal)maxReset delaytimetRHlExternal cap.2.21lF80 - - 80 - - 80 - - ms• Port Electrical Characteristics (Vee = 5.0V ± 10%, Vss = GND and Ta= 0 - +70°C unless otherwise specified)ItemSymbolTestmin typ maxconditionUnitOutput volt· IOH = -2001lA 2.4 - - Vage "High" Ports A.B,C,G.Output volt· E,Fage "Low"Input volt·age "High"VOHIOH = -1OIlA Vee - 0.7 - - VVOL IOl = 1.6mA - - 0.55 V---VIH 2.0 - Vee + 0.3 VInput volt· Ports A,age "Low" B,C,D, Vil -0.3 -0.8 VGInput leak·Vin = 0.5-III-1age current - 1Vee - 0.5VIlA• SCI Timing (Vee = 5.0V±10%, Vss = OV and Ta = 0 -- +70°C unless otherwise specified)ItemSymbolTest HD6305XO HD63A05XO HD63B05XOCondition min typ max min typ max min typ maxClock Cycle tScye 1 - 32768 0.67 - 21845 0.5 - 16384 IlSData Output Delay Time tTXD Fig. 1 - - 250 - - 250 - - 250 nsData Set·up Time tSRX Fig. 2 200 - - 200 - - 200 - - nsData Hold Time tHRX 100 - - 100 - - 100 - - nsUnit398 ~HITACHI

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOClock OutputCs/a

HD6305XO,HD63A05XO,HD63B05XO-----------------------MEMORY MAPThe memory map of the HD6305XO MCU is shown inFig. 4. During interrupt processing, the contents of the CPUregisters are saved into the stack in the sequence shown inFig. 5. This saving begins with the lower byte (PCL) of theprogram counter. Then the value of the stack pointer isdecremented and the higher byte (PCH) of the programcounter, index register (X), accumulator (A) and conditioncode register (CC) are stacked in that order. In a subroutinecall, only the contents of the program counter (pCH and PCL)are stacked.°12712825525640954096818281918192I/O PortsTimerSCIRAM(128Bytes)StackNot UsedROM(4,096Bytes)1-----------InterruptVectorsNot Used1$0000$007Frao$gOFF$ 100soi51000$1FF6$1FFF$200016383 $3FFF0 PORT A $001 PORT B $012 PORT C $023 PORT 0 $03"4 PORT A DDR $04'5 PORT BOOR S05'6 PORT C DDR $06'7 PORT G DDR 507'8 Timer Data Reg $089 Timer CTRL Reg $0910 Mise Heg $OA11 PORT E SOB12 PORT F SOC13 PORT G $00Not Used16 SCI CTRL Reg17 SCI STS Reg18 SCI Data Reg127Not Used$10$11$12$7F• Write only regi ster.. Read only regis terFigure 4 Memory Map of H06305XO MCU-REGISTERSThere are five registers which the programmer can operate.7 o1 ~ _______A....JI Accumulator7 o1 '--_______ X ....JReglsterI Index13 o1 ""'_____________PC ...1. I Counter~rogram13 6 5 01 .... 0-,-1 o .... lo-"_olL.0 ..... 10..... 1_~ .... 1_1 IL.-__s_ p _~I ~~~~~rr--__ ...".._-...~ ConditionCode........................................... RegisterCarry/BorrOWZero1...-. ___ Negative'------InterruptMaskl....------HalfCarryFigure 6 Programming Model• Accumulator (A)This accumulator is an ordinary 8-bit register which holdsoperands or the result of arithmetic operation or data processing.• Index Register (X)The index register is an 8-bit register, and is used for indexaddressing mode. Each of the addresses contained in theregister consists of 8 bits which, combined with an offsetvalue, provides an effective address.In the case of a read/modify/write instruction, the indexregister can be used like an accumulator to hold operationdata or the result of operation.If not used in the index addressing mode, the register canbe used to store data temporarily.Push7 6 543 2 1 0I n-4 1 1 1 Code Condition n+1Registern-3 Accumulator n+2n-2 Index Register n+3n-1 1 1 I PCW n+4n PCl' n+5Pull• Program Counter (PC)The program counter is a 14-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 14-bit register that indicates the addressof the next stacking space. Just after reset, the stackpointer is set at address $OOFF. It is decremented when datais pushed, and incremented when pulled. The upper 8 bitsof the stack pointer are fIXed to 000000 II. During the MCUbeing reset or during a reset stack pointer (RSP) instruction,the pointer is set to address $OOFF. Since a subroutine orinterrupt can use space up to address $OOCI for stacking, thesubroutine can be used up to 31 levels and the interrupt upto 12 levels.• In a subroutine call, only PCl and PCH are stacked.Figure 5 Sequence of Interrupt Stacking400 _HITACHI• Condition Code Regilter (CC)The condition code register is a 5·bit register, each bitindicating the result of the instruction just executed. Thebits can be individually tested by conditional branch instruc-

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOtions. The CC bits are as follows:Half Carry (H): Used to indicate that a carry occurred betweenbits 3 and 4 during an arithmetic operation(ADD, ADC).Interrupt (I): Setting this bit causes all interrupts, excepta software interrupt, to be masked. If aninterrupt occurs with the bit I set, it islatched. It will be processed the instantthe interrupt mask bit is reset. (More specifically,it will enter the interrupt processingroutine after the instruction following theCLI has been executed.)Negative (N): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is negative (bit 7 is logic"I").Zero (Z): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is zero.Carry I Represents a carry or borrow that occurredBorrow (C): in the most re::ent arithmetic operation. Thisbit is also affected by the Bit Test and Branch. instruction and a Rotate instruction.-INTERRUPTThere~e six different types of interrupt: external interrupts(lNT,. IN.T2), internal timer interrupts (TIMER,TIMER2), senal mterrupt (SCI) and interrupt by an instruction(SWI).Of these six interrupts, the INT2 and TIMER or the SCIand TIMER2 generate the same vector address, respectively.When an interrupt occurs, the program in progress stopsand the then CPU status is saved onto the stack. And then,the interrupt mask bit (I) of the condition code register isset and the start address of the interrupt processing routineis obtained from a particular interrupt vector address. Thenthe interrupt routine starts from the start address. Systemcan exit from the interrupt routine by an RTI instruction.When this instruction is executed, the CPU status beforethe interrupt (saved onto the stack) is pulled and the CPUrestarts the sequence with the instruction next to the one atwhich the interrupt occurred. Table 1 lists the priority ofinterrupts and their vector addresses.Table 1Priority of InterruptsInterrupt Priority Vector AddressRES 1 $1 FFE, $1FFFSWI 2 $1FFC, $1FFDINT 3 $1FFA, $1FFBTIMER/INT2 4 $1 FFS, $1FF9SCI/TIMER2 5 $1FF6, $1FF7A flowchart of the interrupt sequence is shown in Fig. 7.A block diagram of the interrupt request source is shown inFig. 8. r--------.y TNT1-1$FF-+SPO-+DDA'SCLA INT Logic$FF ..... TDA$7F--Timer Prescaler$50 ..... TCA$3F--SSA$OO ..... SCR$7F ...... MRyTIMERY SCIFigure 7 Interrupt Flowchart_HITACHI 401

HD6305XO,HD63A05XO,HD63B05XO----------------------In the block diagram, both the external interrupts INT andINT2 are edge trigger inputs. At the falling edge of each input,an interrupt request is generated and latched. The INT interruptrequest is automatically cleared if jumping is made tothe INT processing routine. Meanwhile, the INT2 request iscleareu ~ "0" is written in bit 7 of the miscellaneous register.For the external interrupts (INT, INT2), internal timerinterrupts (TIMER, TIMER2) and serial interrupt (SCI), eachinterrupt request is held, but not processed, if the I bit of thecondition code register is set. Immediately after the I bit iscleared, the corresponding interrupt processing starts accordingto th~ority .The INT2 interrupt can be masked by setting bit 6 of themiscellaneous register; the TIMER interrupt by setting bit 6of the timer control register; the SCI interrupt by setting bit5 . of the serial status register; and the TIMER2 interrupt bysetting bit 4 of the serial status register.The status of the INT terminal can be tested by a BIL orBIH instruction. The INT falling edge detector circuit andits latching circuit are independent of testing by these instructions.This is also true with the status of the INT2 terminal.• Miscellaneous Register (MR; $OOOA)The interrupt vector address for the external interruptINT2 is the same as that for the TIMER interrupt, as shownin Table 1. For this reason, a special register called the miscellaneousregister (MR; $OOOA) is available to control theINT2 interrupts.Bit 7 of this register is the iNTi interrupt request flag.When the falling edge is detected at the INT2 terminal, "1"is set in bit 7. Then the software in the interrupt routine(vector addresses: $IFF8, SIFF9) checks bit 7 to see if itis INT2 interrupt. Bit 7 can be reset by software.Miscellaneous Register (MR;$OOOA)76 543210~6VIZIZVVIZJoiNTi Interrupt MaskL..-___________ INT2 Interrupt Request FlagMiscellaneous Register (MR; SOOOA)Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",then the INT2 interrupt is disabled. Both read and write arepossible with bit 7 but "I" cannot be written in this bit bysoftware. This means that an interrupt request by softwareis impossible .When reset, bit 7 is cleared to "0" and bit 6 is set to "I".-TIMERFigure 9 shows an MCV timer block diagram. The timerdata register is loaded by software and, upon receipt of aclock input, begins to count down. When the timer dataBIH/BIL TestINT InterruptLatchVectoring generated$1FFA.$1FFBCondition Code Register (CC)INTFalling Edge DetectorTIMER~~"""-I---- Vectoring generated$1FF8,$1FF9SCI/TIMER2Serial StatusRegister (SSR)}---~--- Vectoring generated$1FF6.$1FF7Figure 8 Interrupt Request Generation Circuitry402_HITACHI

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOregister (TOR) becomes "0", the timer interrupt requestbit (bit 7) in the timer control register is set. In response tothe interrupt request, the MCU saves its status into the stackand fetches timer interrupt routine address from addresses$1 FF8 and $1 FF9 and execute the interrupt routine. Thetimer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the timer control register. The mask bit(I) in the condition code register can also mask the timerinterrupt.The source clock to the timer can be either an externalsignal from the timer input terminal or the internal E signal(the oscillator clock divided by 4). If the E signal is used asthe source, the clock input can be gated by the input to thetimer input terminal.Once the timer count has reached "0", it starts countingdown with "$FF". The count can be monitored wheneverdesired by reading the timer data register. This permits theprogram to know the length of time having passed after theoccurrence of a timer interrupt, without disturbing the contentsof the counter.When the MCU is reset, both the prescaler and counter areinitialized to logic "1". The timer interrupt request bit(bit 7) then is cleared and the timer interrupt mask bit (bit6) is set.To clear the timer interrupt request bit (bit 7), it is necessaryto write "0" in that bit.TCR7oTimer interrupt requestAbsentPresent• Timer Control Register (TCR; $0009)Selection of a clock source, selection of a prescaler frequencydivision ratio, and a timer interrupt can be controlledby the timer control register (TCR; $0009).For the selection of a clock source, anyone of the fourmodes (see Table 2) can be selected by bits 5 and 4 of thetimer control register (TCR).Timer Control Register (TCR; $0009)L Prescaler division ratio selectionPrescaler initializeL.. ________ Clock input sourceL.. __________ Timer interrupt maskL----------------Tirner interrupt requestAfter reset, the TCR is initialized to "E under timer terminalcontrol" (bit 5 = 0, bit 4 = 1). If the timer terminal is"1", the counter starts counting down with "$FF" immediatelyafter reset.When "1" is written in bit 3, the prescaler is initialized.This bit always shows "0" when read.TCRTable 2Bit 5 Bit 4Clock Source Selection0 0 I nternal clock EClock input sourceTCR6oTimer interrupt maskEnabledDisabled0 1 E under timer terminal control1 0 No clock input (counting stopped)1 1 Event input from timer terminalInitialize!InternalClock)E--+---iTimer DataRegisterL..---r-----r----.... Timer InterruptWriteReadFigure 9 Timer Block Diagram~HITACHI 403

HD6305XO.HD63A05XO.HD63B05XO~~~~~~~~~~~~~~~~~~~~~~A prescaIer division ratio is selected by the combination ofthree bits (bits 0, 1 and 2) of the timer control register (seeTable 3). There are eight different division ratios: +1, +2, +4,+8, +16, +32, +64 and +128. After reset, the TCR is set to the+1 mode.Table 3TCRBit2 Bit 1 BitOPrescaler Division Ratio SelectionPrescaler division ratio0 0 0 +10 0 1 +2·0 1 0 +40 1 1 +8T:A timer interrupt is enabled when the timer interrupt maskbit is "0", and disabled when the bit is "1". When a timerinterrupt occurs, "1" is set in the timer interrupt request bit.This bit can be cleared by writing "0" in that bit.-SERIAL COMMUNICATION INTERFACE (SCI)This interface is used for serial transmission or receptionof 8-bit data. Sixteen transfer rates are available in the rangefrom IllS to approx. 32 ms (for oscillation at 4 MHz).The SCI consists of three 'registers, one eighth counter andone prescaler. (See Fig. 10.) SCI communicates with the CPUvia the data bus, and with the outside world through bits 5,6 and 7 of port C. Described below are the operations ofeach register and data transfer.-SCI Control Register (SCR; $0010)1 0 0 +161 0 1 +3~.1 1 0 +64;)1 1 1 +128:SCI Control Registers (SCR; 0010)E"-............. _--'TransferClockGeneratorInitializeSCI Status Registers(SSR :$0011)Not UsedSCI TIMER2Figure 10 SCI Block Diagram404 _HITACHI

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOSCR7oC, terminalUsed as I/O terminal (by DDR).Serial data output (DDR output)Bit 7 (SSR7)Bit 7 is the SCI interrupt request bit which is set uponcompletion of transmitting or receiving 8·bit data. It iscleared when reset or data is written to or read from theSCI data register with the SCR5="'1 ". The bit can also becleared by writing "0" in it.SCR6oC 6 terminalUsed as I/O terminal (by DDR).Serial data input (DDR input)SCR5 SCR4 Clock source C 5 terminal0 0 - Used as I/O terminal (by0 1 -DDR).1 0 Internal Clock output (DDR output)1 1 External Clock input (DDR input)Bit 7 (SCR7)When this bit is set, the DDR corresponding to the C,becomes "1" and this tenninal serves for output of SCI data.After reset, the bit is cleared to "0".Bit 6 (SCR6)When this bit is set, the DDR corresponding to the C 6becomes "0" and this tenninal serves for input of SCI data.After reset, the bit is cleared to "0".Bits 5 and 4 (SCR5, SCR4)These bits are used to select a clock source. After reset,the bits are cleared to "0".Bit 6 (SSR6)Bit 6 is the TIMERz interrupt request bit. TIMERz is usedcommonly with the serial clock generator, and SSR6 is seteach time the internal transfer clock falls. When reset, thebit is cleared. It also be cleared by writing "0" in it. (Fordetails, see TIMER2 .)Bit 5 (SSR5)Bit 5 is the SCI interrupt mask bit which can be set orcleared by software. When it is "I" , the SCI interrupt (SSR7)is masked. When reset, it is set to "1".Bit 4 (SSR4)Bit 4 is the TIMERz interrupt mask bit which can be setor cleared by software. When the bit is "1", the TIMERzinterrupt (SSR6) is masked. When reset, it is set to "I".Bit 3 (SSR3)When "1" is written in this bit, the prescaler of the transferclock generator is initialized. When read, the bit always is "0".Bits 2..., 0Not used.SSR7oSCI interrupt requestAbsentPresentBits 3..., 0 (SCR3 -- SCRO)These bits are used to select a transfer clock rate. Afterreset, the bits are cleared to "0".SCR3 SCR2 SCR1 SCROTransfer clock rate4.00 MHz 4.194 MHz0 0 0 0 1J,Ls 0.95J,Ls0 0 0 1 2J,Ls 1.91J,Ls0 0 1 0 4J,Ls 3.82J,Ls0 0 1 1 8J,Ls 7.64J,LsI I I I I I1 1 1 1 32768J,Ls 1/32 sSSR6oSSR5oSSR4oTIMERz interrupt requestAbsentPresentSCI interrupt maskEnabledDisabledTIME Rz interrupt maskEnabledDisabled-SCI Data Register (SDR; $0012)A serial.parallel conversion register that is used for transferof data.-SCI Status Register (SSR; $0011)76543210• Data TransmissionBy writing the desired control bits into the SCI controlregisters, a transfer rate and a source of transfer clock aredetennined and bits 7 and 5 of port C are set at the serialdata output tenninal and the serial clock tenninal, respec·tively. The transmit data should be stored from the accumu·lator or index register into the SCI data register. The datawritten in the SCI data register is output from the C,/Txtenninal, starting with the LSB, synchronously with thefalling edge of the serial clock. (See Fig.l!.) When 8 bits of~HITACHI 405

HD6305XO,HD63A05XO,HD63B05XO----------------------data have been transmitted, the interrupt request bit is set inbit 7 of the SCI status register with the rising edge of thelast serial clock. This request can be masked by setting bit5 of the SCI status register. Once the data has been sent, the8th bit data (MSB) stays at the C7/Tx terminal. If an externalclock source has been selected, the transfer rate determined bybits 0"" 3 of the SCI control register is ignored, and the Cs/CK terminal is set as input. If the internal clock has beenselected, the Cs/CK terminal is set as output and clocks areoutput at the transfer rate selected by bits 0 ,.., 3 of the SCIcontrol register.Figure 11SCI Timing Chart• Data ReceptionBy writing the desired control bits into the SCI controlregister, a transfer rate and a source of transfer clock are determinedand bit 6 and 5 of port C are set at the serial datainput terminal and the serial clock terminal, respectively.Then dummy-writing or -reading the SCI data register, thesystem is ready for receiving data. (This procedure is notneeded after reading subseqent received data. It must be takenafter reset and after not reading subsequent received data.)The data from the C 6 /Rx terminal is input to the SCIdata register synchronously with the rising edge of theserial clock (see Fig.II). When 8 bits of data have been received,the interrupt request bit is set in bit 7 of the SCIstatus register. This request can be masked by setting bit 5of the SCI status register. If an external clock source have beenselected, the transfer rate determined by bits 0,.., 3 of the SCIcontrol register is ignored and the data is received synchronouslywith the clock from the Cs /CK terminal. If the internalclock has been selected, the Cs/CK terminal is set as outputand clocks are output at the transfer rate selected by bits 0 ,..,3 of the SCI control register..TIMER2The SCI transfer clock generator can be used as a timer.The clock selected by bits 3 ,.., 0 of the SCI control register(4 p.s ,.., approx. 32 ms (for oscillation at 4 MHz» is input tobit 6 of the SCI status register and the TIMER2 interruptrequest bit is set at each falling edge of the clock. Since interruptrequests occur periodically, TIMER2 can be used as areload counter or clock.CD-----1"'-__..J.--_....;00::;:,2 ®t@@LTIMER2 is commonly used with the SCI transfer clockgenerator. If wanting to use TIMER2 independently of theSCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCIclock source.If "Internal" is selected as the clock source, reading orwriting the SDR causes the prescaler of the transfer clockgenerator to be initialized.-I/O PORTSThere are 32 input/output terminals (ports A, B, C, G).Each I/O terminal can be selected for either input or outputby the data direction register. More specifically, an I/O portwill be input if "0" is written in the data direction register,and output if "1" is written in the data direction register.Port A, B or C reads latched data if it has been programmedas output, even with the output level being fluctuated by theoutput load. (See Fig. 12-a.) For port G, in such a case, thelevel of the pin is always read when it is read. (See Fig. 12-b.)This implies that, even when "1" is being output, port G mayread "0" if the load condition causes the output voltage todecrease to below 2.0V .When reset, the data direction register and data register goto "0" and all the input/output terminals are used as input.Bit of datadirectionregisterBit ofoutputdataStatus ofoutputInput toCPU1 0 0 01 1 1 10 X 3-state Pina. Ports A, Band CCD : Transfer clock generator is reset and mask bit (bit 4of SCI status register) is cleared.OO.@ : TlMER2 interrupt request®.@ : TlMER2 interrupt request bit clearedb. Port GFigure 12 Input/Output Port Diagram406 _HITACHI

~~~al ____________________---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOThere are 16 output-only terminals (ports E and F). Eachof them can also read. In this case, latched data is read evenwith the output terminal level being fluctuated by the outputload (as with ports A, B and C).When reset, "Low" level is output from each output terminal.Seven input-only terminals are available (port D). Writingto an input terminal is invalid.All input/output terminals, output terminals and inputterminals are TTL compatible and CMOS compatible in respectof both input and output.If I/O ports or input ports are not used, they should beconnected to Vss via resistors. With none connected to theseterminals, there is the possibility of power being consumeddespite that they are not used.-RESETThe MCV can be reset either by external reset input (RES)or power-on reset. (See Fig. 13.) On power .uP, the resetinput must be held "Low" for at least tose to assure that theinternal oscillator is stabilized. A sufficient time of delay canbe obtained by connecting a capacitance to the RES input asshown in Fig. 14. .5VVeeOV-------RESTerminal --------f""1--~t--6-l EXTALJO-S:OM>U= 5 XTAL HDS:105XOMCU10-22pF±20%Crystal OscillatorHD6305XOMCUExternal Ceramic OscillatorClockInput 6 EXTALNC 5 XTAL HD6305XOMCUFigure 15External Clock DriveInternal Oscillator Circuit~Figure 13 Power On and Reset Timingc,C:y's5 Co 6XTALEXTALAT CutParallelResonanceCo=7pF max.f=2.0-S.0MHzRs=600 max.100kSl typ 2Vec--'V'I/Iv--+----,RES -:;;;. 2.2/IFHD6305XOMCU(a)Figure 16 Parameters of CrystalFigure 14 Input Reset Delay Circuit-INTERNAL OSCILLATORThe internal oscillator circuit is designed to meet therequirement for minimum external configurations. It can bedriven by connecting a crystal (AT cut 2.0 - 8.0MHz) orceramic oscillator between pins 5 and 6 depending on the requiredoscillation frequency stability.Three different terminal connections are shown in Fig. IS.Figs. 16 and 17 illustrate the specifications and typical arrangementof the crystal, respectively.[NOTE] Use as short wirings as possible for connection of the crystalwith the EXTAL and XTAL terminals. Do not allow thesewirings to cross others.Figure 17 Typical Crystal Arrangement~HITACHI 407

HD6305XO,HD63A05XO,HD63B05XO-----------------------LOW POWER DISSIPATION MODEThe HD6305XO has three low power dissipation modes:wait, stop and standby.• Wait ModeWhen WAlT instruction being executed, the.,CU entersinto the wait mode. In this mode, the oscillator stays activebut the internal clock stops. The CPU stops but the peripheralfunctions - the timer and the serial communication interface- stay active. (NOTE: Once the system has entered thewait mode, the serial communication interface can no longerbe retriggered.) In the wait mode, the registers, RAM and I/Oterminals hold their condition just before entering into thewait mode.The escape from this mode can be done by interrupt (INT,TIMER/INT2 or SCI/TIMER2), RES or STBY. The RESresets the MCU and the STBY brings it into the standbymode. (This will be mentioned later.)When interrupt is requested to the CPU and accepted, thewait mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interrupt ismasked by the I bit of the condition code register, after releasingfrom the wait mode the MCU executes the instructionnext to the WAIT. If an interrupt other than the INT (Le.,TIMER/INT2 or SCI/TIMER2) is masked by the timer controlregister, miscellaneous register or serial status register, thereis no interrupt request to the CPU, so the wait mode cannotbe released.Fig. 18 shows a flowchart for the wait function.• Stop ModeWhen STOP instruction being executed, MCU enters intothe stop mode. In this mode, the oscillator stops and the CPUand peripheral functions become inactive but the RAM,registers and I/O terminals hold their condition just beforeentering into the stop mode.The escape from this mode can be done by an externalinterrupt (INT or INTi), RES or STBY. The RES resets theMCU and the STBY brings into the standby mode.When interrupt is requested to the CPU and accepted,the stop mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interruptis masked by the I bit of the condition code register,after releasing from the stop mode, the MCU executes theinstruction next to the STOP. If the INTl interrupt is maskedby the miscellaneous register, there is no interrupt request tothe MCU, so the stop mode cannot be released.Fig. 19 shows a flowchart for the stop function. Fig. 20shows a timing chart of return to the operation mode fromthe stop mode.For releasing from the stop mode by an interrupt, oscillationstarts upon input of the interrupt and, after the internaldelay time for stabilized oscillation, the CPU becomes active.For restarting by RES, oscillation starts when the RES goes"0" and the CPU restarts when the RES goes "1". The durationof RES="O" must exceed tose to assure stabilized oscillation.• Standby ModeThe MCU enters into the standby mode when the STBYterminal goes "Low". In this mode, all operations stop andthe internal condition is reset but the contents of the RAM arehold. The I/O terminals turn to high-impedance state. Thestandby mode should escape by bringing STBY "High". TheCPU must be restarted by reset. The timing of input signalsat the RES and STBY terminals is shown in Fig. 21 .Table 4 lists the status of each parts of the MCU in eachlow power dissipation modes. Transitions between each modeare shown in Fig. 22.408 _HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XOOscillator ActiveTimer and SerialClock ActiveAll Other ClocksStopInitializeCPU, TIMER, SCI,10 and All. Other FunctionsNoNoload PC fromInterrupt VectorAddressesFetchInstructionFigure 18 Wait Mode Flowchart_HITACHI409

HD6305X~HD63A05XO.HD63B05XO~~~~~~~~~~~~~~~~~~~~~-Oscillator andAll Clocks Stop.NoTurn on OscillatorWait for Time Delayto StabilizeTurn on OscillatorWait for Time Delayto Stabilize1=0Load PC fromInterrupt VectorAddressesFetchInstructionFigure 19 Stop Mode Flowchart410_HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XOM11f111111111111111111111111111111111111111111111111111111I11(E ~~~~Oscillator 111111111"" I" 111111111111tSTOP instructionexecutedOscillator 11111111111111111111111111111EInterrupt(a) Restart by Interruptstabilized (built-in delay time)restartSTOP instructionexecutedTime required for oscillation to becomestabilized (tosclResetstart(b) Restart by ResetFigure 20 Timing Chart of Releasing from Stop Mode\~~IiIIII I I'-_oA_-'-__I'\toscRestartFigure 21Timing Chart of Releasing from Standby ModeTable 4Status of Each Part of MCU in Low Power Dissipation ModesHard-wareModeWAITSTOPStandbySoftwareConditionStart Oscil- Timer, 1/0 EscapeCPURegister RAMlatorSerialterminalWAIT instructionSTOP instructionSTBY, RES, INT, IN/2,Active Stop Active Keep Keep Keep each interrupt request ofTIMER, TIMER2, SCIStop Stop Stop Keep Keep Keep STBY, RES, INT, INT2STBY="Low" Stop Stop Stop Reset KeepHigh impedanceSTBY="High"_HITACHI 411

HD6305XO,HD63A05XO,HD63B05XO----------------------Figure 22 Transitions among Active Mode, Wait Mode,Stop Mode, Standby Mode and Reset-BIT MANIPULATIONThe HD6305XO MCV can use a single instruction (BSETor BCLR) to set or clear one bit of the RAM or an I/O port(except the write-only registers such as the data directionregister). Every bit of memory or I/O within page 0 ($00 ,..,$FF) can be tested by the BRSET or BRCLR instruction;depending on the result of the test, the program can branch torequired destinations. Since bits in the RAM, or I/O can bemanipulated, the user may use a bit within the RAM as a flagor handle a single I/O bit as an independent I/O terminal.Fig. 23 shows an example of bit manipulation and the validityof test instructions. In the example, the program is configuredassuming that bit 0 of port A is connected to a zero crossdetector circuit and bit I of the same port to the trigger of atriac.The program shown can activate the triac within a time ofIO#ls from zero-crossing through the use of only 7 bytes onthe ROM. The on

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XO• Indexed (8-bit Offset)See Fig. 29. The EA is the contents of the byte followingthe operation code, plus the contents of the index register.This mode allows access up to the lower 511 th address ofmemory. Each instruction when used in the index addressingmode (8-bit offset) requires a length of 2 bytes.• Indexed (16-bit Offset)See Fig. 30. The contents of the 2 bytes following theoperation code are added to content of the index registerto compute the value of EA. In this mode, the completememory can be accessed. When used in the indexed addressingmode (16-bit offset), an instruction must be 3 bytes long.• Bit Set/ClearSee Fig. 3 1. This addressing mode is applied to the BSETand BCLR instructions that can set or clear any bit on pageO. The lower 3 bits of the operation code specify the bit tobe set or cleared. The byte that follows the operation codeindicates an address within page O.,Memory~ ~AIj: :IPROG LOA :$F8 058ELI=~A~6=:t_------..J05BFl F8I~II• Bit Test and BranchSee Fig. 32. This addressing mode is applied to the BRSETand BRCLR instructions that can test any bit within page 0and can be branched in the relative addressing mode. Thebyte to be tested is addressed depending on the contents ofthe byte following the operation code. Individual bits withinthe byte to be tested are speCified by the lower 3 bits of theoperation code. The 3rd byte represents a relative value whichwill be added to the program counter when a branch conditionis established. Each of these instructions should be 3 byteslong. The value of the test bit is written in the carry bit of thecondition code register.• ImpliedSee Fig. 33. This mode involves no EA. All informationneeded for execution of an instruction is contained in theoperation code. Direct manipulation on the accumulatorand index register is included in the implied addressing mode.Other instructions such as SWl and RTI are also used in thismode. All instructions used in the implied addressing modeshould have a length of one byte.:: ---==-_-c.Ar- ~ F8 IIndex RegIStack PointProg Count05COCCFigure 24Example of Immediate AddressingMemoryACATFCB320048~~L:~~---i_---~~-----{~~2~O:::Jlndex egPROG LOA CAT 0520t-:~t::::J __ .-J052E I-.8• II :IIIIStack kt~in~t --""'"Prog !ount052FCCFigure 25Example of Direct Addressing~HITACHI 413

HD6305XO,HD63A05XO,HD63B05XO----------------------MemoryA40Index RegIStack PointtATFCB6406E5~~4@0~:l ______________ ~Prog Count040CCCFigure 26Example of Extended Addressing,IMemory•. ~ .PROG BEQ PROG2 04A7 2704A8 18~; IFigure 27Example of Relative AddressingMemoryATABLFCC LlOOB8~:J4~C::~----~~~------1-----------~~4~C;;.;J.. 49 n ex e'ROG CDA X '5

----------------------HD6305XO,HD63A05XO,HD63B05XOTABl FCB BF OOB9FCB 86 008AFCB DB 008BFCB CF 008CPROG LOA TABL.X 075B075C, MeJory: :8F86DBCF: :E689§, ,lEAI 008C ~,/ Adder "'--r- --,-Ar1CFIndex Reg03Stack PointIIProg CountI 0750CCIIFigure 29Example of Index (8-bit Offset) AddressingMemory~ . .PROG lOA TABL.X g::~ .......;.;---tTABl ~g: :: g~~~ ...0694J-""';';"'_f"FCB DB 0780 DBFCB CF 0781 .......... C ... F_ ...t::i:;::::t---------JFigure 30Example of Index (16-bit Offset) AddressingMemoryPORT BEaU 1 0001BFAPROG BClR 6. PORT B 058F t=j;10t:j ____....J0590 01~I , :,Index RegIStack PointgOg ~ount0591CCFigure 31Example of Bit Set/Clear AddressingeHITACHI415

HD6305XO,HD63A05XO,HD63B05XO------------------------------------------~PORT C Eau 2.0002 1--........ --4 14'--_-'AInde. RegIPROG BRCLR 2.PORT C. PROG 2 g:~:I--~~-t IProg ~ount05940576 I--";';;'-oflFigure 32Example of Bit Test and Branch AddressingMemorv~'''''G TAX .5.. ~~II• II•I•Figure 33Example of Implied Addressing-INSTRUCTION SETThere are 62 basic instructions available to the HD6305XOMeU. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, andcontrol. The details of each instruction are described inTables 5 through 11.• Register/Memory InstructionsMost of these instructions use two operands. One operandis either an accumulator or index register. The other is derivedfrom memory using one of the addressing modes used on theHD6305XO MeU. There is no register operand in the unconditionaljump instruction (IMP) and the subroutine jumpinstruction (JSR). See Table 5.• ReacllModify/Write InstructionsThese instructions read a memory or register, then modifyor test its contents, and write the modified value into thememory or register. Zero test instruction (TST) does notwrite data, and is handled a5an exception in the read/modify/write group. See Table 6.416 _HITACHI• Branch InstructionsA branch instruction branches from the program sequencein progress if a particular condition is established. See Table 7.• Bit Manipulation InstructionsThese instructions can be used with any bit located up tothe lower 255th address of memory. Two groups are available;one for setting or clearing and the other for bit testing andbranching. See Table 8.• Control InstructionsThe control instructions control the operation of the MeUwhich is executing a program. See Table 9.• List of Instructions in Alphabetical OrderTable 10 lists all the instructions used on the HD6305XOMeU in the alphabetical order.• Operation Code MapTable 11 shows the operation code map for the instructionsused on the MeU.

----------------------HD6305XO,HD63A05XO,HD63B05XOOperationsload A from Memoryloed X from Memory-----Store A in MemoryStore X in MemoryAdd Memory to AAdd Memory and CarrytoASubtract MemorySubtract Memory fromA with BorrowAND Memory to AOR Memory with AExclusive OR Mamorywith AArithmetic Compare Awith MemoryArithmetic Compare Xwith Memory8it Test Memory withA (logical Compare)Jump UnconditionalJump to SubroutineMnemoniclOAlOXSTASTXADDADCSUBSBCANDORAEORCMPCPXBITJMPJSRSymbols: Op = Operation# = Number of bytes- = Number of cyclesTable 5 Register/Memory InstructionsAddressing ModesIndexed Indexed Indexed Boolean IArithmeticImmediate Direct Extended (No Offset) (8-Bit Offset) (18-SitOlf9tt) OperationOP II - OP II - OP II - OP II - OP II - OP II -A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 06 3 5 M-AAE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 M~XB7 2 3 C7 3 4 F7 1 4 E7 2 4 07 3 5 A-MBF 2 3 CF 3 4 FF 1 4 EF 2 4 OF 3 5 X-MAB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 A+M-.AA9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 09 3 5 A+M+C~AAO 2 2 BO 2 3 CO 3 4 FO 1 3 EO 2 4 DO 3 5 A-M~AA2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 02 3 5 A-M-C~AA4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 04 3 5 A, M~AAA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5 A+M~AA8 2 2 88 2 3 C8 3 4 F8 1 3 E8 2 4 08 3 5 A+M-.AAl 2 2 81 2 3 Cl 3 4 Fl 1 3 El 2 4 01 3 5 A-MA3 2 2 83 2 3 C3 3 4 F3 1 3 E3 2 4 03 3 5 X-MA5 2 2 B5 2 3 C5 3 4 F5 j 3 E5 2 4 05 3 5 A·M8C 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 480 2 5 CD 3 6 FD 1 5 ED 2 5 DO 3 6ConditionCodeH I N Z CI• • r--~•• •• •• • •• • •• • •• •• •• • •• • • • •• • • • •IncrementDecrementClearComplementNegateOperations(2's Complement)Rotate left Thru CarryRotate Right Thru Carrylogical Shift leftlogical Shift RightArithmetic Shift RightArithmetic Shift leftTnt for Negativeor ZeroINCDECClRCOMNEGROlRORlSllSRASRASlTSTSymbols: Op· Operation# • Number of bytes- • Number of cyclesTable 6 Read/Modify/Write InstructionsAddressing ModesIndexed IndexedI MnemonicImplied(A) Implied(X) Direct (No Offset) (8·Bit Offset)IOP II - OP II - OP II - OP II - OP II -Booleanl Arithmetic Operation4C 1 2 5C 1 2 3C 2 5 7C 1 5 6C 2 6 A+l-~A or X+l~X or M+l~M4A 1 2 5A 1 2 3A 2 5 7A 1 5 6A 2 6 A-I ~A or X-l~X or M-l ~M4F 1 2 5FI 1 2 3F 2 5 7F 1 5 6F 2 6 OO~A or OO~X or OO~M43 1 2 53 1 2 33 2 5 73 1 5 63 2 6 A-A or x-X or M-MOO-A~A-or OO-X~X40 1 2 50 1 2 30 2 5 70 1 5 60 2 6 orOO-M~M49 1 2 59 1 2 39 2 5 79 1 5 69 2 6 AOfrrliL6t I II II I !sf]46 1 2 56 1 2 36 2 5 76 1 5 66 2 6L@:tC Ibo~IAHor:MI [c tI, bo4B 1 2 58 t 2 38 2 5 78 1 5 68 2 6[}-i I ~Of:lCr* I I t- o44 1 2 54 t 2 34 2 5 74 15 64 2 6 0,tI,I IAE~or:MI I!orO47 1 2 57 1 2 37 2 5 77 1 5 67 2 6[(j' -!o C:: IAt~"':MII 1-048 1 2 58 t 2 38 2 5 78 1 5 68 2 6 Equal to lSl40 t 2 50 1 2 3D 2 4 70 t 4 60 2 5 A-OO or x-oo or M-OOConditionCodeH I N Z C• "I,• 0 1 •• • , 1• • , 1\,• • " ,• •1\ /\ 1\/\• •/\ /\0• •/\ /\1\• •1\ 1\1\• •1\ 1\• • •1\ 1\_HITACHI417

HD6305XO,HD63A05XO,HD63B05XO---------------------------------------------Table 7 Branch InstructionsOperationsBranch AlwaysBranch NeverBranch IF HigherBranch IF lower or SameBranch IF Carry Clear(Branch IF Higher or Same)Branch IF Carry Set(Branch IF lower)Branch IF Not EqualBranch IF EqualBranch IF Half Carry ClearBranch IF Half Carry SetBranch IF PlusBranch IF MinusBranch IF Interrupt MaskBit is ClearBranch IF Interrupt MaskBit is SetBranch IF Interrupt Lineis lwBranch IF Interrupt Lineis HighBranch to SubroutineSymbols: Op = Operation# = Number of bytes- = Number of cyclesMnemonicBRABRNBHIBlSBCC(BHS)BCS(BlO)BNEBEQBHCCBHCSBPlBMIBMCBMSBilBIHBSRAddressing ModesRelativeOP # -20 2 3 None21 2 3 None22 2 3 C+Z=O23 2 3 C+Z=124 2 3 C=O24 2 3 C=O25 2 3 C=125 2 3 C=126 2 3 z=o27 2 3 Z=128 2 3 H=O29 2 3 H=12A 2 3 N=O2B 2 3 N=l2C 2 3 1=020 2 3 1=12E 2 3 INT=O2F 2 3 INT=1AD 2 5 --Branch TestCondition CodeH I N Z C• • • • •• • • • •• • • • •• • • • •• • • • •. Table 8 Bit Manipulation InstructionsOperationsMnemonicBranch IF Bit n is set BRSET n(n=0···7)Branch IF Bit n is clear BRClR n(n=0 .. ·7)Set B~t n BSET n(n=0 ..·7)Clear Bit n BClR n(n =0 .. ·7)Symbols: Op = Operation# = Number of bytes- = Number of cyclesAddressing ModesBoolean/Bit Set/Clear Bit Test and Branch ArithmeticOP # - OP # -Operation- .-.-2·n 3 5 --- - - 01+2·n 3 5 -10+2·n 2 5 -- - -- 1---Mn11 +2·n 2 5 -'- -- - O---MnBranchTestCondition CodeH I N Z CMn=1• • • • 1\Mn=O• • • • 1\-• • • • •-• • • • •418~HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XOTable 9Control InstructionsAddressing ModesOperations Mnemonic Implied Boolean OperationCondition CodeOP # - H I N Z CTransfer A to X TAX 97 1. 2 A ...... X• • • • •Transfer X to A TXA 9F 1 2 X ...... A• • • • •Set Carry Bit SEC 99 1 1 1 ...... C• • • • 1Clear Carry Bit CLC 98 1 1 O-C • 0Set Interrupt Mask Bit SEI 9B 1 2 1-1 1 Clear Interrupt Mlask Bit CLI 9A 1 2 0-1 0 Software Interrupt SWI 83 1 10 1 Return from Subroutine RTS 81 1 5• • • • •Return from Interrupt RTI 80 1 8 ? ? ? ? ?Reset Stack Pointer RSP 9C 1 2 $FF-SP No-Operation NOP 90 1 1 Advance Prog. Cntr. Only • • •Decimal Adjust A OAA 80 1 Converts binary add of BCD charcters into2 BCD format /\ /\ /\*Stop STOP 8E 1 4 Wait WAIT 8F 1 4• • • • •Symbols: Op = Operation# = Number of bytes- = Number of cycles* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)Table 10 Instruction Set (in Alphabetical Order)MnemonicADCADDANDASLASRBCCBClRBCSBEQBHCCBHCSBHI(BHS)BIHBilBIT(BlO)BlSBMCBMIBMSBNEBPLBRAImpliedxxImmediatexxxCondition Code Symbols:H Half Carry (From Bit 3) CI Interrupt Mask/\N Negative (Sign Bit)•Z Zero ?XAddressing ModesIndexed IndexedDirect Extended Relative (No Offset) (S-Bit)x x x xx x xXx x xXxXXXXXXXXxXXxX X XXXXXXXxXx.Carry/BorrowTest and Set if True, Cleared OtherwiseNot AffectedLoad CC Register From StackXXIndexed(16-Bit)XXxXCondition CodeBit BitSet! Test &Clear Branch H I N Z C1\ 1\ 1\ 1\/\ /\ /\ /\•X•/\ /\ /\ /\ /\/\ /\ /\• • /\ /\ • • • • •• • • • •(to be continued)_HITACHI419

HD6305XO,HD63A05XO,HD63B05XO----------------------Table 10 Instruction Set (in Alphabetical Order)MnemonicImplied ImmediateBRNBRCLRBRSETBSETBSRCLCXCLIXCtRXCMPXCOMXCPXXDAAXDECXEORXINCXJMPJSRLOAXLOXXLSLXLSRXNEGXNOPxORAXROLxRORxRSPxRTIXRTSxSBCxSECXSEIxSTASTOPxSTXSUBxSWIXTAXXTSTXTXAXWAITXCondition Code Svmbols:H Half Carry (From Bit 3) CI Interrupt Mask1\N Negative (Sign Bit)•Z ZeroDirectXAddressing ModesX X XXX X XXX X XXX X XX X XX X XX X XXXXx x xxxxxx X xX X xx X XX X XXIndexed IndexedExtended Relative (No Offset) (S-Bit)XCarry /BorrowTest and Set if True, Cleared OtherwiseNot AffectedLoad CC Register From StackXXXXXXXXXXXXXX"XXXXXXXXXxxxxXXXXIndexed(18-Bit)XXXXXXXxxxXXBitSetlBitTest &Condition CodeClear Branch H I N Z C• • • • •X• • • • 1\XX 1\•• 00 • • 0 1 •1\ 1\ 1\1\ 1\ 11\ 1\ 1\1\ 1\ 1\1\ /\ 1\ 1\ ,\ 1\ • • 1\ 1\ •/\ /\ /\ /\ 1\0 1\ /\/\ ,\ ,\• • •1\ /\ 1\ /\ /\1\ /\ /\• • • • •? ? ? ? ?• • •/\ /\ /\• 11 • • • 1\ 1\ • •• 1\ /\ 1\ 1\ 1\1• • 1\ /\ • • • • •420eHITACHI

---------------------------------------------HD6305XO,HD63A05XO,HD63B05XOTable 11Operation Code MapBit Manipulation Branch Read Modify Write Control Register MemoryTest & Set/Branch Clear Rei OIR A X ,Xl .XO IMP IMP IMM OIR EXT .X2 .Xl .XO0 1 2 3 4 5 6 7 8 9 A B C D E F --;-H0 BRSETO BSETO BRA NEG RTI" SUB 01 BRClRO BClRO BRN RTS" CMP 12 BRSETl BSET1 BHI SBC 23 BRClR1 BClR1 BlS COM SWI" CPX 34 BRSET2 BSET2 BCC lSR AND 45 BRClR2 BClR2 BCS BIT 56 BRSET3 BSET3 BNE ROR lOA 67 BRClR3 BClR3 BEQ ASR TAX" STA 5TA(+11 78 BRSET4 BSET4 BHCC lSl ASl ClC EOR 89 BRClR4 BClR4 BHCS ROl SEC AOC 9A BRSET5 BSET5 BPl DEC CLI* ORA AB BRClR5 BClR5 BMI SEI* ADD B-C BRSET6 BSET6 BMC INC RSP" JMP(-l) C0 BRClR6 BClR6 BMS T5TI-I) TST TST(-l) OAA" NOP BSR" JSR(+2) JSR(+l) JSR(+2) 0E BRSET7 BSET7 Bil STOP' - lOX EF BRClR7 BClR7 BIH ClR WAIT' TXA" STX 5TX(+11 F3/5 2/5 2/3 2 5 1 2 I 12 2 6 1 5 1 " 1 1 2.'2 2.3 3/4 3/5 2/4 1 / 3IGHloW(NOTES)I. "-" is an undefined operation code.2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).The number of cycles for the mnemonics asterisked (*) is as follows:RTI 8 TAX 2RTS 5 RSP 2SWI 10 TXA 2DAA 2 BSR 5srop 4 ~I 2WAIT 4 SEI 23. The parenthesized numbers must be added to the cycle count of the particular instruction.• Additional InstructionsThe following new instructions are used on the HD6305XO:DAA Converts the contents of the accumulator into BCDcode.WAIT Causes the MCU to enter the wait mode. For this mode,see the topic, Wait Mode.STOP Causes the MCU to enter the stop mode. For this mode,see the topic, Stop Mode._HITACHI 421

HD6305X1 ,HD63A05X1 ,HD63B05X1H D6305X2, H D63A05X2, H D63B05X2CMOS MCU (Microcomputer Unit)The HD6305XI and the HD6305X2 are CMOS versions ofthe HD6805XI and. the HD6805X2, which are NMOS 8·bitsingle chip microcomputers. A CPU, a clock generator, a 128-byte RAM, I/O terminals, two timers and a serial communicationinterface (SCI) are built in both chip of the HD6305Xland the HD6305X2. Their memory spaces are expandable to16k bytes externally.The HD6305XI and the HD6305X2 have the same functionsas the HD6305XO's except for the number of I/O terminals.The HD6305X 1 has a 4k byte ROM and its memory space isexpandable to 12k bytes externally. The HD630SX2 is a microcomputerunit which includes no ROM and its memory spaceis expandable to 16k bytes externally.• HARDWA~E FEATURES.8·bit based MCU.4k·bytes of internal ROM (HD6305Xl)No internal ROM (HD6305X2)• 128·bytes of RAM• A total of 31·terminals, including 24 I/O's, 7 inputs• Two timers- 8·bit timer with a 7·bit prescaler (programmable prescaler;event counter)- 15·bit timer (commonly used with the SCI clock divider)• On-chip serial interface circuit (synchronized with clock).Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation modes- Wait .... In this mode, the clock oscillator is on and theCPU halts but the timer/serial/interrupt func·tion is operatable.- Stop .... In this mode, the clock stops but the RAMdata, I/O status and registers are held.- Standby .. In this mode, the clock stops, the RAM datais held, and the other internal condition isreset.• Minimum instruction cycle time- HD6305Xl/X2 .. 11ls (f = 1 MHz)- HD63A05Xl/X2 .. 0.671ls (f = 1.5 MHz)- HD63805Xl/X2 .. 0.51ls (f = 2 MHz)• Wide operating rangeVce = 3 to 6V (f = 0.1 to 0.5 MHz)- HD6305Xl/X2 .. f = 0.1 to 1 MHz (VCC = 5V ± l()o~)- HD63A05Xl/X2 .. f = 0.1 to 1.5 MHz (VCC = 5V ± l()o~)- HD63805Xl/X2 .. f = 0.1 to 2 MHz (VCC = 5V ± l()O~).System development fully supported by an evaluation kitHD6305X1P, HD63A05X1P,HD63805X1P, HD6305X2P,HD63A05X2P, HD63805X2PH D6305X 1 F, H D63A05X 1 F,HD63805X1F, HD6305X2F,HD63A05X2F, HD63805X2F• SOFTWARE FEATURES(FP·64}-PRELIMINARY-.Similar to HD6800• Byte efficient instruction set• Powerful bit manipulation instructions (8it Set, Bit Clear, and8it Test and 8ranch usable for all RAM bits and all I/O termi·nals)• A variety of interrupt operations• Index addressing mode useful for table processing• A variety of conditional branch instructions• Ten powerful addressing modes.Ail addressing modes adaptable to RAM, and I/O instructions• Three new instructions, STOP, WAIT and DAA, added to theHD6805 family instruction set• Instructions that are upwar-d compatible with those of Moto·rola's MC6805P2 and MCl46805G2422 $ HITACHI

HD6305X1,HD6305X2• PIN ARRANGEMENT• HD6305X1P, HD63A05X1P, HD63B05X1P, HD6305X2P,H D63A05X2P, H D63B05X2P• HD6305X1F, HD63A05X1F, HD63B05X1F, HD6305X2F,HD63A05X2F,H063B05X2FVs~~ 0REs'CINTSTBy FXTALEXTALNUMTIMERA7A,A,A.A,A2A,AoB7B,8,B.B3B2B,BoC7/T.C,/RxC,/CKC.C3C 2C,Co~ ______________ .- Vee(Top View)DATAoDATA,DATA 2DATA,DATA.DATA,DATA,DATA 7ER/WADR"ADR12ADR"ADR,oADA,ADR,ADR7ADR,ADR,ADR.ADR,ADR2ADR,ADRo07D,/iN'f;0,D.03020,C7/TxC6 /Rx~ ..U.. U U U0 u u u 0 0 0 0>(Top View)isI~051 DATAsDATA 7ER/WADR'3ADR'2ADR"ADR,OADR gADReADR1ADR6ADR~ADR.ADR3ADR2ADR,ADRo01• BLOCK DIAGRAMXTAl EXTAl E RliiTIMERPoftA110TerminalsPoft B1/0TerminalsIndexe Register xCondition CodeRegisterccStack6 Pointer spProgramCounter6 "High" PCHCPUCPUControlD,D .... iNT,D,D. Port 003 Inputg~ Terminals" No internal ROM in H06305X2OATA7DATA.DATA,DATA.DATA]OATA1DATAlDAT-'o~HITACHI423

-HD6305X1,HD6305X2-------------------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee -0.3-+7.0 VInput Voltage Vin -0.3 - Vee + 0.3 VOperating Temperature Topr 0-+70 °cStorage Temperature Tstg -55 - +150 °c[NOTE)These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normaloperation, we recommended Vln, Vout; Vss ~ IV ln or Vout) ~ Vee.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee· 5.0V±10%. Vss· OV. T. • 0 - +70°C. unleu otherwise noted.)Input "High" VoltageInput "Low" VoltageItemRES,STBYEXTALOther InputsAll InputsOutput "High" Voltage All OutputsOutput "Low" Voltage All OutputsInput Leakage CurrentThree-state CurrentCurrent Dissipation··Input CapacitanceTIMER,INT,0 1 - D"STBYAo - A" Bo - B"C 41- C" ADRo - ADR13·,E , RM·OperatingWaitStopStandbyAll Terminals• Only at standby•• VIH min'"' Vee-1.0V, VIL max'"' O.8V••• The value at f = xMHz is given by using.IcC If = xMHz) = Icc If = 1MHzI )C xSymbol Test Condition minV IHVee-0.5VeexO.72.0V IL -0.3VOHIOH = -200llA 2.4IOH = -101lAVee-0.7VOL IOL = 1.6mA -!lId -Vin = 0.5 - Vee-0.5IITSII ---Icc f = 1MHz···--Cin f = 1MHz, Vin = OV -typ max Unit- Vee+0.3- Vee+0 .3 V- Vee+0.3- 0.8 V- -V- -- 0.55 V- 1.0 IlA- 1.0 IlA5 10 mA2 5 mA2 10 IlA2 10 IlA- 12 pF• AC CHARACTERISTICS (Vee = 5.0V ±10%, Vss = OV, T.· 0 - +70°C, unless otherwise noted.)ItemSymbolTest HD6305X 1/X2 HD63A05X1/X2Condition min typ max min typ maxCycle Time tcvc 1 - 10 0.666 - 1020 - - 20Enable Rise Time tEr~Enable Fall Time tEf - - 20 - - 20Enable Pulse Width("High" Level) PWEH 450 - - 300 - -Enable Pulse Width ("Low" Level) PWEL 450 - - 300 - -Address Delay Time tAD Fig. 1 - - 250 - - 190Address Hold Time tAH 20 - - 20 - -Data Delay Time tow - - 250 - - 160Data Hold Time (Write) tHW 20 - - 20 - -Data Set-up Time (Read) tOSR 80 - - 60 - -Data Hold Time (Read) tHR 0 - - 0 - -HD63B05X 1 /X2min typ maxUnit0.5 - 10 #AS- - 20 ns- - 20 ns220 - - ns220 - - ns- - TBD ns20 - - ns- - TBD ns20 - - nsTBD - - ns0 - - ns424 _HITACHI

-------------------------------------------------------HD6305X1,HD6305X2• PORT TIMING (VCC=5.0V±10%, VSS=OV, Ta=O-+70°C,unlessotherwisenoted.)ItemSymbolTest HD6305X 1/X2 H D63A05X 1/X2 HD63B05X1/X2ConditionUnitmin typ max min typ max min typ maxPort Data Set-up Time(Port A, B, C, D)tpDS 200 - - 200 - - 200 - - nsFig. 2Port Data Hold Time(Port A, S, C, D) tpDH 200 - - 200 - - 200 - - nsPort Data Delay Time(Port A, S, C)tpDw Fig. 3 - - 300 - - 300 - - 300 ns• CONTROL SIGNAL TIMING (Vee = 5.0V±10%, Vss = OV, T8 = 0 - +70°C, unless otherwise noted.)INTPuise WidthItemINT2 Pulse WidthSymboltlWLt'WL2Test HD6305X1/X2 HD63A05X1/X2 HD63B05X1/X2Condition min typ max min typ max min typ maxtcyc- -tcycUnit- -tcyc- - ns+250 +200 +200tcyctcyCtcyc+250- - +200 - - +200 - - nsRES Pulse Width tRWL 5 - - 5 - - 5 - - tcvcControl Set-up Time tcs Fig. 5 250 - - 250 - - 250 - - nsTimer Pulse WidthtTWLtcyc-tcyc tcyc+250 - - -+200 +200- - nsOscillation Start Time (Crystal) tose Fig.5.Fig.20· - - 20 - - 20 - - 20 msReset Delay Time tRHL Fig. 19 80 - - 80 - - 80 - - ms• C L = 22pF ±20%, Rs = 600 max.• SCI TIMING (Vee = 5.0V±10%, VSS= OV, Ta = 0"'" +70°C, unless otherwise noted.)ItemSymbolTest HD6305X1/X2 HD63A05Xl/X2 HD63B05Xl/X2Condition min typ max min typ max min typ maxClock Cycle tScyc 1 - 32768 0.67 - 21845 0.5 - 16384 IlSData Output Delay Time tTXD Fig. 6, - - 250 - - 250 - - 250 nsData Set-up Time tSRX Fig. 7 200 - - 200 - - 200 - - nsData Hold Time tHRX 100 - - 100 - - 100 - - nsUnit~HITACHI 425

HD6305X1,HD6305X2------------------------------------______________ __E.... ---------tcvc----------..I\100011----PWEL---~J!4----PWeHI-----..IterAo-A13R/W2.4VO.6VAddress ValidMCU Write00-07towMCU Read00-07Figure 1 Bus TimingEEPortA.B.C.oPortA.B.C2.4V DataO.6V ValidFigure 2 Port Data Set-up and Hold Times(MCU Read)Figure 3 Port Data Delay Time (MCU Write)InterruptTestEAddressBusData BusR/WOpCodeOperand IrrelevantOp Code DataPCo­PC7\~------------~IFigure 4 Interrupt SequenceVector Vector First Inst. of~::.ess~~:ress Interrupt Routine426_HITACHI

-----------------------------------------------------HD6305Xl.HD6305X2EVee=:=-u-1~.~ toseSi'Bv-Address--BusRiWIVee-O.SV____ ~--~ __ ----~,---~~~~enun­~tose]~~Verl-O.5VRES--I '--, ----Data Bus';:=r-&llllll/$1FFF 1FFF New PC 1FFF_~I----------------~I~~$ffjfh}____FigureS Reset TimingClock OutputC5/CKtscyC2.4VO.6VData OutputC7/TXtSRXData InputCa/Rx2.0VO.BVFigure6 SCI Timing (Internal Clock)tscyCClock InputC5/CK2.0VO.8VData OutputC7/TXData InputC6/RX2.0VO.8VFigure7 SCI Timing(External Clock)_HITACHI 427

HD6305Xl,HD6305X2-------------------------------------------------------TTL load(Port)Test pointterminal2.4kQIOl=1.6mAo----4~--...... --*"--1'90pF12kQVee[NOTES J 1. The load capacitance includes stary capacitance causedby the probe, etc.2. All diodes are 1 S2074 ® .Figure 8 Test Load- DESCRIPTION OF TERMINAL FUNCTIONSThe input and output signals of the MCU are describedhere..Vee, VssVoltage is applied to the MCU through these two terminals.Vee is 5.0V ± 10%, while Vss is grounded..INT,INT2External interrupt request inputs to the MCU. For details,refer to "INTERRUPT". The INT2 terminal is also used asthe port D6 terminal.• XTAL, EXTALThese terminals provide input to the on-chip clock circuit.A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramicfilter is connected to the terminal. Refer to "INTERNALOSCILLATOR" for using these input terminals.• TIMERThis is an input terminal for event counter. Refer to"TIMER" for details..RESUsed to reset the MCU. Refer to "RESET" for details..NUMThis terminal is not for user application. In case of theHD6305XI, this terminal should be connected to Veethrough iOkU resistance. In case of the HD6305X2, thisterminal should be connected to Vss·• Enable (E)This output terminal supplies E clock. Output is a singlephase,TTL compatible and 1/4 crystal oscillation frequencyor 1/4 external clock frequency. It can drive one TTL loadand a 90pF condenser .• Data Bus (DATAo '" DATA,)This TTL compatible three-state buffer can drive one TTLload and 90pF.• Address Bus (ADRo '" ADR 13)Each terminal is TTL compatible and can drive one TTLload and 90pF.• Input/Output Terminals (Ao '" A, • Bo '" B,. Co '" C,)These 24 terminals consist of four 8-bit I/O ports (A, B, C).Each of them can be used as an input or output terminal ona bit through program control of the data direction register.For details, refer to "I/O PORTS."• Input Terminals (01 '" 0,)These seven input-only terminals are TTL or CMOS compatible.Of the port D's, D6 is also used as INT2. If D6 isused as a port, the INIl interrupt mask bit of the miscellaneousregister must be set to "I" to prevent an INT2 interruptfrom being aCCidentally accepted .• STBYThis terminal is used to place the MCU into the standbymode. With STBY at "Low" level, the oscillation stops andthe internal condition is reset. For details, refer to "StandbyMode."The terminals described in the following are I/O pins forserial communication interface (SCI). They are also used asports C s , C 6 and C,. For details, refer to "SERIAL COM­MUNICATION INTERFACE.".CK (Cs)Used to input or output clocks for serial operation ..Rx (C6)Used to receive serial data..Tx (C,)Used to transmit serial data .-MEMORY MAPThe memory map of the MCU is shown in Fig. 9. $1000""$IFFF of the HD6305X2 are external addresses. However,care should be taken to assign vector addresses to $lFF6 ...,$IFFF. During interrupt processing, the contents of the CPUregisters are saved into the stack in the sequence shown inFig. 10. This saving begins with the lower byte (PCL) of theprogram counter. Then the value of the stack pointer isdecremented and the higher byte (PCH) of the programcounter, index register (X), accumulator (A) and conditioncode register (CC) are stacked in that order. In a subroutinecall, only the contents of the program counter (PCH and peL)are stacked.• Read/Write (R/W)This TTt compatible output Signal indicates to peripheraland memory devices whether MCU is in Read ("High"), orin Write ("Low"). The normal standby state is Read ("High").Its output can drive one TTL load and a 90pF condenser.428 ~ HITACHI

-------------------------------------------------------HD6305X1,HD6305X2012712 B2552564095409t8188191 Ve81921638 3PushI/O PortsTimerSCIRAM(12BBytes)StackExternalMemory SpaceROM'(4,096Bytes)2 -~n!i~~~~t-.-ExternalMemory Space1$0000 0 PORT A1 PORT B2 PORT C3 PORT 0S007F~~080$O~F4 PORT A DDR5 PORT B DDR6 PORT C DDRNot Used$gOFF$ 100 B Timer Data Reg9 Timer CTRl Reg10 Mlsc Reg5100\6SCI$lFF6Sl FFF$2000$3FFFNot UsedCTRl Reg17 SCI STS Reg18 SCI Data Reg31Not Used32 External12~~ Memory SpaceSOO$01S02$03"$04"$05"$06"$08$09$OA$10$11$12$lF$20$7F* Write only reg ister.. Read only reg ister• ROM area ($1000 - $1 FFF) in the HD6305X2is changed into External Memory Space.Figure 9 Memory Map of MCU7 6 543 2 1 0I n-4 1 1 1 Condition n+lCode Registern-3 Accumulator n+2n-2 Index Register n+3n-l 1 11 PCH" n+4n PCl" n+5Pull• In a subroutine call, only PCl and PCH are stacked.Figure 10 Sequence of Interrupt Stacking-REGISTERSThere are five registers which the programmer can operate.7 oI1..-_______ A --11 Accumulator7 oI X I indexL-_______ ....... Register13 oI '--_____________ PC --'. I Counter:rogram13 6 5 0I ~0_Llo~lo~l~o~lo~lo~l~l~l-l~I ____ s-p ____ ~1~~~~r...-...,..........--.---r...... ConditionCode'-r....,-..,~...,......"T-' Register~gg~~Zero'-----Negative'------InterruptMask'-------HalfCarryFigure 11 Programming Modele Accumulator (A)This accumulator is an ordinary 8-bit register which holdsoperands or the result of arithmetic operation or data processing.elndex Register (X)The index register is an 8-bit register, and is used for indexaddressing mode. Each of the addresses contained in theregister consists of 8 bits which, combined with an offsetvalue, provides an effective address.In the case of a read/modify/write instruction, the indexregister can be used like an accumulator to hold operationdata or the result of operation.If not used in the index addressing mode, the register canbe used to store data temporarily._ Program Counter (PC)The program counter is a 14-bit register that contains theaddress of the next instruction to be executed.- Stack Pointer (SP)The stack pointer is a 14-bit register that indicates the addressof the next stacking space. Just after reset, the stackpointer is set at address SOOFF. It is decremented when datais pushed, and incremented when pulled. The upper 8 bitsof the stack pointer are fixed to 00000011. During the MCUbeing reset or during a reset stack. pointer (RSP) instruction,the pointer is set to addresS SOOFF. Since a subroutine orinterrupt can use space up to address SOOC1 for stacking, thesubroutine can be used up to 31 levels and the interrupt upto 12 levels.-Condition Code Register (CC)The condition code register is a 5-bit register, each bitindicating the result of the instruction just executed. Thebits can be indiVidually tested by conditional branch instruc-_ HITACHI 429

HD6305X1,HD6305X2----------------------------------------------____ __tions. The CC bits are as follows:Half Carry (H): Used to indicate that a carry occurred betweenbits 3 and 4 during an arithmetic operation(ADD, ADC).Interrupt (I): Setting this bit causes all interrupts, excepta software interrupt, to be masked. If aninterrupt occurs with the bit I set, it islatched. It will be processed the instantthe interrupt mask bit is reset. (More specifically,it will enter the interrupt processingroutine after the instruction following theCLI has been executed.)Negative (N): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is negative (bit 7 is logic"I").Zero (Z): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is zero.Carry! Represents a carry or borrow that occurredBorrow (C): in the most recent arithmetic operation. Thisbit is also affected by the Bit Test and Branchinstruction and a Rotate instruction.-INTERRUPTThere are six different types of interrupt: external.interrupts(00,. IN.T2), internal timer interrupts (TIMER,TIMER2), senal mterrupt (S.CI) and interrupt by an instruction(SWI).Of these six interrupts, the INT2 and TIMER or the SCIand TIMER2 generate the same vector address, respectively.When an interrupt occurs, the program in progress stopsand the then CPU status is saved onto the stack. And then,the interrupt mask bit (I) of the condition code register isset and the start address of the interrupt processing routineis obtained from a particular interrupt vector address. Thenthe interrupt routine starts from the start address. Systemcan exit from the interrupt routine by an RTI instruction.When this instruction is executed, the CPU status beforethe interrupt (saved onto the stack) is pulled and the CPUrestarts the sequence with the instruction next to the one atwhich the interrupt occurred. Table I Usts the priority ofinttrrupts and their vector addresses.Table 1Priority of InterruptsInterrupt Priority Vector AddressRES 1 SlFFE, $lFFFSWI 2 $lFFC, $lFFDINT 3 $lFFA, $lFFBTIMERIINT2 4 $lFFS, $lFF9SCI/TIMER2 5 SlFFS, SlFF7A flowchart of the interrupt sequence is shown in Fig. 12.A block diagram of the interrupt request source is shown inFig. 13. ,--------.y !NT1--1SFF--SPO--OOR'sCLR INT LogicSFF--TDRS7F--Timer PrescalerS50--TCRS3F--SSRSOO--SCRS7F ..... MRyTIMERY SCIFigure 12 Interrupt Flow Chart430 Cf)HITACHI

------------------------------------------~-----------HD6305X1,HD6305X2In the block diagram, both the external interrupts INT andINTi are edge trigger inputs. At the faUing edge of each input,an interrupt request is generated and latched. The INT interruptrequest is automatically cleared if jumping is made tothe iNf processing routine. Meanwhile, the INT2 request iscleared if ''0'' is written in bit 7 of the misceUaneol. .:gister.For the external interrupts (INT, INT2), internal timerinterrupts (TIMER, TIMER2) and serial interrupt (SCI), eachinterrupt request is held, but not processed, if the I bit of thecondition code register is set. Immediately after the I bit iscleared, the corresponding interrupt processing starts accordingto th~ority.The INT2 interrupt can be masked by setting bit 6 of themiscellaneous register; the TIMER interrupt by setting bit 6of the timer control register; the SCI interrupt by setting bitS of the serial status register; and the TIMERz interrupt bysetting bit 4 of the serial status register.The status of the 00 terminal can be tested by a BIL orBIH instruction. The INT falling edge detector circuit andits latching circuit are independent of testing by these instructions.This is also true with the status of the INTi terminal.-Miscellaneous Register (MR; $OOOA)The interrupt vector address for the external interruptINT2 is the same as that for the TIMER interrupt, as shownin Table 1. For this reason, a special register called the miscellaneousregister (MR; SOOOA) is available to control theINTi interrupts.Bit 7 of this register is the INTi interrupt request flag.When the fa1ling edge is detected at the INT2 terminal, "I"is set in bit 7. Then the software in the interrupt routine(vector addresses: SIFF8, $IFF9) checks bit 7 to see if itis INT2 interrupt. Bit 7 can be reset by software.Miscellaneous Register (MR;$OOOA)76543210IMR~MR6IZ1Z1Z1Z1ZJZIf --INT2 Interrupt MaskIl..... __________ INTl Interrupt Request FlagMiscellaneous Register (MR; SOOOA)Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",then the INT2 interrupt is disabled. Both read and write arepossible with bit 7 but "I" cannot be written in this bit bysoftware. This means that an interrupt request by softwareis impossible.When reset, bit 7 is cleared to "0" and bit 6 is set to "1".-TIMERFigure 14 shows a MCU timer block diagram. The timerdata register is loaded by software and, upon receipt of aclock input, begins to count down. When the timer dataBIH/BIL TestIVectoringgenerated$1 FFA, $1 FFBCondition Code Register (CC)Falling Edge Detector,INTTIMER~~~+---- Vectoring generated$1FF8,$1FF9SCI/TIMER2Serial StatusRegister (SSR)~----41~-- Vectoring generated$1FF6,$1FF7Figur~ 13 Interrupt Request Generation Circuitry$ HITACHI 431

HD6305X1,HD6305X2----------------------------------------------------register (TDR) becomes "0", the timer interrupt requestbit (bit 7) in the timer control register is set. In response tothe interrupt request, the CPU saves its status into 'the stackand fetches timer interrupt routine address from addressesSlFF8 and $lFF9 and execute the interrupt routine. Thetimer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the timer control register. The mask bit(I) in the condition code register can also mask the timerinterrupt.The source clock to the timer can be either an externalsignal from the timer input terminal or the internal E signal(the oscillator clock divided by 4). If the E signal is used asthe source, the clock input can be gated by the input to thetimer input terminal.Once the timer count has reached "0", it starts countingdown with "SFF". The count can be monitored wheneverdesired by reading the timer data register. This permits theprogram to know the length of time having passed after theoccurrence of a timer interrupt, without disturbing the contentsof the counter.When the MCU is reset, both the prescaler and counter areinitialized to logic "1". The timer interrupt request bit(bit 7) then is cleared and the timer interrupt mask bit (bit6) is set.To clear the timer interrupt request bit (bit 7), it is necessaryto write "0" in that bit.TCR7oTCR6oTimer·interrupt requestAbsentPresentTimer interrupt maskEnabledDisabled• Timer Control Register (TCR; $0(09)Selection of a clock source, selection of a prescaler frequencydivision ratio, and a timer interrupt can be controlledby the timer control register (TCR; $0009).For the selection of a clock source, anyone of the fourmodes (see Table 2) can be selected by bits 5 and 4 of thetimer control register (TCR).Timer Control Register (TCR; $0009)L Prescaler division rltio selectionPrescaler initialize1..-________ Clock input source1...-__________ Timer interrupt mask'---------------Timer interrupt requestAfter reset, the TCR is initialized to "E under timer terminalcontrol" (bit 5 = 0, bit 4 = 1). If the timer terminal is"1", the counter starts counting down with "$FF" immediatelyafter reset.When "1" is written in bit 3, the prescaler is initialized.This bit always shows "0" when read.Bit5TCRTable 2Bit4Clock Source Selection0 0 Internal clock EClock input source0 1 E under timer terminal control1 0 No clOGk input (counting stopped)1 1 Event input from timer terminalInitialize(InternalClock)E --+-, ~3.... ___ ---..... ----' Timer InterruptWriteReadFigure 14 Timer Block Diagram432 _HITACHI

-------------------------------------------------------HD6305Xl,HD6305X2A prescaler division ratio is selected by the combination ofthree bits (bits 0, 1 and 2) of the timer control register (seeTable 3). There are eight different division ratios: +1, +2, +4,+8, +16, +32, +64 and +128. After reset, the TCR is set to the+1 mode.Table 3TCRBit 2 Bit 1 Bit 0Prescaler Division Ratio SelectionPrescaler division ratio0 0 0 +1,0 0 1 +20 1 0 +40 1 1 +8A timer interrupt is enabled when the timer interrupt maskbit is "0", and disabled when the bit is "1". When a timerinterrupt occurs, "1" is set in the timer interrupt request bit.This bit can be cleared by writing "0" in that bit.-SERIAL COMMUNICATION INTERFACE (SCI)This interface is used for serial transmission or receptionof 8-bit data. Sixteen transfer rates are available in the rangefrom 1 jJ.S to approx. 32 ms (for oscillation at 4 MHz).The SCI consists of three registers, one eighth counter andone prescaier. (See Fig. 15.) SCI communicates with the CPUvia the data bus, and with the outside world through bits 5,6 and 7 of port C. Described below are the operations ofeach register and data transfer.-SCI Control Register (SCR; $0010)1 0 0 +161 0 1 +321 1 0 +641 1 1 +128SCI Control Registers (SCR; 0010)r--~--'C5(CK) :IIIIIIIIC6(Rx) :-----.IC7(Tx)SCI Data Registers L....-L,.l---'(SOR: $0012) .... _________ ~'--_.....1-_,......1L ______ r---~=r~~~~~~~~~~~~~~~~~~~~~~==~--~SCI Status Registers(SSR :$0011 )TransferClockGeneratorInitializeNot UsedSCI/TIMER2Figure 15 SCI Block Diagram~HITACHI433

HD6305X1,HD6305X2-------------------------------------------------------SCR7oC, terminalUsed as I/O terminal (by DOR).Serial data output (DDR output)Bit 7 (SSR7)Bit 7 is the SCI interrupt request bit which is set uponcompletion of transmitting or receiving 8-bit data. It iscleared when reset or data is written to or read from theSCI data register with the SCRS="I". The bit can also becleared by writing "0" in it.SCR6oC 6 terminalUsed as I/O terminal (by DDR).Serial data input (DDR input)SCR5 SCR4 Clock source C 5 terminal0 0 - Used as I/O terminal (by0 1 -DDR).1 0 Internal Clock output (DDR output)1 1 External' Clock input (DDR input)Bit 7 (SCR7)When this bit is set, the DDR corresponding to the C,becomes" 1" and this terminal serves for output of SCI data.After reset, the bit is cleared to "0".Bit 6 (SCR6)When this bit is set, the DDR corresponding to the C 6becomes "0" and this terminal serves for input of SCI data.After reset, the bit is cleared to "0".Bits 5 and 4 (SCR5, SCR4)These bits are used to select a clock source. After reset,the bits are cleared to "0".Bit 6 (SSR6)Bit 6 is the TIMER2 interrupt request bit. TIMER2 is usedcommonly with the serial clock generator, and SSR6 is seteach time the internal transfer clock falls. When reset, thebit is cleared. It also be cleared by writing "0" in it. (Fordetails, see TIMER2.)Bit 5 (SSRS)Bit 5 is the SCI interrupt mask bit which can be set orcleared by software. When it is "I", the SCI interrupt (SSR7)is masked. When reset, it is set to "I".Bit 4 (SSR4)Bit 4 is the TIMER2 interrupt mask bit which can be setor cleared by software. When the bit is "I", the TIMER2interrupt (SSR6) is masked. When reset, it is set to "1".Bit 3 (SSR3)When "I" is written in this bit, the prescaler of the transferclock generator is initialized. When read, the bit always is "0".Bits 2-0Not used.SSR7oSCI interrupt requestAbsentPresentBits 3 - 0 (SCR3 - SCRO)These bits are used to select a transfer clock rate. Mterreset, the bits are cleared to "0".SCR3 SCR2 SCR1 SCROTransfer clock rate4.00 MHz 4.194 MHz0 0 0 0 1 I1s 0.9511s0 0 0 1 211s 1.9111S0 0 1 0 411s 3.8211s0 0 1 1 Bl1s 7.6411S1 1 l l l l1 1 1 1 3276811s 1/32 sSSR6oSSR5oSSR4oTIMER2 interrupt requestAbsentPresentSCI interrupt maskEnabledDisabledTIMER2 interrupt maskEnabledDisabled• Data Transmission-SCI Data Register (SDR; $0012)By writing the desired control bits into the SCI controlA serial-parallel conversion register that is used for transferregisters, a transfer rate and a source of transfer clock areof data.determined and bits 7 and 5 of port C are set at the serialdata output terminal and the serial clock terminal, respectively.The transmit data should be stored from the accumu­-SCI Status Register (SSR; $0011)76543210lator or index register into the SCI data register. The datawritten in the SCI data register is output from the C,fTxterminal, starting with the LSB, synchronously with thefalling edge of the serial clock. (See Fig. 16.) When 8 bit of434~HITACHI

---------------------------------------------------------HD6305Xl,HD6305X2data have been transmitted, the interrupt request bit is set inbit 7 of the SCI status register with the rising edge of the lastserial clock. This request can be masked by setting bit 5 of theSCI status register. Once the data has been sent, the 8th bitdata (MSB) stays at the C7/Tx terminal. If an external clocksource has been selected, the transfer rate determined bybits 0 - 3 of the SCI control register is ignored, and the Cs /CK terminal is set as input. If the internal clock has beenselected, the Cs/CK terminal is set as output and clocks areoutpu t at the transfer rate selected by bits 0 - 3 of the SCIcontrol register.Figure 16 SCI Timing Chart• Data ReceptionBy writing the desired control bits into the SCI controlregister, a transfer rate and a source of transfer clock are determinedand bit 6 and 5 of port C are set at the serial datainput terminal and the serial clock terminal, respectively.Then dummy-writing or -reading the SCI data register, thesystem is ready for receiving data. (This procedure is notneeded after reading subsequent received data. It must be takenafter reset and after not reading subsequent received data.The data from the C 6 /Rx terminal is input to the SCIdata register synchronously with the rising edge of theserial clock (see Fig. 16). When 8 bits of data have been received,the interrupt request bit is set in bit 7 of the SCIstatus register. This request can be masked by setting bit 5of the SCI status register. If an external clock source have beenselected, the transfer rate determined by bits 0 - 3 of the SCIcontrol register is ignored and the data is received synchronouslywith the clock from the Cs /CK terminal. If the internalclock has been selected, the Cs/CK terminal is set as outputand clocks are output at the transfer rate selected by bits 0 -3 of the SCI control register..TIMER2The SCI transfer clock generator can be used as a timer.The clock selected by bits 3 - 0 of the SCI control register(4 p.s - approx. 32 ms (for oscillation at 4 MHz» is input tobit 6 of the SCI status register and the TIMER2 interruptrequest bit is set at each falling edge of the clock. Since interruptrequests occur periodically, TIMER2 can be used as areload counter or clock.---~~:, ®@~ ____ ~----~t~ ____ ~@@LCD : Transfer clock generator is reset and mask bit (bit 4of SCI status register! is clea red.®.@ : TIMER2 interrupt request@.@ : TlMER2 interrupt request bit clearedTIMER2 is commonly used with the SCI transfer clockgenerator. If wanting to use TIMER2 independently of theSCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCIclock source.If "Internal" is selected as the clock source, reading orwriting the SDR causes the· prescaler of the transfer clockgenerator to be initialized.-I/O PORTSThere are 24 input/output terminals (ports A, B, C). EachI/O terminal can be selected for either input or output by thedata direction register. More specifically, an I/O port willbe input if "0" is written in the data direction register, andoutput if "1" is written in the data direction register. Port A,B or C reads latched data if it has been programmed as output,even with the output level being fluctuated by the outputload. (See Fig. 17.)When reset, the data direction register and data register goto "0" and all the input/output terminals are used as input.Bit of datadirectionregisterBit ofoutputdataStatus ofoutputInput toCPU1 a 0 a1 1 1 1a x 3·state PinFigure 17Input/Output Port DiagramSeven input-only terminals are available (port D). Writingto an input terminal is invalid.All input/output terminals and input terminals are TTLcompatible and CMOS compatible in respect of both input andoutput.If I/O ports or input ports are not used, they should beconnected to VSS via resistors. With none connected to theseterminals, there is the possibility of power being consumeddespite that they are not used.-RESETThe MCV can be reset either by external reset input (RES)or power-on reset. (See Fig. 18.) On power up, the resetinput must be held "Low" for at least tose to assure that theinternal oscillator is stabilized. A sufficient time of delay canbe obtained by connecting a capacitance to the RES input asshown in Fig. 19.~HITACHI 435

HD6305X1,HD6305X2-------------------------------------------------------5VVceOV-------RESTerminal ---------rrequirement for minimum external configurations. It can bedriven by connecting a crystal (AT cut 2.0 -- 8.0MHz) orceramic oscillator between pins 5 and 6 depending on the requiredoscillation frequency stability.Three different terminal connections are shown in Fig. 20.Figs. 21 and 22 illustrate the speCifications and typical arrangementof the crystal, respectively.~::~al ____________ ~Figure 18 Power On and Reset TimingAT CutParallelResonanceCo=7pF max.f=2.0-S.0MHzRs=6OQ max.100kn typ 2V CC ~'N"v--+----,(a)Figure 21Parameters of CrystalHD6305XMCUFigure 19Input Reset Delay Circuit-INTERNAL OSCILLATORThe internal oscillator circuit is designed to meet the4366 EXTAliO-~t-OM-H-Z-1c:J~-t5 XTAl HD6305XMCU10-22pF±20%Crystal OscillatorHD6305XMCUExternal Ceramic OscillatorClockInput 6 EXTAlNC 5 XTAl HD6305XFigure 20MCUExternal Clock DriveInternal Oscillator Circuit~HITACHI[NOTE) Use as short wirings as possible for connection of the crystalwith the EXT AL and XTAL terminals. Do not allow thesewirings to cross others.Figure 22Typical Crystal Arrangement-LOW POWER DISSIPATION MODEThe HD6305X has three low power dissipation modes:wait, stop and standby..WaitModeWhen WAIT instruction being executed, the MCU entersinto the wait mode. In this mode, the oscillator stays activebut the internal clock stops. The CPU stops but the peripheralfunctions - the timer and the serial communication interface- stay active. (NOTE: Once the system has entered thewait mode, the serial communication interface can no longerbe retriggered.) In the wait mode, the registers, RAM and I/Oterminals hold their condition just before entering into thewait mode.The escape from this mode can be done by interrupt (INT,TIMER/INT2 or SCI/TIMER2), RES or STBY. The RESresets the MCU and the STBY brings it into the standbymode. (This will be mentioned later.)When interrupt is requested to the CPU and accepted, thewait mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interrupt ismasked by the I bit of the condition code register, after releasingfrom the wait mode the MCU executes the instructionnext to the WAIT. If an interrupt other than the INT (Le.,TIMER/INT2 or SCI/TIMER2) is masked by the timer control

-------------------------------------------------------HD6305X1,HD6305X2register, miscellaneous register or serial status register, thereis no interrupt request to the CPU, so the wait mode cannotbe released.Fig. 23 shows a flowchart for the wait function.• Stop ModeWhen STOP instruction being executed, MCU enters intothe stop mode. In this mode, the oscillator stops and the CPUand peripheral functions become inactive but the RAM,registers and 1/0 terminals hold their condition just beforeentering into the stop mode.The escape from this mode can be done by an externalinterrupt (INT or INT2), RES or STBY. The RES resets theMCU and the STBY brings into the standby mode.When interrupt is requested to the CPU and accepted,the stop mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interruptis masked by the I bit of the condition code register,after releasing from the stop mode, the MCU executes theinstruction next to the STOP. If the INT2 interrupt is maskedby the miscellaneous register, there is no interrupt request tothe MCU, so the stop mode cannot be released.Fig. 24 shows a flowchart for the stop function. Fig. 25shows a timing chart of return to the operation mode fromthe stop mode.For releasing from the stop mode by an interrupt, oscillationstarts upon input of the interrupt and, after the internaldelay time for stabilized oscillation, the CPU becomes active .For restarting by RES, oscillation starts when the RES goes"0" and the CPU restarts when the RES goes "I". The durationof RES="O" must exceed tose to assure stabilized oscillation.• Standby ModeThe MCU enters into the standby mode when the SrBYterminal goes "Low". In this mode, all operations stop andthe internal condition is reset but the contents of the RAM arehold. The I/O terminals turn to high-impedance state. Thestandby mode should escape by bringing STBY "High". TheCPU must be restarted by reset. The timing of input signalsat the RES and STBY terminals is shown in Fig. 26.Table 4 lists the status of each parts of the MCU in eachlow power dissipation modes. Transitions between each modeare shown in Fig. 27.~HITACHI 437

HD6305X1,HD6305X2-------------------------------------------------------Oscillator ActiveTimer and SerialClock ActiveAll Other ClocksStopInitializeCPU, TIMER; SCI,I/O and AllOther FunctionsNoNo1=1Load PC fromInterrupt VectorAddressesFetchInstructionFigure 23 Wait Mode Flow Chart438_HITACHI

-------------------------------------------------------HD6305Xl,HD6305X2Stop Oscillatorand All ClocksNoTurn on OscillatorWait for Time Delayto StabilizeTurn on OscillatorWait for Time Delayto Stabilize1=1load PC fromInterrupt VectorAddressesFetchInstructionFigure 24 Stop Mode Flow Chart~HITACHI439

HD6305X1 ,HD6305X2 -----------------------____ _o.:w.~~~"~~~~~~~tTime required for oscillation to becomeSTOP instructionexecutedInterrupt(a) Restart by Interruptstabilized (built·in delay time)InstructionsrestartOscillator 11111111111111111111111111111ESTOP instructionexecutedTime required for oscillation to becomestabilized (tose)Resetstart(b) Restart by ResetFigure 25 Timing Chart of Releasing from Stop Mode\HIiIIIi ,-_.. I __ I L __ I\toscRestartFigure 26Timing Chart of Releasing from Standby ModeTable 4Status of Each Part of MCU in Low Power Dissipation ModesModeHard-wareStandby440WAITSoft-- wareSTOPConditionStart Oscil· Timer, I/O EscapeCPURegister RAMlatorSerialterminalWAIT in·STBY, RES, INT, INI2,Active Stop Active Keep Keep Keep each interrupt request ofstructionTIMER, TIMER2, SCISTOP instructionStop Stop Stop Keep Keep Keep STBY, RES, INT, INT2STBY="Low" Stop Stop Stop Reset KeepHigh im·pedanceSTBY="High"~HITACHI

---------------------------------------------------------HD6305Xl,HD6305X2Figure 27Transitions among Active Mode, Wait Mode,Stop Mode, Standby Mode and Reset-BIT MANIPULATIONThe MCU can use a single instruction (BSET or BCLR) toset or clear one bit of the RAM or an I/O port (except thewrite-only registers such as the data direction register). Everybit of memory or I/O within page 0 ($00 ~ $FF) can be testedby the BRSET or BRCLR instruction; depending on the resultof the test, the program can branch to required destinations.Since bits in the RAM, or I/O can be manipulated, the usermay use a bit within the RAM as a flag or handle a single I/Obit as an independent I/O terminal. Fig. 28 shows an exampleof bit manipulation and the validity of test instructions. Inthe example, the program is configured assuming that bit 0of port A is connected to a zero cross detector circuit andbit 1 of the same port to the trigger of a triac.The program shown can activate the triac within a time oflOllS from zero-crossing through the use of only 7 bytes onthe ROM. The on-chip timer provides a required time ofdelay and pulse width modulation of power is also possible.SELF 1. BRClR 0, PORT A, SELF 1BSET 1, PORT ABClR 1, PORT AFigure 28Exa~ple of Bit Manipulation-ADDRESSING MODESTen different addressing modes are available to the MCU.elmmediateSee Fig. 29. The immediate addreSSing mode providesaccess to a constant which does not vary during execution ofthe program.This access requires an instruction length of 2 bytes. Theeffective address (EA) is PC and the operand is fetched fromthe byte that follows the operation code.e DirectSee Fig. 30. In the direct addressing mode, the address ofthe operand is contained in the 2nd byte of the instruction.The user can gain direct access to memory up to the lower255th address. All RAM and I/O registers are on page 0 of addressspace so that the direct addressing mode may be utilized.e ExtendedSee Fig. 31. The extended addressing is used for referencingto all addresses of memory. The EA is the contents ofthe 2 bytes that follow the operation code. An extendedaddressing instruction requires a length of 3 bytes.e RelativeSee Fig. 32. The relative addreSSing mode is used withbranch instructions only. When a branch occurs, the programcounter is loaded with the contents of the byte following theoperation code. EA = (PC) + 2 + ReI., where ReI. indicates asigned 8-bit data following the operation code. If no branchoccurs, ReI. = O. When a branch occurs, the program jumpsto any byte in the range + 129 to -127. A branch instructionrequires a length of 2 bytes.elndexed (No Offset)See Fig. 33. The indexed addreSSing mode allows accessup to the lower 255th address of memory. In this mode, aninstruction requires a length of one byte. The EA is thecontents of the index register.~HITACHI 441

HD6305X1,HD6305X2-------------------------------------------------------elndexed (8-bit Offset)See Fig. 34. The EA is the contents of the byte followingthe operation code, plus the contents of the index register.This mode allows access up to the lower 511 th address ofmemory. Each instruction when used in the index addressingmode (8-bit offset) requires a length of2 bytes.elndexed (16-bit Offset)See Fig. 35. The contents of the 2 bytes following theoperation code are added to content of the index registerto compute the value of EA. In this mode, the completememory can be accessed. When used in the indexed addressingmode (l6-bit offset), an instruction must be 3 bytes long.e Bit Set/ClearSee Fig. 36. This addressing mode is applied to the BSETand BCLR instructions that can set or clear any bit on pageO. The lower 3 bits of the operation code specify the bit tobe set or cleared. The byte that follows the operation codeindicates an address within page o.e Bit Test and BranchSee Fig. 37. This addressing mode is applied to the BRSETand BRCLR instructions that can test any bit within page 0and can be branched in the relative addressing mode. Thebyte to be tested is addressed depending on the contents ofthe byte following the operation code. Individual bits withinthe byte to be tested are specified by the lower 3 bits of theoperation code. The 3rd byte represents a relativ~ value whichwill be added to the program counter when a branch conditionis established. Each of these instructions should be 3 byteslong. The value of the test bit is written in the carry bit of thecondition code register.elmpliedSee Fig. 38. This mode involves no EA. All informationneeded for execution of an instruction is contained in theoperation code. Direct manipulation on the accumulatorand index register is included in the implied addressing mode.Other instructions such as SWI and RTI are also used in thismode. All instructions used in the implied addressing modeshould have a length of one byte.iMemoryAI::~I__ CA~F8 JIndex RegIStack PointPROG LOA :I$F8 05BEII::::~A~6=:}_------J05BFI F8IProg Count05COCCFigure 29Example of Immediate AddressingMemoryCATFCB32004B~~L:~~--t_---~~-----{~~2~O~:JIndex egPROG LOA CAT 0520052E r::~=::l----.J~ . .: :I 'Figure 30Example of Direct Addressing442 ~HITACHIAStack kbo::!":in=-:"t -_.....Prog !ount052FCC

-------------------------------------------------------HD6305Xl,HD6305X2Memory~0000: :PROG LOA CAT g:g!I-~~-_L040BI---':;';"'_-t"'A40Index RegIStack PointCATFCB6406E5~~4~0~~!_--------------~Prog Count040CCCFigure 31Example of Extended Addressing,Memory~PROG BEQ PROG2 04A7 2704A8 18Figure 32Example of Relative AddressingMemoryATABLFCC II 00B8~~4~C::::~--~~~-------1----------~~~4~C;;;J49B8Stack POintProg Count05F5CCFigure 33Example of Indexed (No Offset) Addressing~HITACHI 443

HD6305X1.HD6305X2-----------------------------------------------------TABL FCB BF 0089FCB 86 008AFCB DB OOBBFCB CF OOBCPROG LOA TABL.X 075B075CIIMeJoryBF86DBCF: :E689§, ,IIrlEAOOBC II/ Adder ""-r-' ----r---IIIACFIndex Reg03Stack PointIProg CountI 0750ccIIIIFigure 34Example of Index (8-bit Offset) AddressingMemory~ . .PROG LOA TABL.X 069206930694CCTABL FCB BF 077E BF IFCB B6 077F 86FCB DB 0780 DBFCB CF 0781 CFFigure 35Example of Index (16-bit Offset) AddressingMemoryPORT B EQU 1 0001t---=B;;;.F_-f"1PROG BCLR 6. PORT B 058F t=jlDtj r----.--J0590 01AIIndex RegStack PointProg Count0591CC~I, I ,Figure 36Example of Bit Set/Clear Addressing444 ~HITACHI

-------------------------------------------------------HD6305X1,HD6305X2PORT C EQU 2 0002 ~.....;.~--t IPROG BRCLR 2.PORT C PROG 2 05740575 .. 1-_-_-~~~ -_-_-1-10576t--~.;;...---tAIndex RegIProg ~ount0594Figure 37Example of Bit Test and Branch AddressingMemory•~"00'" ",. ~~IIIIIIIIFigure 38Example of Implied Addressing-INSTRUCTION SETThere are 62 basic instructions available to the HD6305XMeU. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, andcontrol. The details of each instruction are described inTables 5 through 11.• Register/Memory InstructionsMost of these instructions use two operands. One operandis either an accumulator or index register. The other is derivedfrom ~emory using one of the addressing modes used on theHD6305X MeU. There is no register operand in the unconditionaljump instruction (JMP) and the subroutine jumpinstruction (JSR). See Table s.• Read/Modify/Write InstructionsThese instructions read a memory or register, then modifyor test its contents, and write the modified value into thememory or register. Zero test instruction (TST) does notwrite data, and is handled as an exception in the read/modify/write group. See Table 6.• Branch InstructionsA branch instruction branches from the program sequencein progress if a particular condition is established. See Table 7.• Bit Manipulation InstructionsThese instructions can be used with any bit located up tothe lower 255th address of memory. Two groups are available;one for setting or clearing and the other for bit testing andbranching. See Table 8.• Control InstructionsThe control instructions control the operation of the MeUwhich is executing a program. See Table 9.• List of Instructions in Alphabetical OrderTable 10 lists all the instructions used on the HD6305XMeU in the alphabetical order.• Operation Code MapTable 11 shows the operation code map for the instructionsused on the MeU.~HITACHI 445

HD6305X1.HD6305X2 ---------------------------Table 5 Register/Memory InstructionsOperetionsLoad A from MemoryLOld X from MemoryStore A in MemoryStore X in MemoryAdd Memory to AAdd Memory and Carryto ASubtract MemorySubtract Memorv fromA with BorrowAND Memory to AOR Memorv with AExclusive OR Memorvwith AArithmetic Compare Awith MemorvArithmetic Compare Xwith MemorvBit Test Memorv withA (Logical Compare)Jump UnconditionalJump to SubroutineMnemonicLOALOXSTASTXADDAOCSUBSBCANDORAEORCMPCPX81TJMPJSRSymbols: Op ~ Operation# ~ Number of bytes- = Number of cyclesAddrelling ModesIndexed Indexed Indexed BooleenlArithmeticImmediate Direct Extended (No Offset) (S·Bit Offset) (l6-SitOtlset) OperationOP # - OP # - OP # - OP # - OP # - OP # -A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 06 3 5 M-AAE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 M-XB7 2 3 C7 3 4 F7 1 4 E7 2 4 07 3 5 A-MBF 2 3 CF 3 4 FF 1 4 EF 2 4 OF 3 5 X-MAB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 A+M-.AA9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 09 3 5 A+M+C-AAO 2 2 BO 2 3 CO 3 4 FO 1 3 EO 2 4 DO 3 5 A-M-AA2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 02 3 5 A-M-C-AA4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 04 3 5 A·M-AAA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 OA 3 5 A+M-AAS 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 08 3 5 A(£lM-AAl 2 2 Bl 2 3 Cl 3 4 Fl 1 3 El 2 4 01 3 5 A-MA3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 03 3 5 X-MA5 2 2 85 2 3 C5 3 4 F5 1 3 E5 2 4 05 3 5 A·MBC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4BO 2 5 CD 3 6 FO 1 5 ED 2 5 DO 3 6ConditionCodaH I N Z C• A A A A • •• A 1\ • •A AA•A 1\ r,A• 1\ t "• • A A I,• • 1\ A "• • I, 1\. •• • 1\ A •• • I, I' •• • 1\ I' "• • A I' r• A" •• • • • •IncrementDecrementCleerComplementNegateOperations(2's Complement)Rotate Left Thru CarryRotate Right Thru CarryLogical Shift LeftLogical Shift RightArithmetic Shift RightArithmetic Shift LeftTest for Negativeor ZeroI MnemonicIINCDECCLRCOMNEGROLRORLSLLSRASRASLTSTSymbols: Op = Operation# = Number of bytes- = Number of cyclesTable 6 Read/ModifylWrite InstructionsAddressing ModesIndexedIndexedImplied(A) Implied(X) Direct (No Offset) (8·Bit Offset)Booleanl Arithmetic OperationOP II - OP II - OP II - OP II - OP II -4C 1 2 5C 1 2 3C 2 5 7C 1 5 6C 2 6 A + 1 -A or X + 1 -X or M + 1 -M4A 1 2 5A 1 2 3A 2 5 7A 1 5 6A 2 6 A-I -A or X-I -X or M -1 -M4F 1 2 5F 1 2 3F 2 5 7F 1 5 6F 2 6 OO-A or OO-X or OO-M43 1 2 53 1 2 33 2 5 73 1 5 63 2 6 A-A or x-X or M-MOO-A-A or OO-X-X40 1 2 50 1 2 30 2 5 70 1 5 60 2 6 or OO-M-M49 1 2 59 1 2 39 2 5 79 1 5 69 2 6LO-( A ... x ... II ~~46 1 2 56 1 2 36 2 5 76 1 5 66 2 6LEJ=t eI I I I I I II IA r3 ...: MI [ bo~e b, ~48 1 2 58 1 2 38 2 5 78 1 5 68 2 61\ I,D-i I ~",:xr~ 11 t--0 • • "b, bo e44 1 2 54 1 2 34 2 5 74 1 5 64 2 601 1 IAr~"':MI I ro • • 0 A 1\47 1 2 57 1 2 37 2 5 77 1 5 67 2 6~ cL?b' -1\:1 IAH ...:t.i1I KJ • •A 1\48 1 2 58 1 2 38 2 5 78 1 5 68 2 6 Equal to LSL• • A 1\ A40 1 2 50 1 2 3D 2 4 70 1 4 60 2 5 A-OO or X-OO or M-OOConditionCodeH I N Z C• 1\ 1\ •A 1\ 0 1 •1\ I, 1• •• • " "1\• • 1\ , 1\• •A 1\ I,• • 1\ A •446$ HITACHI

-------------------------------------------------------HD6305X1,HD6305X2Table 7 Branch InstructionsAddressing ModesOperations Mnemonic RelativeBranch TestCondition CodeOP 1:* H I N Z CBranch Always BRA 20 2 3 None • •• • •Branch Never BRN 21 2 3 None • •• • •Branch IF Higher BHI 22 2 3 C+Z=O • •• • •Branch IF Lower or Same BLS 23 2 3 C+Z= 1 • •• • •Branch IF Carry Clear BCC 24 2 3 C =0 • •• • •(Branch IF Higher or Same) (BHS) 24 2 3 c=o • •• • •Branch IF Carry Set BCS 25 2 3 C = 1 • •• • •(Branch IF Lower) (BLO) 25 2 3 C= 1 • •• • •Branch IF Not Equal BNE 26 2 3 z=o • •• • •Branch IF Equal BEQ 27 2 3 Z= 1 • • • • I •-B-r-a-nc-h-I-F-H-a-If-C-a-rr-y-C-Ie-a-r--~---B-H-C-C---+-2-8·-1--2--+--3~-H-=--0---------------------r-.-r-.-r-.-r-.-~Branch IF Half Carry Set BHCS I 29 2 3 H = 1 •. 1 •I ••Branch IF Plus BPL 2A 2 3 N =0 • •• • •Branch IF Minus BMI 2B 2 3 N= 1 • I. • • •Branch IF Interrupt Mask +--------+----+--\1----+---------- ,I 1Bit is Clear I BMC 2C 2 I 3 I~O I_ I - , - I - I -Symbols: Op = Operation# = Number of bytes- = Number of cyclesOperationsMnemonicITable 8 Bit Manipulation InstructionsAddressing ModesBit Set Clear I Bit Test and Branch1I OP 1::1-[ OP 1::1-Branch IF Bit n is set : BRSET n(n=0···7) i ! 1 ~315Branch IF Bit n is clear \ BRCLR n(n=0···7) I I !01+2·n:3:5Set Bit n I BSET n(n=0···7) i 10+2·n I 2 5 1 I IClear Bit n I BCLR n(n=0-·-7) 111 +2·n j 2 51Symbols: Op = Operation# = Number of bytes- = Number of cyclesIIBoolean/Arithmetic IOperationBranchTestCondition CodeH i I I N'-ZTC- Mn=1·1· • • /\- Mn=O• • • • II1-+MnI-• • • • •O-+Mn -• • • • •~HITACHI447

HD6305X1,HD6305X2-------------------------------------------------------Table 9 Control InstructionsAddressing ModesOperations Mnemonic Implied Boolean OperationCondition CodeOP # - H I N Z CTransfer A to X TAX 97 1 2 A-X• • • • •Transfer X to A TXA 9F 1 2 X-A• • • • •Set Carry Bit SEC 99 1 1 l-C• • • • 1Clear Carry Bit CLC 98 1 1 O-C • 0Set Interrupt Mask Bit SEI 9B 1 2 1-1--1 Clear Interrupt Mask Bit CLI 9A 1 2 0-1 0 Software Interrupt SWI 83 1 10 1 Return from. Subroutine RTS 81 1 5 • • • • •Return from Interrupt RTI 80 1 8 ? ? ? ? ?Reset Stack Pointer RSP 9C 1 2 $FF-SP No-Operation NOP 90 1 1 Advance Prog. Cntr. Only • • •Converts binary add of BCD charcters IntoDecimal Adjust A DAA 80 1 2 1\ 1\ 1\*BCD formatStop STOP 8E 1 4--c--Wait WAIT 8F 1 4• • • • •Symbols: Op = Operation# ='Number of bytes- = Number of cycles* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)Table 10 Instruction Set (in Alphabetical Order)MnemonicImplied ImmediateADCxADDxANDxASlxASRxBCCBClRBCSBEQBHCCBHCSBHI(BHS)BIHBilBITx(BlO)BLSBMCBMIBMSBNEBPLBRACondition Code Symbols:H Half Carry (From Bit 3) CI Interrupt Mask1\N Negative (Sign Bit)•Z Zero ?Addressing ModesIndexed IndexedDirect Extended Relative (No Offset) (8-Bit)x x x xx x x xx x x xxx xxx xxxxxxxxxxx x xxxxxxxxxCarry/BorrowTest and Set if True. Cleared OtherwiseNot Affectedload CC Register From StackxIndexed(16-Bit)XXxxCondition CodeBit BitSet! Test &Clear Branch H I N Z C1\ 1\ 1\ 1\1\ 1\ 1\ 1\•x•1\ 1\ 1\ 1\ 1\1\ 1\ 1\• • • • •1\ 1\• • • • •• • • • •• • • • •• • • • •• • • • •• • • • •(to be continued)448~HITACHI

---------------------------------------------------------HD6305X1,HD6305X2Table 10 Instruction Set (in Alphabetical Order)MnemonicImplied ImmediateBRNBRCLRBRSETBSETBSRCLCXCliXCLRXCMPXCOMXCPXXDAAXDECXEORXINCXJMPJSRLOAXLOXXLSLXLSRXNEGXNOPXORAXROLXRORXRSPXRTIXRTSXSBCXSECXSEIXSTASTOPXSTXSUBXSWIXTAXXTSTXTXAXWAITXCondition Code Symbols:H Half Carry (from Bit 3) CI Interrupt Mask(\N Negative (Sign Bit)•Z ZeroDirectXAddressing ModesIndexedExtended Relative (No Offset)X X XXX X XXX X XXX X XX x XX x xX X XXXXX X XXx!XX X XX X XX x XX X XXCarry/BorrowTest and Set if True. Cleared OtherwiseNot AffectedLoad CC Register From StackXXXXXXXXXXXIndexed(S-Bit)XXXXXXXXXXXXXXXXXXXXXXIndexed(16-Bit)XXXXXxXXXXXXBitSetBitTest &Condition CodeClear Branch H I N Z C• • • • •X• • • • /\XX /\•• 00 • • 0 1 •/\ /\ /\/\ /\ 1/\ /\ /\/\ /\ /\,\ 1\ /\ /\I 1\ /\ • • /\ /\ •/\ /\ /\ /\ 1\0 /\ /\/, 1\ /\• • ,1\ /\ •/\ /\ /\/\ /\ /\• • • • •? ? ? ? ?• • •/\ /\ /\• 11 • • /, • • • /\ •• /\ /\ /\ /\ /\1• • /\ /\ • • • • •$ HITACHI449

HD6305X1,HD6305X2-----------------------------------------------------Table 11Operation Code MapBit Manipulation Branch Read/Modify/Write Control Register /MemoryTest &Set/Branch Clear Rei OIR A X ,Xl ,XO IMP IMP IMM OIR EXT ,X2 ,Xl ,XO0 1 2 3 4 5 6 7 8 9 A B C 0 E F +-H IGH0 BRSETO BSETO BRA NEG RTI'· - SUB 01 BRCLRO BCLRO BRN...- RTS' -- CMP 12 BRSETl BSETl BHI -- .- -- SBC 23 BRCLRl BCLR1 BLS COM SWI' CPX 34 BRSET2 BSET2 BCC LSR.. - - AND 45 BRCLR2 BCLR2 BCS--- BIT 56 BRSET3 BSET3 BNE ROR -- LOA 67 BRCLR3 BCLR3 BEQ ASR TAX' STA STAj+11 78 BRSET4 BSET4 BHCC LSl/ASL CLC EOR 89 BRCLR4 BCLR4 BHCS ROL SEC AOC 9A BRSET5 BSET5 BPL DEC CLI* ORA AB BRCLR5 BCLR5 BMI SEI* ADD BC BRSET6 BSET6 BMC INC RSP' JMP(-l) -C-D BRCLR6 BCLR6 BMS TSTHI TST TST(-l) OAA' NOP BSR' JSR(+2) JSR(+lJ~~~ 0E BRSET7 BSET7 BIL STOP' - LOX 7F BRClR7 BClR7 BIH CLR WAIT' TXA' STX STX(+11 F3/5 2/5 2/3 2 i 5 1/2 1/2 2/6 15 1." 111 2/2 2/3 3/4 3/5 2/4 1/3LoWJNOTES)1. "-" is an undefined operation code.2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).The number of cycles for the mnemonics asterisked (+) is as follows:RTI 8 TAX 2RTS 5 RSP 2SWI 10 TXA 2DAA 2 BSR 5STOP 4 ell 2WAIT 4 SEI 23. The parenthesized numbers must be added to the cycle count of the particular instruction.• Additional InstructionsThe following new instructions are used on the HD6305X:DAA Converts the contents of the accumulator into BCDcode.WAIT Causes the MCU to enter the wait mode. For this mode,see the topic, Wait Mode.STOP Causes the MCU to enter the stop mode. For this mode,see the topic, Stop Mode.450 $ HITACHI

HD6305YO,HD63A05YO,--­HD63B05YOCMOS MCU (Microcomputer Unit)HD6305YO is a CMOS 8-bit single-chip microcomputerwhich includes a CPU upward compatible with the HD6305XO.On the chip of the HD6305YO, 7872 byte ROM, 256 byte RAM,55 I/O terminals, two timers and a serial communication interface(SCI) are built in. And three low power dissipation modes(stop, wait and standby) support the low power operating.Instruction set is upward compatible with the HD6805 family.HD6305YOP, HD63A05YOP,HD63B05YOP-PRELIMINARV-• HARDWARE FEATURES.8-bit based MCU• 7872 bytes of ROM.256 bytes of RAM.A total of 55 terminals, including 32 I/O's, 7 inputs and 16outputs.Two timers8-bit timer with a 7-bit prescaler (programmable prescaler;event counter)15-bit timer (commonly used with the SCI clock divider)• On-chip serial interface circuit (synchronized with clock).Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation. modes- Wait ... , In this mode, the clock oscillator is on and theCPU halts but the timer/serial/interrupt functionis operatable.- Stop .... In this mode, the clock stops but the RAMdata, I/O status and registers are held.- Standby .. In this mode, the clock stops, the RAM datais held, and the other internal condition isreset..Minimum instruction cycle timeHD6305YO ...'. 1 "'S (f = 1 MHz)- HD63A05YO .... 0.67 "'S (f = 1.5 MHz)- HD63B05YO .... 0.5 "'S (f -= 2 MHz)• Wide operating rangeVCC = 3 to 6V (f = 0.1 to 0.5 MHz)HD6305YO f = 0.1 to 1 MHz (VCC = 5V ± 10%)HD63A05YO .... f = 0.1 to 1.5 MHz (VCC = 5V ± 100h)HD63B05YO .... f = 0.1 to 2 MHz (VCC = 5V ± 100h).System development fully supported by an evaluation kit_HD6305YOF, HD63A05YOF,HD63B05YOF(DP-64S)(FP-64)• Three new instructions, STOP, WAIT and DAA, added to theHD6805 family instruction set• Instructions that are upward compatible with those of Motorola'sMC6805P2 and MC146805G2• SOFTWARE FEATURES.Similar to HD6800• Byte efficient instruction set• Powerful bit manipulation instructions (Bit Set, Bit Clear, andBit Test and Branch usable for 192 byte RAM bits within pageo and all I/O terminals)• A variety of interrupt operations.Index addressing mode useful for table processing• A variety of conditional branch instructions• Ten powerful addressing modes• All addressing modes adaptable to RAM, and I/O instructions~HITACHI 451

HD6305YO.HD63A05YO.HD63B05YO------------~----------------~~-----------• PIN ARRANGEMENT• HD6305YOP, HD63A05YOP, HD63B05YOP0 ~Go~G,DG2G 3G4GsGsG7F7FsFsF4F3F%F,FoE7E,EsE4E3E2E,Eo0 70,/INT2Os0 40 3O 20,Co ~ ______________'- VeeVSS.£:::RES·CINTSTBYXTALEXTALNUM L-TIMERA7AsAsA4A3lA2A,AoB7B6BsB4B3B2B,BoC7/ TxC6/ RxCs/CKC4C3C 2C,• BLOCK DIAGRAM(Top View)B5B4B3B2B,BoC7/TxC6/RxXTAL EXTAL RES NUM iiiiT SriW• HD6305YOF, HD63A05YOF, HD63B05YOF(Top View)TIMERPortAI/OTerminalsAccumulator8 AIndex8 Register xCondition CodeRegister ·ccStackCPUCPUControl0,O./iNT;""0,Port 0D.0, Input0, Terminals0,Port BI/OTerminalsEoE,E, Port EE,E. OutputE. TerminalsE.E,FoF,F, Port FF,OutputF.F, TerminalsF.F,·1II:c0.;:;CIS~·tII:GoG,GoGoGoGoGoG,PortGI/OTerminals452 ~HITACHI

----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply voltage Vee -0.3 - +7.0 VI nput voltage Vin -0.3 - Vee + 0.3 VOperating temperature Topr 0-+70 °cStorage temperature Tstg -55 - +150 °c[NOTE)These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normaloperation, we recommended Vin, Vout; Vss ~ (Vin or Vout) ~ Vee .• ELECTRICAL CHARACTERISTICS• DC Characteristics (Vee = 5.0V ± 10%, Vss = GND and T. = 0 ,... +70°C unless otherwise specified)ItemSymDolTestconditionmin typ maxAES,S'fBV Vee- 0.5 - Vee+ 0.3Inputvoltage EXTAL VIH Vee x 0.7 - Vee+ 0.3"High"Others 2.0 - Vee+ 0.3Input voltage"Low"CurrentdissipationInputAll Input VIL -0.3 - 0.8Operating - 5 10Wait - 2 5leef = 1MHz*Stop - 2 10Standby - 2 10TIMER,leakage INT, IIILI - - 1current~-D7'BYThree- Ao -A7,Vin = 0.5-state Bo - B7, IITSII Vee - 0.5Vcurrent Co -C7,Go -G7,Eo-E7**Fo - F7**Input Allcapacity terminalsCinVin = OV- - 1f = 1MHz,- - 12UnitVVVVmArnAIlAIlAIlAIlApF• The value at f = xMHz can be calculated by the following equation:•• At standby modeICC (f = xMHz) = Icc (f = 1MHz) multiplied by x~HITACHI453

HD630SYO,HD63AOSYO,HD63BOSYO----------------------------------------------• AC Characteristics (Vee = 5.0V ± 10%, Vss = GND and T. = 0 -+70°C unless otherwise specified)ItemClockfrequencySymbolTest HD6305YO HD63A05YO HD63B05YOcondition min typ max min typ max min typ maxfcl 0.4 - 4 0.4 - 6 0.4 - 8 MHzCycle time tCYC 1.0 - 10 0.666 - 10 0.5 - 10 p.sINT pulsetlWL tcsc -tcyc-- -tcyc- - nswidth +2 0 +200 +200INT2 pulsetcyc tcyc tcycwidth tlwL2- --+250-+200+200RES pulsewidthUnit- - nstRWL 5 - - 5 - - 5 - - t cvcTIMER pulsetcyc tcyc tcycwidthtTWL+250- -+200- -+200CL = 22pF ±Oscillation200,.6start time tose Rs = 60n(crystal)maxReset delaytimetRHLExternal cap.2.2p.F- - ns- - 20 - - 20 - - 20 ms80 - - 80 - - 80 - - ms• Port Electrical Characteristics (Vee = 5.0V ± 10%, Vss = GND and Ta = 0 - +70°C unless otherwise specified)ItemSymbolTestconditionmin typ max UnitOutput volt-IOH = -200p.A 2.4 - - Vage "High"VO HPorts A,IOH = -10p.A Vee - 0.7 - - VB,C,G,Output volt- E,Fage "Low"VOL IOL = 1.6mA - - 0.55 VInput voltage"High"VIH 2.0 - Vee + 0.3 VInput volt- Ports A,age "Low" B,C,D, VIL -0.3 -0.8 VGInput leak-Vin=0.5-age currentIlLVee - 0.5V-1 - 1 p.A• SCI Timing (Vee = 5.0V±10%, Vss= GND and Ta= 0 - +70°C unless otherwise specified)Test HD6305YO HD63A05YO HD63B05YOItemSymbolConditionUnitmin typ max min typ max min typ maxClock ~ycle !~c 1 - 32768 0.67 - 21845 0.5 - 16384 p.sData Output Delay Time tTXD Fig. 1, - - 250 - - 250 - - 250 nsData Set-up Time tSRX Fig. 2 200 - - 200 - - 200 - - nsData Hold Time tHRX 100 - - 100 - - 100 - - ns4S4~HITACHI

-----------------------HD6305YO,HD63A05YO,HD63B05YOClock OutputCs/a

HD6305YO,HD63A05YO,HD63B05YO------------------------------------------------MEMORY MAPThe memory map of the HD6305YO MCU is shown inFig. 4. During interrupt processing, the contents of the MCUregisters are saved into the stack in the sequence shown inFig. 5. This saving begins with the lower byte (peL) of theprogram counter. Then the value of the stack pointer isdecremented and the higher byte (PCH) of the programcounter, index register (X), accumulator (A) and conditioncode register (CC) are stacked in that order. In a subroutinecall, only the contents of the program counter (PCH and PCL)are stacked.o63642552563193208182819181921/0 PortsTimerSCIRAM(192Bytes)StackRAM(64Bytes)ROM(7,872Bytes)~----------InterruptVectorsNot Used$0000roo$003F$gOFF$ 100\$013F$0140$1FF6$1FFF$200016383 $3FFFFigure 4Push0 PORT A $001 PORT B $012 PORT C $023 PORT 0 $03·"4 PORT A DDR $04"5 PORT BOOR $05"6 PORT C DDR $06"7 PORT G DDR $Or8 Timer Data Reg $089 Timer CTRL Reg $0910 Misc Reg11 PORT E$OASOB12 PORT F SOC13 PORT G $00Not Used16 SCI CTRL Reg17 SCI STS Reg18 SCI Data Reg63Not Used$10$11$12$3F" Write only regi ster." Read only regis terMemory Map of H06305YO MCU76543210I 1 1 1 ConditionPulln-4 n+lCode Registern-3 Accumulator n+2n-2 Index Register n+3n-l 1 1 IPCW n+4n PCl" n+5-REGISTERSThere are five registers which the programmer can operate.7 oI'--________A.... 1 Accumulator7 oIX / Index'--________..1 Register13 oI PC / Program~ _______________---,.Counter13 6 5 01~0_1~0.10~1_0~10.10~1~1~I_l~I ____ s_p ____ ~I~~~~rFigure 6~ggX~Zero'-----Negative'------InterruptMask~-----HalfCarryProgramming Model• Accumulator (A)This accumulator is an ordinary 8-bit register which holdsoperands or the result of arithmetic operation or data processing.• Index Register (X)The index register is an 8-bit register, and is used for indexaddressing mode. Each of the addresses contained in theregister consists of 8 bits which, combined with an offsetvalue, provides an effective address.In the case of a read/modify/write instruction, the indexregister can be used like an accumulator to hold operationdata or the result of operation.If not used in the index addressing mode, the register canbe used to store data temporarily.• Program Counter (PC)The program counter is a 14-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 14-bit register that indicates the addressof the next stacking space. Just after reset, the stackpointer is set at address $OOFF. It is decremented when datais pushed, and incremented when pulled. The upper 8 bitsof the stack pointer are fIXed to 00000011. During the MCUbeing reset or during a reset stack pointer (RSP) instruction,the pointer is set to address $OOFF. Since a subroutine orinterrupt can use space up to address $OOCI for stacking, thesubroutine can be used up to 31 levels and the interrupt upto 12 levels .• In a subroutine call, only PCl and PCH are stacked.Figure 5Sequence of Interrupt Stacking456 ~HITACHI• Condition Code Register (CC)The condition code register is a 5-bit register, each bitindicating the result of the instruction just executed. Thebits can be individually tested by conditional branch instruc-

----------------------------------------------HD6305YO,HD63A05YO,HD63B05YOtions. The CC bits are as follows:Half Carry (H): Used to indicate that a carry occurred betweenbits 3 and 4 during an arithmetic operation(ADD, ADC).Interrupt (I): Setting this bit causes all interr ·,ts, excepta software interrupt, to be ma~"ed. If aninterrupt occurs with the bit I set, it islatched. It will be processed the instantthe interrupt mask bit is reset. (More specifically,it will enter the interrupt processingroutine after the instruction following theCLI has been executed.)Negative (N): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is negative (bit 7 is logic"1 ").Z~ro (Z): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is zero.Carry I Represents a carry or borrow that occurredBorrow (C): in the most recent arithmetic operation. Thisbit is also affected by the Bit Test and Branchinstruction and a Rotate instruction.-INTERRUPTThere are six different types of interrupt: external interrupts(INT, INTz), internal timer interrupts (TIMER,TIMER2), serial interrupt (SCI) and interrupt by an instruction(SWI).Of these six interrupts, the INT2 and TIMER or the SCIand TIMER2 generate the same vector address, respectively.When an interrupt occurs, the program in progress stopsand the then CPU status is saved onto the stack. And then,the interrupt mask bit (I) of the condition code register isset and the start address of the interrupt processing routineis obtained from a particular interrupt vector address. Thenthe interrupt routine starts from the start address. Systemcan exit from the interrupt routine by an RTI instruction.When this instruction is executed, the CPU status beforethe interrupt (saved onto the stack) is pulled and the CPUrestarts the sequence with the instruction next to the one atwhich the interrupt occurred. Table 1 lists the priority ofinterrupts and their vector addresses.Table 1Priority of InterruptsInterrupt Priority Vector AddressRES 1 $1 FFE, $1FFFSWI 2 $1FFC, $1FFDINT 3 $1FFA, $1FFBTIMER/INT2 4 $1FF8, $1FF9SCI/TIMERz 5 $1FF6, $1FF7A flowchart of the interrupt sequence is shown in Fig. 7.A block diagram of the interrupt request source is shown inFig. 8.yTNTyfNf21 .... 1$FF .... SPO .... DDR·SCLR INT Logic$FF .... TDR$7F .... Timer Prescaler$50 .... TCR$3F .... SSR$OO .... SCR$7F-+MRyTIMERY SCIFigure 7Interrupt Flowchart~HITACHI 457

HD6305YO,HD63A05YO,HD63B05YO---------------------------------------------In the block diagram, both the external interrupts INT andINT2 are edge trigger inputs. At the falling edge of each input,an interrupt request is generated and latched. The INT interruptrequest is automatically cleared if jumping is made tothe INT processing routine. Meanwhile, the INT2 request iscleared if "0" is written in bit 7 of the miscellaneous register.For the external interrupts (INT, INT2), internal timerinterrupts (TIMER, TIMER2) and serial interrupt (SCI), eachinterrupt request is held, but not processed, if the I bit of thecondition code register is set. Immediately after the I bit iscleared, the corresponding interrupt processing starts accordingto th!.E!!0rity.The INT2 interrupt can be masked by setting bit 6 of themiscellaneous register; the TIMER interrupt by setting bit 6of the timer control register; the SCI interrupt by setting bit5 of the serial status register; and the TIMER2 interrupt bysetting bit 4 of the serial status register.The status of the INT terminal can be tested by a BIL orBIH instruction. The INT falling edge detector circuit andits latching circuit are independent of testing by these instructions.This is also true with the status of the INT2 terminal.• Miscellaneous Register (MR; $OOOA)The interrupt vector address for the external interruptINT2 is the same as that for the TIMER interrupt, as shownin Table I. For this reason, a special register called the miscellaneousregister (MR; $OOOA) is available to control theINT2 interrupts.Bit 7 of this register is the INT2 interrupt request flag.When the falling edge is detected at the INT2 terminal, "I"is set in bit 7. Then the software in the interrupt routine(vector addresses: $IFF8, $IFF9) checks bit 7 to see if itis INT2 interrupt. Bit 7 can be reset by software.Miscellaneous Register (MR;$OOOA)765432101M R71MR61Z1Z1ZlZV1ZJf tL __________ INT2 Interrupt Mask'------------- INTl Interrupt Request FlagBit 6 is the INT2 interrupt mask bit. Ifthis bit is set to "1",then the INT2 interrupt is disabled. Both read and write arepossible with bit 7 but "I" cannot be written in this bit bysoftware. This means that an interrupt request by softwareis impossible.When reset, bit 7 is cleared to "0" and bit 6 is set to "I" .-TIMERFigure 9 shows an MCU timer block diagram. The timerdata register is loaded by software and, upon receipt of aclock input, begins to count down. When the timer dataBIH/BIL TestINT InterruptLatchVectoring generated$1FFA,$1FFBCondition Code Register (CC)INTFalling Edge DetectorlMiscellaneousRegister (MR)TIMER)-----4I~f----Vectoring generated$1FF8,$1FF9SCI/TIMER2Serial StatusRegister (SSR))---.----- Vectoring generated$1FF6,$1FF7Figure 8Interrupt Request Generation Circuitry458 $ HITACHI

----------------------------------------------HD6305YO,HD63A05YO,HD63B05YOregister (TDR) becomes "0", the timer interrupt requestbit (bit 7) in the timer control register is set. In response tothe interrupt request, the MCV saves its status into the stackand fetches timer interrupt routine address from addresses$1 FF8 and $1 FF9 and execute the interrupt routine. Thetimer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the timer control register. The mask bit(I) in the condition code register can also mask the timerinterrupt.The source clock to the timer can be either an externalsignal from the timer input terminal or the internal E signal(the oscillator clock divided by 4). If the E signal is used asthe source, the clock input can be gated by the input to thetimer input terminal.Once the timer count has reached "0", it starts countingdown with "$FF". The count can be monitored wheneverdesired by reading the timer data register. This permits theprogram to know the length of time having passed after theoccurrence of a timer interrupt, without disturbing the contentsof the counter.When the MCV is reset, both the prescaler and counter areinitialized to logic "1". The timer interrupt request bit(bit 7) then is cleared and the timer interrupt mask bit (bit6) is set.To clear the timer interrupt request bit (bit 7), it is necessaryto write "0" in that bit.• Timer Control Register (TCR, $0009)Selection of a clock source, selection of a prescaler frequencydivision ratio, and a timer interrupt can be controlledby the timer control register (TCR; $0009).For the selection of a clock source, anyone of the fourmodes (see Table 2) can be selected by bits 5 and 4 of thetimer control register (TCR).Timer Control Register (TCR; $0009)4'-------------- Timer interrupt mask'-------------------Timer interrupt requestAfter reset, the TCR is initialized to "E under timer terminalcontrol" (bit 5 = 0, bit 4 = 1). If the timer terminal is"1 ", the counter starts counting down with "$FF" immediatelyafter reset.When "1" is written in bit 3, the prescaler is initialized.This bit always shows "0" when read.TCR7oTCR6oTimer interrupt requestAbsentPresentTimer interrupt maskEnabledDisabledTable 2 Clock Source SelectionTCRBit 5 Bit4Clock input sour:ce0 0 I nternal clock E0 1 E under timer terminal control1 0 No clock input (counting stopped)1 1 Event input from timer terminalInitialize(InternalClock)E --/---j3Timer DataRegister.....__..,...____,.-__-' Timer InterruptWriteReadFigure 9Timer Block Diagram~HITACHI 459

HD6305YO,HD63A05YO,HD63B05YO-----------------____ _A prescaler division ratio is selected by the combination ofthree bits (bits 0, 1 and 2) of the timer control register (seeTable 3). There are eight different division ratios; +1, +2, +4,+8, +16, +32, +64 and +128. After reset, the TCR is set to the+1 mode.Table 3TCRBit2 Bit 1 BitOPrescaler Division Ratio SelectionPrescaler division ratio0 0 0 +1'0 0 1 +20 1 0 +40 1 1 +8A timer interrupt is enabled when the timer interrupt maskbit is "0", and disabled when the bit is "1". When a timerinterrupt occurs, "1" is set in the timer interrupt request bit.This bit can be cleared by writing "0" in that bit.-SERIAL COMMUNICATION INTERFACE (SCI)This interface is used for serial transmission or receptionof 8~bit data. Sixteen transfer rates are available in the rangefrom IllS to approx. 32 ms (for oscillation at 4 MHz).The SCI consists of three registers, one eighth counter andone prescaler. (See Fig. 10.) SCI communicates with the CPUvia the data bus, and with the outside world through bits 5,6 and 7 of port C. Described below are the operations ofeach register and data transfer.eSCI Control Register (SCR; $0010)1 0 0 +161 0 1 +321 1 0 +641 1 1 +128SCI Control Registers (SCA; $0010)..... _E.... _--'TransferClockGeneratorInitializeSCI Status Registers(SSR :$0011 )Not UsedSCITIMER2Figure 10SCI Block Diagram460~HITACHI

---------------------------------------------HD6305YO,HD63A05YO,HD63B05YOSCR7oC 7 terminalUsed as I/O terminal (by DDR).Serial data output (DDR output)Bit 7 (SSR7)Bit 7 is the SCI interrupt request bit which is set uponcompletion of transmitting or receiving 8-bit data. It iscleared when reset or data is written to or read from theSCI data register with the SCRS=" I". The bit can also becleared by writing "0" in it.SCR6oC 6 terminalUsed as I/O terminal (by DDR).Serial data input (DDR input)SCR5 SCR4 Clock source C s terminal0 0 - Used as I/O terminal (by-0 1 -DDR).1 0 Internal Clock output (DDR output)1 1 External Clock input (DDR input)Bit 7 (SCR7)When this bit is set, the DDR corresponding to the C 7becomes "1" and this terminal serves for output of SCI data.After reset, the bit is cleared to "0".Bit 6 (SCR6)When this bit is set, the DDR corresponding to the C 6becomes "0" and this terminal serves for input of SCI data.After reset, the bit is cleared to "0" .Bits Sand 4 (SCRS, SCR4)These bits are used to select a clock source. After reset,the bits are cleared to "0".Bit 6 (SSR6)Bit 6 is the TIMER2 interrupt request bit. TIMER2 is usedcommonly with the serial clock generator, and SSR6 is seteach time the internal transfer clock falls. When reset, thebit is cleared. It also be cleared by writing "0" in it. (Fordetails, see TIMER2')Bit S (SSRS).Bit S is the SCI interrupt mask bit which can be set orcleared by software. When it is "1", the SCI interrupt (SSR7)is masked. When reset, it is set to "1".Bit 4 (SSR4)Bit 4 is the TIMER2 interrupt mask bit which can be setor cleared by software. When the bit is "I", the TIMER2interrupt (SSR6) is masked. When reset, it is set to "I".Bit 3 (SSR3)When "1" is written in this bit, the prescaler of the transferclock generator is initialized. When read, the bit always is "0".Bits 2,..., 0Not used.SSR7oSCI interrupt requestAbsentPresentBits 3,..., 0 (SCR3 ,..., SCRO)These bits are used to select a transfer clock rate. Afterreset, the bits are cleared to "0".SCR3 SCR2 SCR1 SCROTransfer clock rate4.00 MHz 4.194 MHz0 0 0 0 1 I1S 0.9511S0 0 0 1 211s 1.9111S0 0 1 0 411S 3.8211S0 0 1 1 811s 7.6411s1 1 1 1 1 11 1 1 1 3276811S 1/32 sSSR6oSSR5oSSR4oTIMER2 interrupt requestAbsentPresentSCI interrupt maskEnabledDisabledTIMER2 interrupt maskEnabledDisabledeSCI Data Register (SDR; $0012)A serial-parallel conversion register that is used for transferof data.eSCI Status Register (SSR; S0011)76543210ISSR7ISSR6ISSR5ISSR4ISSR3~• Data TransmissionBy writing the desired control bits into the SCI controlregisters, a transfer rate and a source of transfer clock aredetermined and bits 7 and S of port C are set at the serialdata output terminal and the serial clock terminal, respectively.The transmit data should be stored from the accumulatoror index register into the SCI data register. The datawritten in the SCI data register is output from the C 7 /Txterminal, starting with the LSB, synchronously with thefalling edge of the serial clock. (See Fig. 11.) When 8 bits of~HITACHI 461

HD6305YO,HD63A05YO,HD63B05YO---------------------------------------------data have been transmitted, the interrupt request bit is set inbit 7 of the SCI status register with the rising edge of thelast serial clock. This request can be masked by setting bit 5of the SCI status register. Once the data has been sent, the 8thbit data (MSB) stays at the C7/Tx terminal. If an externalclock source has been selected, the transfer rate determined bybits 0 - 3 of the SCI control register is ignored, and the Cs/CK terminal is set as input. If the internal clock has beenselected, the Cs/CK terminal is set as output and clocks areoutput at the transfer rate selected by bits 0 '" 3 of the SCIcontrol register.Figure 11 SCI Timing Chart• Data ReceptionBy writing the desired control bits into the SCI controlregister, a transfer rate and a source of transfer clock are determinedand bit 6 and 5 of port C are set at the serial datainput terminal and the serial clock terminal, respectively.Then dummy-writing or -reading the SCI data register, thesystem is ready for receiving data. (This procedure is notneeded after reading subsequent received data. It must be takenafter reset and after not reading subsequent received data.)The data from the C 6 /Rx terminal is input to the SCIdata register synchronously with the rising edge of theserial clock (see Fig. II). When 8 bits of data have been received,the interrupt request bit is set in bit 7 of the SCIstatus register. This request can be masked by setting bit 5of the SCI status register. If an external clock source have beenselected, the transfer rate determined by bits 0 '" 3 of the SCIcontrol register is ignored and the data is received synchronouslywith the clock from the Cs /CK terminal. If the internalclock has been selected, the Cs/CK terminal is set as outputand clocks are output at the transfer rate selected by bits 0 '"3 of the SCI control register..TIMER2The SCI transfer clock generator can be used as a timer.The clock selected by bits 3 '" 0 of the SCI control register(4 JlS '" approx. 32 ms (for oscillation at 4 MHz)) is input tobit 6 of the SCI status register and the TIMER2 interruptrequest bit is set at each falling edge of the clock. Since interruptrequests occur periodically, TIMER2 can be used as areload counter or clock.CD ®@ @@-----'.....! _----'r---~t'-_ ___Jr---.::;,LTIMER2 is commonly used with the SCI transfer clockgenerator. If wanting to use TIMER2 independently of theSCI, specify "External" (SCR5 = 1, SCR4 = 1) as the SCIclock source.If "Internal" is selected as the clock source, reading orwriting the SDR causes the prescaler of the transfer clockgenerator to be initialized.-I/O PORTSThere are 32 input/output terminals (ports A, B, C, G).Each I/O terminal can be selected for either input or outputby the data direction register. More specifically, an I/O portwill be input if "0" is written in the data direction register,and output if "1" is written in the data direction register.Port A, B or C reads latched data if it has been programmedas output, even with the output level being fluctuated by theoutput load. (See Fig. 12-a.) For port G, in such a case, thelevel of the pin is always read when it is read. (See Fig. 12-b.)This implies that, even when "1" is being output, port G mayread "0" if the load condition causes the output voltage todecrease to below 2 .OV .When reset, the data direction register and data register goto "0" and all the input/output terminals are used as input.Bit of data Bit ofdirection outputStatus of Input toregister dataoutput CPU1 0 0 01 1 1 10 X 3-state Pina. Ports A, Band CCD : Transfer clock generator is reset and mask bit (bit 4of SCI status register! is cleared.®.@ : TIMER2 interrupt request@.@ : T1MER2 interrupt request bit clearedFigure 12b. Port GInput/Output Port Diagram462 $ HITACHI

-----------------------------------------------HD6305YO,HD63A05YO,HD63B05YOThere are 16 output-only terminals (ports E and F). Eachof them can also read. In this case, latched data is read evenwith the output terminal level being fluctuated by the outputload (as with ports A, B and C).When reset, "Low" level is output from each output terminal.Seven input-only terminals are available (port D). Writingto an input terminal is invalid.All input/output terminals, output terminals and inputterminals are TTL compatible and CMOS compatible in respectof both input and output.If I/O ports or input ports are not used, they should beconnected to Vss via resistors. With none connected to theseterminals, there is the possibility of power being consumeddespite that they are not used.-RESETThe MCU can be reset either by external reset input (RES)or power-on reset. (See Fig. 13.) On power up, the resetinput must be held "Low" for at least 30 ms to assure that theinternal oscillator is stabilized. A sufficient time of delay canbe obtained by connecting a capacitance to the RES input asshown in Fig. 14.5VVccOV6 EXTAL.......-5-t XTAL HD6305YOMCU10-22pF±20%iO-:,I-OM-H-Zc::JCrystal OscillatorHD6305YOMCUExternal Ceramic OscillatorClockInput 6 EXTALNC 5 XTAL HD6305YOMCURESV ~-VIH RESTerminal----------------~- tRHL I---Figure 15External Clock DriveI nternal Oscillator Circuit~::;;al----__ --------------~Figure 13Power On and Reset Timing100kSl typ 2v cc ~"V\./'v"""'I-----,HD6305YOMCURES*2.2.uFC1C~ sXTALEXTAL5 Co 6(a)Figure 16Parameters of CrystalAT CutParallelResonanceCo=7pF max.f=2.0-S.0MHzRs=600 max.Figure 14Input Reset Delay Circuit-INTERNAL OSCILLATORThe internal oscillator circuit is designed to meet therequirement for minimum external configurations. It can bedriven by connecting a crystal (AT cut 2.0 '" 8.0MHz) orceramic oscillator between pins 5 and 6 depending on the requitedoscillation frequency stability.Three different terminal connections are shown in Fig. 15.Figs. 16 and 17 illustrate the specifications and typical arrangementof the crystal, respectively.[NOTE) Use as short wirings as possible for connection of the crystalwith the EXTAL and XTAL terminals. Do not allow thesewirings to cross others.Figure 17Typical Crystal Arrangement~HITACHI 463

"HD6305YO,HD63A05YO,HD63B05YO-----------------------------------------------LOW POWER DISSIPATION MODEThe HD6305YO has three low power dissipation modes:wait, stop and standby.• Wait ModeWhen WAIT instruction being executed, the MCU entersinto the wait mode. In this mode, the oscillator stays activebut the internal clock stops. The CPU stops but the peripheralfunctions - the timer and the serial communication interface- stay active. (NOTE: Once the system has entered thewait mode, the serial communication interface can no longerbe retriggered.) In the wait mode, the registers, RAM and I/Oterminals hold their condition just before entering into thewait mode.The escape from this mode can be done by interrupt (INT,TIMER/INT2 or SCI/TIMER2), RES or STBY. The RESresets the MCU and the STBY brings it into the standbymode. (This will be mentioned later.)When interrupt is requested to the CPU and accepted, thewait mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interrupt ismasked by the I bit of the condition code register, after releasingfrom the wait mode the MCU executes the instructionnext to the WAIT. If an interrupt other than the INT (Le.,TIMER/INT2 or SCI/TIMER2) is masked by the timer controlregister, miscellaneous register or serial status register, thereis no interrupt request to the CPU, so the wait mode cannotbe released.Fig. 18 shows a flowchart for the wait function.• Stop ModeWhen STOP instruction being executed, MCU enters intothe stop mode. In this mode, the oscillator stops and the CPUand peripheral functions become inactive but the RAM,registers and I/O terminals hold their condition just beforeentering into the stop mode.The escape from this mode can be done by an externalinterrupt (00 or INT2), RES or STBY. The RES resets theMCU and the STBY brings into the standby mode.When interrupt is requested to the CPU and accepted,the stop mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the inter-"rupt is masked by the I bit of the condition code register,after releasing from the stop mode, the MCU executes theinstruction next to the STOP. If the INT2 interrupt is maskedby the miscellaneous register, there is no interrupt request tothe MCU, so the stop mode cannot be released.Fig. 19 shows a flowchart for the stop function. Fig. 20shows a timing chart of return to the operation mode fromthe stop mode.For releasing from the stop mode by an interrupt, oscillationstarts upon input of the interrupt and, after the internaldelay time for stabilized oscillation, the CPU becomes active.For restarting by RES, oscillation starts when the RES goes"0" and the CPU restarts when the RES goes "1". The durationof RES="O" must exceed 30 ms to assure stabilized oscillation.• Standby ModeThe MCU enters into the standby mode when the STBYterminal goes "Low". In this mode, all operations stop andthe internal condition is reset but the contents of the RAM arehold. The I/O terminals turn to high-impedance state. Thestandby mode should escape by bringing STBY "High". TheCPU must be restarted by reset. The timing of input signalsat the RES and STBY terminals is shown in Fig. 21.Table 4 lists the status of each parts of the MCU in eachlow power dissipation modes. Transitions between each modeare shown in Fig. 22.464 $ HITACHI

----------------------------------------------HD6305YO,HD63A05YO,HD63B05YOOscillator ActiveTimer and SerialClock ActiveAll Other ClocksStopInitializeCPU, TIMER, SCI,I/O and AllOther FunctionsNoNoLoad PC fromInterrupt VectorAddressesFetchInstructionFigure 18Wait Mode Flow Chart~HITACHI465

Oscillator andAll Clocks Stop.NoTurn on OscillatorWait for Time Delayto StabilizeTurn on OscillatorWait for Time Delayto Stabilize1=0Load PC fromInterrupt VectorAddressesFetchInstructionFigure 19Stop Mode Flow Chart466$ HITACHI

~_.l_-L. __~~~~~~~~~~~~~~~~~~~~~~-HD6305YO,HD63A05YO,HD63B05YOO·":~'~I~: ~~I~~~~ITime required for oscillation to becomeSTOP instructionexecutedInterrupt(a) Restart by Interruptstabilized (built-in delay time)restartOscillator IIIII111111111111111111111111E~Ir----+----'RESSTOP instructionexecutedTime required for oscillation to becomestabilized (tosclResetstart(b) Restart by ResetFigure 20Timing Chart of ReleaSing from Stop Mode\ H IRESIIIiIIII\toscRestartFigure 21Timing Chart of Releasing from Standby ModeTable 4Status of Each Part of MCU in Low Power Dissipation ModesConditionModeStartOscil-Timer,I/OEscapeCPURegister RAMlatorSerialterminalWAIT in-mY, RE~, INT, INT"WAIT Active Stop Active Keep Keep Keep each interrupt request ofSoft- structionTIMER TIMER~, SCI- wareSTOP in-STOPStop Stop Stop Keep Keep Keep STBY, RES, INT, INT2structionStand- Hard-High im-STBY="Low" Stop Stop Stop Reset Keepby ware pedanceSTBY="High"~HITACHI 467

HD6305YO,HD63A05YO,HD63B05YO----------------------------------------------Figure 22Transitions among Active Mode, Wait Mode,Stop Mode, Standby Mode and Reset-BIT MANIPULATIONThe HD6305YO MCV can use a single instruction (BSETor BCLR) to set or clear one bit of the RAM within page 0 oran I/O port (except the write-only registers such as the datadirection register). Every bit of memory or I/O within page 0($00"'" $FF) can be tested by the BRSET or BRCLR instruction;depending on the result of the test, the program canbranch to required destinations. Since bits in the RAM on page0, or I/O can be manipulated, the user may use a bit within theRAM on page 0 as a flag or handle a single I/O bit as anindependent I/O terminal. Fig. 23 shows an example of bitmanipulation and the validity of test instructions. In theexample, the program is configured assuming that bit 0 of portA is connected to a zero cross detector circuit and bit 1 of thesame port to the trigger of a triac.The program shown can activate the triac within a time oflOlls from zero-crossing through the use of only 7 bytes onthe ROM. The on-chip timer provides a required time ofdelay and pulse width mudulation of power is also possible.SE IF 1. BRClR 0, PORT A. SELF 1BSET 1 • PORT ABClR 1, PORT AFigure 23Exa~ple of Bit Manipulation-ADDRESSING MODESTen different addressing modes are available to theHD6305YO MCV.elmmediateSee Fig. 24. The immediate addressing mode providesaccess to a constant which does not vary during execution of468 ~HITACHIthe program.This access requires an instruction length of 2 bytes. Theeffective address (EA) is PC and the operand is fetched fromthe byte that follows the operation code.eDirectSee Fig. 25. In the direct addressing mode, the address ofthe operand is contained in the 2nd byte of the instruction.The user can gain direct access to memory up to the lower255th address. 192 byte RAM and I/O registers are on page 0of address space so that the direct addressing mode may beutilized.e ExtendedSee Fig. 26. The extended addressing is used for referenc·ing to all addresses of memory. The EA is the contents ofthe 2 bytes that follow the operation code. An extendedaddressing instruction requires a length of 3 bytes.• RelativeSee Fig. 27. The relative addressing mode is used withbranch instructions only. When a branch occurs, the programcounter is loaded with the contents of the byte following theoperation code. EA = (PC) + 2 + ReI., where ReI. indicates asigned 8·bit data following the operation code. If no branchoccurs, ReI. = O. When a branch occurs, the program jumpsto any. byte in the range + 129 to -127. A branch instructionrequires a length of 2 bytes.• Indexed (No Offset)See Fig. 28. The indexed addressing mode allows accessup to the lower 255th address of memory. In this mode, aninstruction requires a length of one byte. The EA is thecontents of the index register.

~~~~~~~~~~~~~~~~~~~~~~-HD6305Y~HD63A05YO.HD63B05YOe Indexed (8-bit Offset)See Fig. 29. The EA is the contents of the byte followingthe operation code, plus the contents of the index register.This mode allows access up to the lower 511 th address ofmemory. Each instruction when used in the index addressingmode (8-bit offset) requires a length of 2 bytes.elndexed (16-bit Offset)See Fig. 30. The contents of the 2 bytes following theoperation code are added to content of the index registerto compute the value of EA. In this mode, the completememory can be accessed. When used in the indexed addressingmode (16-bit offset), an instruction must be 3 bytes long.e Bit Set/ClearSee Fig. 31. This addressing mode is applied to the BSETand BCLR instructions that can set or clear any bit on pageO. The lower 3 bits of the operation code specify the bit tobe set or cleared. The byte that follows the operation codeindicates an address within page O.e Bit Test and BranchSee Fig. 32. This addressing mode is applied to the BRSETand BRCLR instructions that can test any bit within page 0and can be branched in the relative addressing mode. Thebyte to be tested is addressed depending on the contents ofthe byte following the operation code. Individual bits withinthe byte to be tested are specified by the lower 3 bits of theoperation code. The 3rd byte represents a relative value whichwill be added to the program counter when a branch conditionis established. Each of these instructions should be 3 byteslong. The value of the test bit is written in the carry bit of thecondition code register.elmpliedSee Fig. 33. This mode involves no EA. All informationneeded for execution of an instruction is contained in theoperation code. Direct manipulation on the accumulatorand index register is included in the implied addressing mode.Other instructions such as SWI and RTI are also used in thismode. All instructions used in the implied addressing modeshould have a length of one byte.IMemory~: :PROG LOA #$F8 058Et::~~~f-_----~05BFIt-""';";;--I~I•: Iili--=~_---ltA ~:JIF8Index RegIStack PointProg Count05COCCFigure 24Example of Immediate AddressingMemoryACATFCB32004Bt:~c::jr---+----~~-----{~~2~O::Jlndex egPROG LOA CAT 0520 t-:~t::::l--~052E ...~II: :; IStack PointProg Count052FCCFigure 25Example of Direct Addressing~HITACHI 469

HD6305Y~HD63A05YO,HD63B05YO~~~~~~~~~~~~~~~~~~~~~~Memory~: :PROG LOA CAT g:g!t-~~--L040BI-""';;';;'-_ ...0000A40Index RegIStack PointtATFCB6406E5~~~::~ ______________ ~Prog Count040CCCFigure 26Example of Extended AddressingMemoryAIndex RegIStack PointPROG BEQ PROG2 04A704A8Prog Count04C1rC;,;:C~~_.,Figure 27Example of Relative AddressingMemoryATABLFCC II 00B8t:~4~C~:j~--~~~-------1----------~~~4~C;;~49o'''§Stack"06 CDA X§. . ,Figure 28B8PointProg Count05F5CCExample of Indexed (No Offset) Addressing470 $ HITACHI

----------------------------------------------HD6305YO,HD63A05YO,HD63B05YOTABL FCB II BF 0089FCB 1186 008AFCB 1I0B 008BFCB IICF 008CPROG LOA TABl.X 075B075CMe~Ory: .IBF86DBCF: :E689§,lEAI 008C I,/ Adder "'--r--- ~ AIIICFIndex Reg03Stack PointIProg CountI 0750CC11IIFigure 29Example of Index (S·bit Offset) AddressingMemory@, .PROG LOA TABl.X ~::~t--:-=---I0694 I-----tTABL :~:FCB:::1t08 0780g~~~ .. t::~:~:[::~---------.-l08FCB IICF 0781 ........;C;,;.F_......Figure 30Example of Index (16·bit Offset) AddressingMemoryPORT B EQU 1 00011-....;B;,;.F_-r"lPROG BCLR 6. PORT B 058F t=:.2 1 0t:~~ ___ .-l0590 01~I , :,AIIndex RegStack PointProg Count0591CCFigure 31Example of Bit Set/Clear Addressing$ HITACHI471

PORT C EQU 2.0002 ...-.....;.FO:"---j I L __/AIndex RegIStack POIntPROG BRCLR 2.PORT C.PROG 2 g:~:"'--;~;'~_-I0576.,.-....:.1:;;,,0_-1Prog bount0594CCCFigure 32Example of Bit Test and Branch Addressing,Memory~',",0 ,.. " .. ~~IIIIIII•Figure 33Example of Implied Addressing-INSTRUCTION SETThere are 62 basic instructions available to the HD6305YOMeV. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, andcontrol. The details of each instruction are described inTables 5 through 11.• Register/Memory InstructionsMost of these instructions use two operands. One operandis either an accumulator or index register. The other is derivedfrom ~emory using one of the addressing modes used on theHD6305YO MeV. There is no register operand in the unconditionaljump instruction (JMP) and the subroutine jumpinstruction (JSR). See Table 5.• Read/Modify/Write InstructionsThese instructions read a memory or register, then modifyor test its contents, and write the modified value into thememory or register. Zero test instruction (TST) does notwrite data, and is handled as an exception in the read/modify/write group. See Table 6.472 ~HITACHI• Branch InstructionsA branch instruction branches from the program sequencein progress if a particular condition is established. See Table 7.• Bit Manipulation InstructionsThese instructions can be used with any bit located up tothe lower 255th address of memory. Two groups are available;one for setting or clearing and the other for bit testing andbranching. See Table 8.• Control InstructionsThe control instructions control the operation of the MeVwhich is executing a program. See Table 9.• List of Instructions in Alphabetical OrderTable to lists all the instructions used on the HD6305YOMeV in the alphabetical order.• Operation Code MapTable 11 shows the operation code map for the instructionsused on the Mev.

~~~~~~~~~~~~~~~~~~~~~~-HD6305YO,HD63A05YO,HD63B05YOTable 5 Register/Memory InstructionsOperationsLoad A from MemoryLoad X from MemoryStore A in MemoryStore X in MemoryAdd Memory to AAdd Memory and Carryto ASubtract MemorySubtract Memory fromA with BorrowAND Memory to AOR Memory with AExclusive OR Memorywith AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory withA (Logical Compare)Jump UnconditionalJump to SubroutineMnemonicLOALOXSTASTXADDAOCSUBSBCANDORAEORCMPCPXBITJMPJSRSymbols: Op = Operation# = Number of bytes- = Number of cyclesAddressing ModesIndexed Indexed Indexed BooleanlArithmeticImmediate Direct Extended (No Offset) (S-Bit Offset) (16-BitOffsetl OperationOP II - OP II - OP II - OP II - OP II - OP II -A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 06 3 5 M~AAE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 M~XB7 2 J. C7 3 4 F7 1 4 E7 2 4 07 3 5 A~MBF 2 3 CF 3 4 FF 1 4 EF 2 4 OF 3 5 X~MAB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 A+M-·AA9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 09 3 5 A+M+C~AAO 2 2 BO 2 3 CO 3 4 FO 1 3 EO 2 4 DO 3 5 A-M-·AA2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 02 3 5 A-M-C~AA4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 04 3 5 A·M~AAA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 OA 3 5 A+M~AA8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 08 3 5 A'-!:JM-AAI 2 2 Bl 2 3 Cl 3 4 Fl 1 3 El 2 4 01 3 5 A-MA3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 03 3 5 X-MA5 2 2 85 2 3 C5 3 4 F5 1 3 E5 2 4 05 3 5 A·MBC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4BO 2 5 CD 3 6 FO 1 5 ED 2 5 DO 3 6ConditionCodeH I N Z Ca a 1\ f, aa a 1\ f, aa a 1\ r aa a 1\ 1\ a1\ a 1\1\ a 1\ fa a Aa a ,A /a a t," aa a aa a ,A aa a ra a 1\a a 1\ aa a a a aa a a a aTable 6 Read/ModifylWrite InstructionsOperationsIncrementDecrementClearComplementI MnemonicIINCDECCLRCOMAddressing ModesIndexedIndexedImplied(A) Implied(X) Direct (No Offset) (S-Bit Offset)OP II - OP II - OP II - OP II - OP II -Booleanl Arithmetic Operation4C 1 2 5C 1 2 3C 2 5 7C 1 5 6C 2 6 A+l~A or X+l-X or M+l-M4A 1 2 5A 1 2 3A 2 5 7A 1 5 6A 2 6 A-I ~A or X-l-X or M-l ~M4F 1 2 5F 1 2 3F 2 5 7F 1 5 6F 2 6 OO~A or OO~X or OO-M43 1 2 53 1 2 33 2 5 73 1 5 63 2 6 A~A or X~X or M~MConditionCodeH I N Z Ca a 1\ 1\ aa a 1\ 1\ aa a 0 1 aa a 1\ 1\ 1NegateOO-A~A or OO-X~X(2's Complement)Rotate Left Thru CarryNEGROL40 1 2 50 1 2 30 2 5 70 1 5 60 2 6 or OO-M~M49 1 2 59 1 2 39 2 5 79 1 5 69 2 6Lb-tA 01 X or III I I I I I IboiJa a 1\ 1\ 1\a a 1\ /\ /\Rotate Right Thru CarryROR46 1 2 56 1 2 36 2 5 76 1 5 66 2 6~b,! !AHor:M! ! bo~a a 1\ 1\ 1\Logical Shift LeftLogical Shift RightLSLLSRc b, bo48 1 2 58 1 2 38 2 5 78 1 5 68 2 6D-1 I ~or:xr~ I I 1-b, 0110 C44 1 2 54 1 2 34 2 5 74 , 5 64 2 60-1 ! IAH~MI I 1-0a a 1\ 1\ 1\a a 0 1\ 1\Arithmetic Shift RightArithmetic Shift L.lftTest for Negativeor ZeroASRASLTSTSymbols: Op· Operation# • Number of bytes- • Number of cyclesbo C47 1 2 57 1 2 37 2 5 77 1 5 67 2 6 [(b':1 1+~or:MI 11-048 1 2 58 1 2 38 2 5 78 1 5 68 2 6 Equal to LSL40 1 2 50 1 2 3D 2 4 70 1 4 60 2 5 A-OO or X-OO or M-OOa a 1\ 1\ 1\a a 1\ 1\ 1\a a 1\ 1\ a~HITACHI473

HD6305YO,HD63A05YO,HD63B05YO----------------------------------------------Table 7 Branch InstructionsOperationsBranch AlwaysBranch NeverBranch IF HigherBranch IF lower or SameBranch IF Carry Clear(Branch IF Higher or Same).Branch IF Carry Set(Branch IF L

~~~~~~~~~~~~~~~~~~~~~~-HD6305YO.HD63A05YO.HD63B05YOTable 9 Control InstructionsAddressing ModesOperations Mnemonic Implied Boolean OperationCondition CodeOP # - H I N Z CTransfer A to X TAX 97 1 2 A-+X• • • • •Transfer X to A TXA 9F 1 2 X-+A• • • • •Set Carry Bit SEC 99 1 1 1-+C• • • • 1Clear Carry Bit ClC 98 1 1 O-+C • 0Set Interrupt Mask Bit SEI 9B 1 2 1-+1 1 Clear Interrupt Mask Bit Cli 9A 1 2 0-+1 0 - ---Software Interrupt SWI 83 1 10 1 Return from Subroutine RTS 81 1 5• • • • •Return from Interrupt RTI 80 1 8 ? ? ? ? ?Reset Stack Pointer RSP 9C 1 2 $FF-+SP No-Operation NOP 90 1 1 Advance Prog. Cntr. Only • • •Decimal Adjust A OAA Converts binary add of BCD charCler-s Inlo80 1 2 BCD format 1\ 1\ 1\*Stop STOP 8E 1 4 Wait WAIT 8F 1 4• • • • •Symbols; Op = Operation# = Number of bytes- = Number of cycles* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance'!I Interrupt Mask1\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit)Not Affected•Z Zero ? load CC Register From StackTable 10 Instruction Set (in Alphabetical Order)MnemonicAddressing ModesIndexed Indexed IndexedImplied Immediate Direct Extended Relative (No Offset) (B-Bit) (16-Bit)ADCXX X XX XADDXX X XX XANDXX X XX XASlXXXXASRXXXXBCC ....XBClRBCSBEQBHCCBHCSBHI(BHS)BIHBilXXXXXXXXBITXX X XX X(BlO)BlSBMCBMIBMSBNEBPlBRAXXXXXXXXCondition Code Symbols;H Half Carry (From Bit 3) C Carry lBorrowCondition CodeBit BitSet! Test &Clear Branch H I N Z C/\ /\ /\ /\/\ /\ /\ /\•X•/\ /\ /\ /\ '/\/\ 1\ 1\• • /\ 1\ • • • • •• • • • •(to be continued)~HITACHI475

HD6305YO,HD63A05YO,HD63B05YO------------------------------------________ _Table 10 Instruction Set (in Alphabetical Order)MnemonicBRNBRCLRBRSETBSETBSRCLCCLICLRCMPCOMCPXDAADECEORINCJMPJSRLOALOXLSLLSRNEGNOPORAROLRORRSPRTIRTSSBCSECSEISTASTOPSTXSUBSWITAXTSTTXAWAITImpliedxxxxxxxxxxxxxxxxxxxxxxxxImmediatexxxxxCondition Code Symbols:H Half Carry (From Bit 3) CI Interrupt MaskAN Negative (Sign Bit)•Z ZeroxxxDirectAddressing ModesIndexedExtended Relative (No Offset)xxxx x xxxx x xxxx x xxxx x xx x xx x xx x xxxxxxxx x xxxxxx x xx x xx x xx x xxCarry /BorrowTest and Set if True, Cleared OtherwiseNot AffectedLoad CC Register From StackxxIndexed(S-Bit)xxxxxxxxxxxxxxxxxxxxxxIndexed(16-Bit)xxxxxxxxxxxxCondition CodeBit BitSet! Test &Clear Branch H I N Z Cxxx•AA•• 00 • • 0 1 •• II A A• A /\ 1A II IIA A A• • A 1\ •A A/\ A • • /\ II •A A• • II A A0 A AA A A• • •A A A II AA A II• • • • •? ? ? ? ?• • •• A A A• • • 11 • • II • A • •• • A II A A A1• • II A• • • • •476~HITACHI

JMP(-1)STX---------------------------------------------·HD6305YO.HD63A05YO.HD63B05YOTable 11Operation Code Map"-"-Bit Manipulation Branch Read/Modify/Write Control Register /MemoryTest & Set/Branch Clear Rei OIR A X ,X1 ,XO IMP IMP IMM OIR EXT .X2 ,X1 ,XO0 1 2 3 4 5 6 7 8 9 A B C 0 E F ........ HIGH0 BRSETO BSETO BRA NEG RTI" SUB 01 BRCLRO BCLRO BRN - RTS" CMP 12 BRSET1 BSET1 BHI - SBC 23 BRCLR1 BClR1 BlS COM SWI" CPX 3 L4 BRSET2 BSET2 BCC lSR - AND 4oW5 BRCLR2 BCLR2 BCS - BIT 56 BRSET3 BSET3 BNE ROR LOA 6-7 BRCLR3 BClR3 BEQ ASR TAX" STA STAI+l) 78 BRSET4 BSET4 BHCC LSl/ASl CLC EOR 89 BRCLR4 BClR4 BHCS ROL SEC AOC 9A BRSET5 BSET5 BPL DEC CLI· ORA AB BRCLR5 BClR5 BMI - SEI* ADD BC BRSET6 BSET6 BMC INC RSP" C0 BRCLR6 BCLR6 BMS TSTI-l) TST TST(-1) OAA" NOP BSR" JSR(+2) JSR(+ 1) JSRI+2) 0E BRSET7 BSET7 Bil - STOP" - lOX EF BRCLR7 BCLR7 BIH CLR WAIT" TXA" STXI+l) F3/5 2/5 2/3 2/5 1/2 1/2 2/6 1/5 1/" 1/1 2/2 2/3 3/4 3/5 2/4 1/3(NOTES)1. "-" is an undefined operation code.2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).The number of cycles for the mnemonics asterisked (*) is as follows:RTI 8 TAX 2RTS 5 RSP 2SWI 10 TXA 2DAA 2 BSR 5STOP 4 ell 2WAIT 4 SEI 23. The parenthesized numbers must be added to the cycle count of the particular instruction.• Additional InstructionsThe following new instructions are used on the HD630SYO:DAA Converts the contents of the accumulator into BCDcode.WAIT Causes the MCU to enter the wait mode. For this mode,see the topic, Wait Mode.STOP Causes the MCU to enter the stop mode. For this mode,see the topic, Stop Mode.·~HITACHI 477

H06305Y1 ,H063A05Y1 ,HD63B05Y1-­H 06305 Y2, H 063A05Y2, H D63B05Y2CMOS MCU (Microcomputer Unit)-PREll MINARY-The HD6305YI and the HD6305Y2 are CMOS 8-bit singlechip microcomputers. A CPU, a clock generator, a 256 byteRAM, I/O terminals, two timers and a serial communicationinterface (SCI) are built in both chip of the HD6305Y 1 andthe HD6305Y2. Their memory spaces are expandable to 16kbytes externally.The HD6305YI and the HD6305Y2 have the same functionsas the HD630SYO's except for the number of I/O terminals.The HD6305YI has 7872 byte ROM and its memory space isexpandable to 8k bytes externally. The HD6305Y2 is a microcomputerunit which includes no ROM and its memory spaceis expandable to 16k bytes ex tern ally .- HARDWARE FEATURES.8·bit based MCU.7872 bytes of internal ROM (HD6305Y1)No internal ROM (HD6305Y2).256 bytes of RAM• A total of 31 terminals, including 24 I/O's, 7 inputs.Two timers8·bit timer with a 7-bit prescaler (programmable prescaler;event counter)15·bit timer (commonly used with the SCI clock divider).On-chip serial interface circuit (synchronized with clock).Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation modes- Wait .... In this mode, the clock oscillator is on and theCPU halts but the timer/serial/interrupt func·tion is operatable.- Stop .... In this mode, the clock stops but the RAMdata, I/O status and registers are held.- Standby.. I n this mode, the clock stops, the RAM datais held, and the other internal condition isreset.• Minimum instruction cycle timeHD6305Y1/Y2 .. 11ls (f = 1 MHz)- HD63A05Y1/Y2 .. 0.671ls (f = 1.5 MHz)- HD63B05Y1/Y2 .. 0.51ls (f = 2 MHz)• Wide operating rangeVCC = 3 to 6V (f = 0.1 to 0.5 MHz)- HD6305Y1/Y2 .. f = 0.1 to 1 MHz (VCC = 5V ± 100J»- HD63A05Y1/Y2 .. f = 0.1 to 1.5 MHz (VCC = 5V ± 100J»- HD63B05Y1/Y2 .. f = 0.1 to 2 MHz (VCC = 5V ± 100J».System development fully supported by an evaluation kitHD6305Y1P, HD63A05Y1P,HD63B05Y1P, HD6305Y2P,HD63A05Y2P, HD63B05Y2PHD6305Y1F, HD63A05Y1F,HD63B05Y1 F, HD6305Y2F,HD63A05Y2F, HD63B05Y2F(FP·64)• Index addressing mode useful for table processing• A variety of conditional branch instructions• Ten powerful addressing modes• All addressing modes adaptable to RAM, and I/O instructions• Three new instructions, STOP, WAIT and DAA, added to theHD6805 family instruction set• Instructions that are upward compatible with those of Moto·rola's MC6805P2 and MC146805G2-SOFTWARE FEATURES• Similar to HD6800• Byte efficient instruction set• Powerful bit manipulation instructions (Bit Set, Bit Clear, andBit Test and Branch usable for 192 byte RAM bits within pageo and all I/O terminals)• A variety of interrupt operations478 ~HITACHI

HD6305Y1,HD6305Y2• PIN ARRANGEMENT• HD6305Y1P, HD63A05Y1P, HD63B05Y1P,HD6305Y2P, HD63A05Y2P, HD63B05Y2Pvss r--: 0RESINTSTBYXTALEXTALNUMTIMERA7AeAsA.AJAzA,AoB7BeB5B.B3BzB,BoC7/TxC,/RxCliCKC.C3CzC,Co(Top View)~ DATAoB3 DATA,B2 DATAzDATAJDATA.DATAsDATAeDATA7ERtWADR13ADR12ADR"ADR,oADRaADR,ADR7ADReADRsADR.ADR3ADR zADR,AORo0 7O,/i'N'f;0 1O.03Oz0,VCCC,/Tx• HD6305Y1F, HD63A05Y1F, HD63B05Y1F,HD6305Y2F, HD63A05Y2F, HD63B05Y2F....Jc:(~ ~::::> XZ wU uu u~ .{ J.cn~ ~ ~cnc:( c:( c:(> 0 0 0u c5 0 0(Top View).;,~c:(0~~c:(0d 0~~c:(0dDATA6DATA,EADR.ADR,ADR6ADRsADR4ADR3ADR2ADR.ADRo• BLOCK DIAGRAMXTAl EXTAlTIMERPort A1/0TerminalsPort B1/0TerminalsCondition CodeRegisterCCStack6 Pointer SpProgramCounter6 "High" PCHCPUControlIL-L-_D,O./iNT,0,0.. Port 0OJ Input~~ Terminals• No internal ROM in H06305Y2DATA,DATA.DATA,DATA.DATA,DATA2DATA,DATA.~HITACHI479

HD6305Yl,HD6305Y2-------------------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee -0.3-+7.0 VInput Voltage Vin -0.3 - Vee + 0.3 VOperating Temperature Topr 0-+70 °cStorage Temperature Tstg -55 - +150 °c[NOTE)These products heve e protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normaloperation, we recommended Vln, Vout; Vss ~ (V ln or V out ) ~ Vee .• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = ~.OV±10%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)Input "High" VoltageInput "Low" VoltageItemRES,STBYEXTALOther InputsAll InputsOutput "High" Voltage All OutputsOutput "Low" VoltageInput Leakage CurrentThree-state CurrentCurrent Dissipation * *I nput CapacitanceAll OutputsTlMER,INT,0 1 '" 0" STBYAo-A"Bo-B"Co'" C" ADRo '" ADRI3*,E*, R/W*OperatingWaitStopStandbyAll Terminals• Only at standby•• VIH min = Vec-1.OV. VIL max = O.BV••• The value at f = xMHz is given by using.ICC Ct=xMHz) = Icc (f= 1MHz) xxSymbol Test Condition minV 1HVee-0.5VeexO.72.0V 1L -0.3IOH - -200J,LA 2.4V OHIOH = -10J,LA Vee-0.7VOL IOL = 1.6mA -Il ILi -Vin = 0.5 '" V ee-0.5IITS11 -Icc f = 1MHz***----Cin f = 1MHz, Vin = OV -typ max Unit- Vee+0 .3- Vee+0.3 V- Vee+0.3- 0.8 V- -V- -- 0.55 V- 1.0 J,LA- 1.0 J,LA5 10 mA2 5 mA2 10 J,LA2 10 J,LA- 12 pF• AC CHARACTERISTICS (Vee = 5.OV±10%, Vss = OV, Ta = 0 '" +70°C, unless otherwise noted.)ItemSymbolTest HD6305Y1!Y2 HD63A05Y1/Y2Condition min typ max min typ maxCycle Time tcyC 1 - 10 0.666 - 10Enable Rise Time tEr - - 20 - - 20Enable Fall Time tEf - - 20 - - 20Enable Pulse Width("High" Level) PWEH 450 - - 300 - -Enable Pulse Width("Low" Level) PWEL 450 - - 300 - -Address Delay Time tAO Fig. 1 - - 250 - - 190Address Hold Time tAH 20 - - 20 - -Data. Delay Time tow - - 250 - - 160Data Hold Time (Write) tHW 20 - - 20 - -Data Set-up Time (Read) tOSR 80 - - 60 - -Data Hold Time (Read) tHR 0 - - 0 - -HD63B05Y1!Y2min typ maxUnit0.5 - 10 J,Ls- - 20 ns- - 20 ns220 - - ns220 - - ns- - TBD ns20 - - ns- - TBD ns20 - - nsTBD - - ns0 - - ns480 ~HITACHI

-------------------------------------------------------HD6305Yl,HD6305Y2• PORT TIMING (Vee = 5.0V±10%, Vss = OV, Ta = 0'" +70°C, unless otherwise noted.)Port Data Set·up Time(Port A, B, C, D)Port Data Hold TimeTest H D6305Y 1 /Y2 HD63A05Yl/Y2 H D63B05Y 1 /Y2ItemSymbolConditionUnitmin typ max min typ max min typ maxtpDS 200 - - 200 - - 200 - - nsFig.2(Port A, B, C, D) tpDH 200 - - 200 - - 200 - - nsPort Data Delay Time(Port A, B, C)tpDW Fig. 3 - - 300 - - 300 - - 300 ns• CONTROL SIGNAL TIMING (Vee:: 5.0V±10%, Vss:: OV, Ta = 0'" +70 o C, unless otherwise noted.)ItemTest HD6305Yl/Y2 HD63A05Yl/Y2 HD63B05Yl/Y2SymbolUnitCondition min typ max min typ max min typ maxINT Pulse Widtht'WLINT; Pulse Widtht'WL2tcyc+250 +200 +200tcyctcyctcyC- -- -+250 +200 +200- - tCYc - -tcyc- - ns- - nsRES Pulse Width tRWL 5 - - 5 - - 5 - - tCycControl Set-up Time tcs Fig. 5 250 - - 250 - - 250 - - nsTimer Pulse WidthtcyctTWL-tcyc--tcyc+250 +200-+200- - nsOscillation Start Time (Crystal) tosc Fig.5,Fig.20· - - 20 - - 20 - - 20 msReset Delay Time tRHL Fig. 19 80 - - 80 - - 80 - - ms* CL = 22pF ±20%, Rs = 600 max.• SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta = 0'" +70 o C, unless otherwise noted.)Test HD6305Yl/Y2 HD63A05Yl/Y2 H D63B05Y 1 /Y2ItemSymbolUnitCondition min typ max min typ max min typ maxClock Cycle tScyc 1 - 32768 0.67 - 21845 0.5 - 16384 JlSData Output Delay Time tTxD Fig.6, - - 250 - - 250 - - 250 nsData Set-up Time tSRX Fig. 7 200 - - 200 - - 200 - - nsData Hold'rime tHRX 100 - - 100 - - 100 - - ns~HITACHI 481

HD6305Y1,HD6305Y2------------------------------------------------------14-----------tcYC----------.EPWELte,Ao--A13R/W2.4VO.6VtowMCU Write00-07MCU Read00-07Figure 1 Bus TimingE2.4VE'tvtpow/PortA,B,C,DPortA,B,C2.4V DataO.6V ValidFigure 2 Port Data Set-up and Hold Times(MCU Read)Figure 3 Port Data Delay Time (MCU Write)InterruptTestEAddressBusData BusOperand Irrelevantop Cod. DataPCo­PC7\~------------~I~~~or ~s~tor First Inst. ofAddressAddress Interrupt RoutineFigure 4 Interrupt Sequence482$ HITACHI

-----------------------------HD6305Y1,HD6305Y2E~ .. ~~m _~~Veetosc----l --;:Jr ------~~_+--~-----------------~Vee-O.5Vt....--tVee-O.5V~·~ _______ ~-JIL-_IAddressBus-~ 1 FFF 1FFF 1 FFF 1 FFE 1 FFF New PC----R/W __ 'IJ~1FFFData Bus____:.-1------------iI.--~//J/l/11Ih__Figure5 Reset TimingClock OutputCs/CKts cvc2.4VO.6VData OutputC7/TXData InputCs/RXtSRXtHRX -----I2.0VO.8VFigure6 SCI Timing (Internal Clock)tscyCClock InputCs/CK2.0VO.8VData OutputC7/TXtSRXData InputCs/RX2.0VO.8VFigure7 SCI Timing(External Clock)~HITACHI 483

HD6305Y1,HD6305Y2------------------------------------------------------TTL Load(Port)Test pointterminalIOL=1.6mAn---~-----

------------------------------------------------------HD6305Y1,HD6305Y2o63642552563193201,0 PortsTimerSCIRAM(192Bytes)StackRAM(64Bytes)ROM·(7.872Bytes)8182 r----------8191 1'I7!~~~~~t •819216383PushExternalMemory Space1$0000$003Fr040$gOFF$ 100\$013F$0140$lFF6$lFFF$2000$3FFF0 PORT A $001 PORT B SOl2 PORT C S023 PORT 0 S03"4 PORT A DDR S04'5 PORT BOOR S05'6 PORT C DDR $06'Not UsedB Timer Data Reg $089 Timer CTRL Reg $0910 Mise Reg $OANot Used16 SCI CTRL Reg $1017 SCI STS Reg $1118 SCI Data Reg $12Not Used31$lFExternal $20j~\63 Memory Space $3F* Write only regi ster** Read only regi ster• ROM are a ($0140 - $1 FFF) in the HD6305Y2is changed into External Memory Space.Figure 9 Memory Map of MCU765432101 1, I Conditionn-4 n+lCode Registern-3 Accumulator n+2n-2 Index Register n+3n-1 , 1 IPCW n+4n PCl' n+5Pull• In a subroutine call. only PCl and PCH are stacked.Figure 10 Sequence of Interrupt Stacking-REGISTERSThere are five registers which the programmer can operate.7 0A ___ ~I AccumulatorI ...____7 0XI I IndexL. ________ ~Reglster13 0L.. ______________PCI ..I.Counter I Program13 6 5 0~gg~~Zero'-----Negative'--------InterruptMask'---------HalfCarryFigure 11 Programming Model• Accumulator (A)This accumulator is an ordinary 8-bit register which holdsoperands or the result of arithmetic operation or data processing.• Index Register (X)The index register is an 8-bit register, and is used for indexaddressing mode. Each of the addresses contained in theregister consists of 8 bits which, combined with an offsetvalue, provides an effective address.In the case of a read/modify/write instruction, the indexregister can be used like an accumulator to hold operationdata or the result of operation.If not used in the index addressing mode, the register canbe used to store data temporarily.• Program Counter (PC)The program counter is a 14-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 14-bit register that indicates the addressof the next stacking space. Just after reset, the stackpointer is set at address SOOFF. It is decremented when datais pushed, and incremented when pulled. The upper 8 bitsof the stack pointer are fIXed to 00000o 11. During the MCUbeing reset or during a reset stack pointer (RSP) instruction,the pointer is set to address SOOFF. Since a subroutine orinterrupt can use space up to address SOOCI for stacking, thesubroutine can be used up to 31 levels and the interrupt upto 12 levels.• Condition Code Register (CC)The condition code register is a 5-bit register, each bitindicating the result of the instruction just executed. Thebits can be individually tested by conditional branch instruc-_HITACHI 485

HD6305Y1,HD6305Y2------------------------------------------------------tions. The CC bits are as follows:Half Carry (H): Used to indicate that a carry occurred betweenbits 3 and 4 during an arithmetic operation(ADD, ADC).Interrupt (I): Setting this bit causes all interrupts, excepta software interrupt, to be masked. If aninterrupt occurs with the bit I set, it islatched. It will be processed the instantthe interrupt mask bit is reset. (More specifically,it will enter the interrupt processingroutine after the instruction following theCLI has been executed.)Negative (N): Used to indicate that the result of the mostrecent arithmetic operation, logical operationor data processing is negative (bit 7 is logic"1 ").Zero (Z): Used to indicate that the result of the mostrecent arithinetic operation, logical operationor data processing is zero.Carry/ Represents a carry or borrow that occurredBorrow (C): in the most recent arithmetic operation. Thisbit is also affected by the Bit Test and Branchinstruction and a Rotate instruction.-INTERRUPTThere~e six different types of interrupt: external interrupts(INT,. IN.T2), internal timer interrupts (TIMER,TIMER2), senal IOterrupt (SCI) and interrupt by an instruction(SWI).Of these six interrupts, the INT2 and TIMER or the SCIand TIMER2 generate the same vector address, respectively.When an interrupt occurs, the program in progress stopsand the then CPU status is saved onto the stack. And then,the interrupt mask bit (I) of the condition code register isset and the start address of the interrupt processing routineis obtained from a particular interrupt vector address. Thenthe interrupt routine starts from the start address. Systemcan exit from the interrupt routine by an RTI instruction.When this instruction is executed, the CPU status beforethe interrupt (saved onto the stack) is pulled and the CPUrestarts the sequence with the instruction next to the one atwhich the interrupt occurred. Table 1 lists the priority ofinterrupts and their vector addresses.Table 1Priority of InterruptsInterrupt Priority Vector AddressRES 1 $lFFE, $lFFF. --SWI 2 $lFFC, $lFFDINT 3 $lFFA, $lFFBTIMER/INT2 4 $lFF8, $lFF9SCI/TIMER2 5 $lFF6, $lFF7A flowchart of the interrupt sequence is shown in Fig. 12.A block diagram of the interrupt request source is shown inFig. 13.yfliIT-1---+1$FF--SPO--OOR'sCLR INT LogicSFF---.TDR$7F---+ Timer Prescaler$50-.. TCRS3F--SSR$OO--SCRS7F---MRyyTIMERSCIFigure 12 Interrupt Flow Chart486 $ HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2In the block diagram, both the external interrupts INT andINT2 are edge trigger inputs. At the falling edge of each input,an interrupt request is generated and latched. The INT interruptrequest is automatically cleared if jumping is made tothe IN'f processing routine. Meanwhile, the INT2 request iscleared if "0" is written in bit 7 of the miscellaneous register.For the external interrupts (lNT, INT2), internal timerinterrupts (TIMER, TlMER2) and serial interrupt (SCI), eachinterrupt request is held, but not processed, if the I bit of thecondition code register is set. Immediately after the I bit iscleared, the corresponding interrupt processing starts accordingto th~ority.The INT2 interrupt can be masked by setting bit 6 of themiscellaneous register; the TIMER interrupt by setting bit 6of the timer control register; the SCI interrupt by setting bit5 of the serial status register; and the TlMER2 interrupt bysetting bit 4 of the serial status register.The status of the INT terminal can be tested by a BIL orBIH instruction. The INT falling edge detector circuit andits latching circuit are independent of testing by these instructions.This is also true with the status of the INT2 terminal.• Miscellaneous Register (MR; $OOOA)The interrupt vector address for the external interruptINT2 is the same as that for the TIMER interrupt, as shownin Table I. For this reason, a special register called the miscellaneousregister (MR; $OOOA) is available to control theINTl interrupts.Bit 7 of this register is the INT2 interrupt request flag.When the falling edge is detected at the INT2 terminal, "I"is set in bit 7. Then the software in the interrupt routine(vector addresses: $IFF8, $IFF9) checks bit 7 to see if itis INT2 interrupt. Bit 7 can be reset by software.Miscellaneous Register (MR;$OOOA)76543210IM~R61ZVV1Z1Z1Z1~ INTi Interrupt Mask.---------- INT2 Interrupt Request FlagBit 6 is the INT2 interrupt mask bit. If this bit is set to "1",then the INT2 interrupt is disabled. Both read and write arepossible with bit 7 but "I" cannot be written in this bit bysoftware. This means that an interrupt request by softwareis impossible.When reset, bit 7 is cleared to "0" and bit 6 is set to "1" .-TIMERFigure 14 shows a MCV timer block diagram. The timerdata register is loaded by software and, upon receipt of aclock input, begins to count down. When the timer dataBIH/BIL TestINT InterruptLatchVectoring generated$1 FFA. $1 FFBCondition Code Register (CC)INTFalling Edge DetectorITIMER~~~~ ___ Vectoring generated$lFFB.$1FF9Serial StatusRegister (SSR)>---....... --- Vectoring generated$1FF6.$1FF7Figure 13 Interrupt Request Generation Circuitry~HITACHI 487

HD6305Y1,HD6305Y2-------------------------------------------------------register (TDR) becomes "0", the timer interrupt requestbit (bit 7) in the timer control register is set. In response tothe interrupt request, the CPU saves its status into the str.ckand fetches timer interrupt routine address from addresses$1 FF8 and $1 FF9 and execute the interrupt routine. Thetimer interrupt can be masked by setting the timer interruptmask bit (bit 6) in the timer control register. The mask bit(I) in the condition code register can also mask the timerinterrupt.The source clock to the timer can be either an externalsignal from the timer input termin.al or the internal E signal(the oscillator clock divided by 4). If the E signal is used asthe source, the clock input can be gated by the input to thetimer input terminal.Once the timer count has reached "0", it starts countingdown with "$FF". The count can be monitored wheneverdesired by reading the timer data register. This permits theprogram to know the length of time having passed after theoccurrence of a timer interrupt, without disturbing the contentsof the counter.When the MCU is reset, both the prescaler and counter areinitialized to logic "1". The timer interrupt request bit(bit 7) then is cleared and the timer interrupt mask bit (bit6) is set.To clear the timer interrupt request bit (bit 7), it is necessaryto write "0" in that bit.• Timer Control Register (TCR; $0009)Selection of a clock source, selection of a prescaler frequencydivision ratio, and a timer interrupt can be controlledby the timer control register (TCR; $0009).For the selection of a clock source, anyone of the fourmodes (see Table 2) can be selected by bits 5 and 4 of thetimer control register (TCR).Timer Control Register (TCR; $0009)4'------------- Timer interrupt mask-------Timer interrupt requestAfter reset, the TCR is initialized to "E under timer terminalcontrol" (bit 5 = 0, bit 4 = 1). If the timer terminal is"1", the counter starts counting down with "$FF" immediatelyafter reset.When "1" is written in bit 3, the prescaler is initialized.This bit always shows "0" when read.TCR7oTCR6oTimer interrupt requestAbsentPresentTimer interrupt maskEnabledDisabledTable 2 Clock Source SelectionTCRBit 5 Bit4Clock input source0 0 I nternal clock E0 1 E under timer terminal control1 0 No clock input (counting stopped)1 1 Event input from timer terminalInitialize(InternalClock)E --+----13Timer DataRegisterL---"'T'"---......,r----..J Timer InterruptWriteReadFigure 14 Timer Block Diagram488 ~HITACHI

-------------------------------------------------------HD6305Yl,HD6305Y2A prescaler division ratio is selected by the combination ofthree bits (bits 0, 1 and 2) of the timer control register (seeTable 3). There are eight different division ratios: +1, +2, +4,+8, +16, +32, +64 and +128. After reset, the TCR is set to the+1 mode.Table 3TCRBit 2 Bit 1 Bit 0Prescaler Division Ratio SelectionPrescaler division ratio0 0 0 +10 0 1 +20 r 0 +40 1 1 +8A timer interrupt is enabled when the timer interrupt maskbit is "0", and disabled when the bit is "I". When a timerinterrupt occurs, "I" is set in the timer interrupt request bit.This bit can be cleared by writing "0" in that bit.-SERIAL COMMUNICATION INTERFACE (SCI)This interface is used for serial transmission or receptionof 8-bit data. Sixteen transfer rates are available in the rangefrom I iJS to approx. 32 ms (for oscillation at 4 MHz).The SCI consists of three registers, one eighth counter andone prescaler. (See Fig. 15.) SCI communicates with the CPUvia the data bus, and with the outside world through bits 5,6 and 7 of port C. Described below are the operations ofeach register and data transfer.-SCI Control Register (SCR; $0010)1 0 0 +161 0 1 +321 1 0 +641 1 1 +128SCI Control Registers (SCR; $0010)EC5(CK) :,. __ -Di __ ,IIIIIIIIC6(Rx) :~IC7(Tx) :IL ______ ~SCI Data Registers 1.--..,..---'(SOR: $0012)'--....-...... -~TransferClockGeneratorInitializeSCI Status Registers(SSR :$0011)Not UsedSCI/TIMER2Figure 15 SCI Block Diagram~HITACHI489

HD6305Y1,HD6305Y2------------------------------------------------------SCR7aC 7 terminalUsed as I/O terminal (by DDR).Serial data output (DDR output)Bit 7 (SSR7)Bit 7 is the SCI interrupt request bit which is set uponcompletion of transmitting or receiving 8-bit data. It iscleared when reset or data is written to or read from theSCI data register with the SCRS="I". The bit can also becleared by writing "0" in it.SCRSaC 6 terminalUsed as I/O terminal (by DDR).Serial data input (DDR input)SCR5 SCR4 Clock source C s terminala a - Used as I/O terminal (bya 1 -DDR).1 0 Internal Clock output (DDR output)1 1 External Clock input (DDR input)Bit 7 (SCR7)When this bit is set, the DDR corresponding to the C 7becomes "1" and this terminal serves for output of SCI data.After reset, the bit is cleared to "0".Bit 6 (SSR6)Bit 6 is the TIMERz interrupt request bit. TIMERz is usedcommonly with the serial clock generator, and SSR6 is seteach time the internal transfer clock falls. When reset, thebit is cleared. It also be cleared by writing "0" in it. (Fordetails, see TIMERz .)Bit 5 (SSRS)Bit 5 is the SCI interrupt mask bit which can be set orcleared by software. When it is "1", the SCI interrupt (SSR7)is masked. When reset, it is set to "1".Bit 4 (SSR4)Bit 4 is the TIMERz interrupt mask bit which can be setor cleared by software. When the bit is "I", the TIMERzinterrupt (SSR6) is masked. When reset, it is set to "I".Bit 3 (SSR3)When "1" is written in this bit, the prescaler of the transferclock generator is initialized. When read, the bit always is "0".Bit 6 (SCR6)When this bit is set, the DDR corresponding to the C 6becomes "0" and this terminal serves for input of SCI data.After reset, the bit is cleared to "0".Bits 5 and 4 (SCRS, SCR4)These bits are used to select a clock source. After reset,the bits are cleared to "0".Bits 3 - 0 (SCR3 - SCRO)These bits are used to select a transfer clock rate. Afterreset, the bits are cleared to "0".SCR3 SCR2 SCR1 SCRaTransfer clock rate4.aaMHz4.194 MHza a 0 0 1 Ils O.951lSa a a 1 21lS 1.911ls0 a 1 0 41ls 3.82 1lsa a 1 1 81lS 7.S41lsI 1 1 1 1 I1 1 1 1 32768lls 1/32 sBits 2 - 0Not used.SSR7oSSRSoSSR5aSSR4aSCI interrupt requestAbsentPresentTIMERz interrupt requestAbsentPresentSCI interrupt maskEnabledDisabledTIMERz interrupt maskEnabledDisabledeSCI Data Register (SDR; $0012)A serial-parallel conversion register that is used for transferof data.eSCI Statui Regilter (SSR; $0011)76543210ISSR7ISSR6ISSR5ISSR4ISSR3~490 _HITACHI• Data TransmissionBy writing the desired control bits into the SCI controlregisters, a transfer rate and a source of transfer clock aredetermined and bits 7 and 5 of port C are set at the serialdata output terminal and the serial clock tenninal, respectively.The transmit data should be stored from the accumulatoror index register into the SCI data register. The datawritten in the SCI data register is output from the C 7 /Txterminal, starting with the LSB, synchronously with thefalling edge of the serial clock. (See Fig. 16.) When 8 bit of

-------------------------------------------------------HD6305Y',HD6305Y2data have been transmitted, the interrupt request bit is set inbit 7 of the SCI status register with the rising edge of the lastserial clock. This request can be masked by setting bit 5 of theSCI status register. Once the data has been sent, the Bth bitdata (MSB) stays at the C, /Tx terminal. If an external clocksource has been selected, the transfer rate determined bybits 0 "'" 3 of the SCI control register is ignored, and the Cs /CK terminal is set as input. If the internal clock has beenselected, the Cs/CK. terminal is set as output and clocks areoutput at the transfer rate selected by bits 0"'" 3 of the SCIcontrol register.Figure 16 SCI Timing Chart• Data ReceptionBy writing the desired control bits into the SCI controlregister, a transfer rate and a source of transfer clock are determinedand bit 6 and 5 of port C are set at the serial datainput terminal and the serial clock terminal, respectively.Then dummy-writing or -reading the SCI data register, thesystem is ready for receiving data. (This procedure is notneeded after reading subsequent received data. It must be takenafter reset and after not reading subsequent received data.)The data from the C 6 /Rx terminal is input to the SCIdata register synchronously with the rising edge of theserial clock (see Fig. 16). When B bits of data have been received,the interrupt request bit is set in bit 7 of the SCIstatus register. This request can be masked by setting bit 5of the SCI status register. If an external clock source have beenselected, the transfer rate determined by bits 0 .... 3 of the SCIcontrol register is ignored and the data is received synchronouslywith the clock from the C 5 /CK terminal. If the internalclock has been selected, the Cs/CK terminal is set as outputand clocks are output at the transfer rate selected by bits 0 "'"3 of the SCI control register..TIMER2The SCI transfer clock generator can be m:ed as a timer.The clock selected by bits 3 "'" 0 of the SCI control register(4 p.s -- approx. 32 ms (for oscillation at 4 MHz» is input tobit 6 of" the SCI status register and the TIMER2 interruptrequest bit is set at each falling edge of the clock. Since interruptrequests occur periodically, TIMER2 can be used as areload counter or clock.CD-----1 ....... __.....-__ OO;;;.,2@t@@LCD : Transfer clock generator is reset and mask bit (bit 4of SCI stiltus register) is clea red.00. @ : TlMER2 interrupt request@. @ : TIMER2 interrupt request bit clearedTIMER2 is commonly used with the SCI transfer clockgenerator. If wanting to use TIMiRi independently of theSCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCIclock source.If "Internal" is selected as the clock source, reading orwriting the SDR causes the' prescaler of the transfer clockgenerator to be initialized.-I/O PORTSThere are 24 input/output terminals (ports A, B, C). EachI/O terminal can be selected for either input or output by thedata direction register. More specifically, an I/O port willbe input if "0" is written in the data direction register, andoutput if "1" is written in the data direction register. Port A,B or C reads latched data if it has been programmed as output,even with the output level being fluctuated by the outputload. (See Fig. 17.)When reset, the data direction register and data register goto "0" and all the input/output terminals are used as input .Bit of datadirectionregisterBit ofoutputdataStatus ofoutputInput toCPU1 0 0 01 1 1 10 X 3-state PinFigure 17Input/Output Port DiagramSeven input-only terminals are available (port D). Writingto an input terminal is invalid.All input/output terminals and input terminals are TTLcompatible and CMOS compatible in respect of both input andoutput.If I/O ports or input ports are not used, they should beconnected to VSS via resistors. With none connected to theseterminals, there is the possibility of power being consumeddespite that they are not used.-RESETThe MCV can be reset either by external reset input (RES)or power-on reset. (See Fig. lB.) On power up, the resetinput must be held "Low" for at least tose to assure that theinternal oscillator is stabilized. A sufficient time of delay canbe obtained by connecting a capacitance to the RES input asshown in Fig. 19.~HITACHI 491

HD6305Y1,HD6305Y2------------------------------------------------------SVvccOV./~ --RES /' VIH RESTerminal --------1"'"- tRHL r---~:::;al ____________________ ~Figure 18 Power On and Reset Timingrequirement for minimum external configurations. It can bedriven by connecting a crystal (AT cut 2.0 - 8.0MHz) orceramic oscillator between pins 5 and 6 depending on the reoquired oscillation frequency stability.Three different terminal connections are shown in Fig. 20.Figs. 21 and 22 illustrate the specifications and typical arrangementof the crystal, respectively.AT CutParallelResonanceCo=7pF max.f=2.0-8.0MHzRs=600 max.100kSl typ 2Vee -V'V'V---+':=::--IRESHD6305YMCU *2.2J.1F(a)Figure 21Parameters of CrystalFigure 19Input Reset Delay Circuit-INTERNAL OSCILLATORThe internal oscillator circuit is designed to meet the6 EXTALIH:l-oM-H-zC] .......-s-t XTAL10-22pF±20%HD6305YMCU[NOTE) Use as short wirings as possible for connection of the crystalwith the EXTAL and XTAL terminals. Do not allow thesewirings to cross others.Figure 22Typical Crystal Arrangement-LOW POWER DISSIPATION MODEThe HD630SY has three low power dissipation modes:wait, stop and standby.492Crystal OscillatorHD6305YMCUExternal Ceramic OscillatorClockInput 6 EXTALNC S XTAL HD6305YMCUExternal Clock DriveFigure 20 Internal Oscillator Circuit~HITACHI• Wait ModeWhen W AIr instruction being executed, the MCU entersinto the wait mode. In this mode, the oscillator stays activebut the internal clock stops. The CPU stops but the peripheralfunctions - the timer and the serial communication inter·face - stay active. (NOTE: Once the system has entered thewait mode, the serial communication interface can no longerbe retriggered.) In the wait mode, the registers, RAM and I/Oterminals hold their condition just before entering into thewait mode.The escape from this mode can be done by interrupt (INT,TIMER/INT2 or SCI/TIMER2), RES or STBY. The RESresets the MCU and the STBY brings it into the standbymode. (This will be mentioned later.)When interrupt is requested to the CPU and accepted, thewait mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interrupt ismasked by the I bit of the condition code register, after releasingfrom the wait mode the MCU executes the instructionnext to ~WAIT. If an interrupt other than the INT (Le.,TIMER/INT2 or SCI/TIMER2) is masked by the timer control

-------------------------------------------------------HD6305Y1,HD6305Y2register, miscellaneous register or serial status register, thereis no interrupt request to the CPU, so the wait mode cannotbe released.Fig. 23 shows a flowchart for the wait function.• Stop ModeWhen STOP instruction being executed, MCU enters intothe stop mode. In this mode, the oscillator stops and the CPUand peripheral functions become inactive but the RAM,registers and I/O terminals hold their condition just beforeentering into the stop mode.The escape from this mode can be done by an externalinterrupt (INT or (NTl), RES or STBY. The RES resets theMCU and the STBY brings into the standby mode.When interrupt is requested to the CPU and accepted,the stop mode escapes, then the CPU is brought to the operationmode and vectors to the interrupt routine. If the interruptis masked by the I bit of the condition code register,after releasing from the stop mode, the MCU executes theinstruction next to the STOP. If the INTl interrupt is maskedby the miscellaneous register, there is no interrupt request tothe MCU, so the stop mode cannot be released.Fig. 24 shows a flowchart for the stop function. Fig. 25shows a timing chart of return to the operation mode fromthe stop mode.For releasing from the stop mode by an interrupt, oscillationstarts upon input of the interrupt and, after the internaldelay time for stabilized oscillation, the CPU becomes active .For restarting by RES, oscillation starts when the RES goes"0" and~ CPU restarts when the RES goes "I". The durationof RES="O" must exceed 30 ms to asslIre stabilized oscillation.• Standby ModeThe MCU enters into the standby mode when the STBYterminal goes "Low". In this mode. all operations stop andthe internal condition is reset but the contents of the RAM arehold. The I/O terminals turn to high-impedance state. Thestandby mode should escape by bringing sfBv "High". TheCPU must be restarted by reset. The timing of input signalsat the RES and STBY terminals is shown in Fig. 26.Table 4 lists the status of each parts of the MeU in eachlow power dissipation modes. Transitions between each modeare shown in Fig. 27.$ HITACHI 493

HD6305Y1,HD6305Y2------------------------------------------------------Oscillator ActiveTimer and SerialClock ActiveAll Other ClocksStopInitializeCPU, TIMER, SCI,1/0 and AllOther FunctionsNoNo1=1Load PC fromInterrupt VectorAddressesFetchInstructionFigure 23 Wait Mode Flow Chart494_HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2Stop Oscillatorand All ClocksNoTurn on OscillatorWait for Time Delayto StabilizeTurn on OscillatorWait for Time Delayto Stabilize1=11=0Load PC fromInterrupt VectorAddressesFetchInstructionFigure 24 Stop Mode Flow Chart~HITACHI495

~_~ ______________________HD6305Y1,HD6305Y2----------------------------------------------------__Oscillator ""I"" 111111111111" 111/1II 7 adfTlllllllllllllllllllllllllllllllllllllllllllllllllllll1111STOP instructionexecutedTime required for oscillation to becomeInterrupt stabilized (built-in delay time)(a) Restart by Interrupt~tionsrestartOscillator 11111111111111111111111111111 II 41111111111111111111111111111/1111/111/111111111111/1111//E/~I~----'~ISTOP instructionexecutedTime required for oscillation to becomestabilized (tosc)'~I start(b) Restart by ResetFigure 25 Timing Chart of Releasing from Stop Mode\'--------;Hr-_----'I,IIII I I ~ __ I ~~~~~--JtoscRestartFigure 26Timing Chart of Releasing from Standby ModeTable 4Status of Each Part of MCU in Low Power Dissipation ModesModeWAIT-STOP498StandbySoftwareHard-WlteConditionStart Oscil- Timer, 1/0 EscapeCPURegister RAMlatorSerialterminalWAIT instructionSTOP InstrIJctionSTBY, RES, INT, INI2,Active Stop Active Keep Keep Keep each interrupt request ofTIMER, TIMER~, SCIStop Stop Stop Keep Keep Keep STBY, AU, INT, INT2S'fIV=" Low" Stop StOP Stop Reset Ke&p_HITACHIHigh im-pedanteSTIY","High"

-----------------------------------------------------HD6305Y1,HD6305Y2Figure 27Transitions among Active Mode, Wait Mode,Stop Mode, Standby Mode and Reset-BIT MANIPULATIONThe MCV can use a single instruction (BSET or BCLR) toset or clear one bit of the RAM within page 0 or an I/O port(except the write-only registers such as the data directionregister). Every bit of memory or I/O within page 0 ($00 '"$FF) can be tested by the BRSET or BRCLR instruction;depending on the result of the test, the program can branch torequired destinations. Since bits in the RAM on page 0, or I/Ocan be manipulated, the user may use a bit within the RAM onpage 0 as a flag or handle a single I/O bit as an independentI/O terminal. Fig. 28 shows an example of bit manipulationand the validity of test instructions. In the example, the programis configured assuming that bit 0 of port A is connectedto a zero cross detector circuit and bit I of the same port tothe trigger of a triac.The program shown can activate the triac within a time of10/-ts from zero-crossing through the use of only 7 bytes onthe ROM. The on-chip timer provides a required time ofdelay and pulse width modulation of power is also possible.SE IF 1. BRClR 0, PORT A, SELF 1BSET 1 , PORT ABClR 1, PORT AFigure 28 Example of Bit Manipulation-ADDRESSING MODESTen different addressing modes are available to the MCU.elmmediateSee Fig. 29. The immediate addressing mode providesaccess to a constant which does not vary during execution ofthe program.This access requires an instruction length of 2 bytes. Theeffective address (EA) is PC and the operand is fetched fromthe byte that follows the operation code.eDirectSee Fig. 30. In the direct addressing mode, the address ofthe operand is contained in the 2nd byte of the instruction.The user can gain direct access to memory up to the lower255th address. 192 byte RAM and I/O registers are on page 0of address space so that the direct addressing mode may beutilized.e ExtendedSee Fig. 31. The extended addressing is used for referencingto all addresses of memory. The EA is the contents ofthe 2 bytes that follow the operation code. An extendedaddressing instruction requires a length of 3 bytes.eRelativeSee Fig. 32. The relative addressing mode is used withbranch instructions only. When a branch occurs, the programcounter is loaded with the contents of the byte following theoperation code. EA = (PC) + 2 + Rei., where ReI. indicates asigned 8-bit data following the operation code. If no branchoccurs, ReI. = O. When a branch occurs, the program jumpsto any byte in the range + 129 to -127. A branch instructionrt:quires a length of 2 bytes.elndexed (No Offset)See Fig. 33. The indexed addressing mode allows accessup to the lower 255 th address of memory. In this mode, aninstruction requires a length of one byte. The EA is thecontents of the index register.$ HITACHI 497

HD6305Y1,HD6305Y2-------------------------------------------------------elndexed (S·bit Offset)See Fig. 34. The EA is the contents of the byte follow·ing the operation code, plus the contents of the index register.This mode allows access up to the lower 511 th address ofmemory. Each instruction when used in the index addressingmode (8·bit offset) requires a length of 2 bytes.elndexed (16-bit Offset)See Fig. 35. The contents of the 2 bytes following theoperation code are added to content of the index registerto compute the value of EA. In this mode, the completememory can be accessed. When used in the indexed address·ing mode (16-bit offset), an instruction must be 3 bytes long.e Bit Set/ClearSee Fig. 36. This addressing mode is applied to the BSETand BCLR instructions that can set or clear any bit on pageO. The lower 3 bits of the operation code specify the bit tobe set or cleared. The byte' that follows the operation codeindicates an address within page O.e Bit Test and BranchSee Fig. 37. This addressing mode is applied to the BRSETand BRCLR instructions that can test any bit within page 0and can be branched in the relative addressing mode. Thebyte to be tested is addressed depending on the contents ofthe byte following the operation code. Individual bits withinthe byte to be tested are specified by the lower 3 bits of theoperation code. The 3rd byte represents a relative value whichwill be added to the program counter when a branch conditionis established. Each of these instructions should be 3 byteslong. The value of the test bit is written in the carry bit of thecondition code register.elmpliedSee Fig. 38. This mode involves no EA. All informationneeded for execution of an instruction is contained in theoperation code. Direct manipulation on the accumulatorand index register is included in the implied addressing mode.Other instructions such as SWI and RTI are also used in thismode. All instructions used in the implied addressing modeshould have a length of one byte.MemorymOGC .... ,,~:F~:~ I ~I~· .,· .Figure 29Example of Immediate AddressingAI FaIndex RegIStack PointProg Count05COccMemoryACATFCB32004Bt:~c::j------+_------~~---------{~~2~0::JIndex egPROG LOA CAT 0520 t-::~t:::::t------.J052E I-~• IIIIIII•IStack PointProg !ount052FCCFigure 30Example of Direct Addressing498 $ HITACHI

--------------------------------------------------------HD6305Y1,HD6305Y2Memory0000A40Index RegIStack PointCATFCB6406E5~::4~0L:~~--------------~Prog Count040CCCFigure 31Example of Extended AddressingPROG BEQ PROG2 g:~~ I--':;';"'-oofFigure 32Example of Relative AddressingMemoryATABlFCC 1I OOBBt:::~:::t----~~~------1_-----------[~~;:~§,"OG CDX X 0'"§. .Figure 33Stack PomtProg Count05F5CCExample of Indexed (No Offset) Addressing~HITACHI 499

HD6305Y1,HD6305Y2:------------------------------------------------------"" mr--Memory~~ ~l:t:: 1rCB CF OOBC: CF : ,_OlOCE:3-'P

------------------------------------------------------HD6305Y1,HD6305Y2PORT C EQU 2. 00021---:..FO~~ I.c; __ ~AInde. RegIStack POintPROG BRCLR 2.PORT C.PROG 2 g~~:I---;;~~~--10576 ........;,1;;,,0_ _1Figure 37Example of Bit Test and Branch AddressingMemory~,"OG TAX 0'" ~§§· .Figure 38Example of Implied Addressing-INSTRUCTION SETThere are 62 basic instructions available to the HD6305YMeU. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, andcontrol. The details of each instruction are described inTables 5 through II.• Register/Memory InstructionsMost of these instructions use two operands. One operandis either an accumulator or index register. The other is derivedfrom memory using one of the addressing modes used on theHD6305Y MeU. There is no register operand in the unconditionaljump instruction (JMP) and the subroutine jumpinstruction (JSR). See Table 5.• Read/Modify/Write InstructionsThese instructions read a memory or register, then modifyor test its contents, and write the modified value into thememory or register. Zero test instruction (TST) does notwrite data, and is handled as an exception in the read/modify/write group. See Table 6.• Branch InstructionsA branch instruction branches from the program sequencein progress if a particular condition is established. See Table 7.• Bit Manipulation InstructionsThese instructions can be used with any bit located up tothe lower 255th address of memory. Two groups are available;one for setting or clearing and the other for bit testing andbranching. See Table 8.• Control InstructionsThe control instructions control the operation of the MeUwhich is executing a program. See Table 9.• List of Instructions in Alphabetical OrderTable to lists all the instructions used on the HD6305YMeU in the alphabetical order.• Operation Code MapTable 11 shows the operation code map for the instructionsused on the MeU.~HITACHI 501

HD6305Y1,HD6305Y2------------------------------------------------------Table 5 Register/Memory InstructionsOperationsMnemonicAddressing ModesIndexed Indexed IndexedImmediate Direct Extended (No Offset) (S·Bit Offset) (IS·Sit 0fI1e1)OP II - OP II - OP II - OP - OP - OP II -Boolean/ArithmeticOperationConditionCodeSymbols: Op - Operation# - Number of bytes- ~ Number of cyclesIncrementDecrementClearComplementNeglleOperations(2's Complement)Rotlte Left Thru CarryRot.te Right Thru C.rryLogic.1 Shift LeftLogic.1 Shift RightArithmetic Shift RightArithmetic Shift LeftT .. t for NeQ.tiveor zeroI MnemonicIINCDECCLRCOMNEGROLRORLSLLSRASRASLTSTSymbols: Op - Oper.tlon# - Number of bytes- - Number of cyclesTable 6 Read/Modify/Write InstructionsAddressing ModesIndexedIndexedImplied(AI Implied(X) Direct (No Offset) (S·Bit OffsetlOP II - OP II - OP II - OP II - OP II -Boolean/Arithmetic Operation4C I 2 5C I 2 3C 2 5 7C I 5 6C 2 6 A+I·-A or X+I~X or M+I~M4A 1 2 5A 1 2 3A 2 5 7A 1 5 6A 2 6 A-1 ~A or X-1~X or M-1~M4F 1 2 5F 1 2' 3F 2 5 7F 1 5 6F 2 6 OO-A or OO~X or OO~M43 1-2 53 1 2 33 2 5 73 1 5 63 2 6 A~A or X-.X or M~MOO-A~A or OO-X~X40 1 2 50 1 2 30 2 5 70 1 5 60 2 6 or OO-M~M49 1 2 59 1 2 39 2 5 79 1 5 69 2 6LO-( I46 1 2 56 1 2 36 2 5 76 1 5 66 2 6Aor i .. 11II I I I ~~l-0-tl IAr~":MI ["WC b, ...48 1 2 58 1 2 38 2 5 78 1 5 68 2 6D-1 I ~,,:xr~ I I t- ob,74!!= C44 1 2 54 1 2 34 2 5 1 5 64 2 6 0., I IA~3·:MI I KJ[?b'... C47 1 2 57 1 2 37 2 5 77 1 5 67 2 6: I IA~~-:MI I 1-048 1 2 58 1 2 38 2 5 78 1 5 68 2 6 Equal to LSL40 1 2 50 1 2 3D 2 4 70 1 4 80 2 5 A-OO IIr X-OO or M-OO••ConditionCodeH I N Z C1\ 1\I, I'•0 1 •• 1\ 1/\ /\ /\• •/\ ,~ 1\• •/\ /\ /\• •/\ /\ /\• •• • 0 /\ 1\/\ 1\ /\• •1\ 1\ /\• •• • •1\ 1\502_HITACHI

------------------------------------------------------HD6305Y1,HD6305Y2Table 7 Branch InstructionsOperationsBranch AlwaysBranch NeverBranch IF HigherBranch IF Lower or SameBranch IF Carry Clear(Branch IF Higher or Same)Branch IF Carry Set(Branch IF Lower)Branch IF Not EqualBranch IF EqualBranch IF Half Carry ClearBranch IF Half Carry SetBranch IF PlusBranch IF MinusBranch IF Interrupt MaskBit is ClearBranc~ IF Interrupt MaskBit is SetBranch IF Interrupt Lineis LowBranch IF Interrupt Lineis HighBranch to SubroutineSymbols: Op .. Operation# .. Number of bytes- .. Number of cyclesMnemonicBRABRNBHIBLSBCC(BHS)BCS(BLO)BNEBEQBHCCBHCSBPLBMIBMCBMSBILBIHBSRAddressing ModesRelativeOP # -20 2 3 None21 2 3 None22 2 3 C+Z=O23 2 3 C+Z=124 2 3 C=O24 2 3 C=O25 2 3 C=125 2 3 C=126 2 3 Z=O27 2 3 Z=128 2 3 H=O29 2 3 H=12A 2 3 N=O2B 2 3 N=12C 2 3 1=020 2 3 1=12E 2 3 INT=O2F 2 3 INT=1AD 2 5 --Branch TestCondition CodeH I N Z C• • • • •• • • • •• • • • •• • • • •• • • • •OperationsMnemonicBranch IF Bit n is set BRSET n(n =0···7)Branch IF Bit n is clear BRClR n(n=0 .. ·7)Set Bit n BSET n(n=0 ..·7)Clear Bit n BClR n(n=0 .. ·7)Symbols: Op" ()peration# • Number of bytes- .. Number of cyclesTable 8 Bit Manipulation InstructionsAddressing ModesBoolean/Bit Set/Clear Bit Test and Branch ArithmeticOP # - OP #!- Operation-- -- --2'n 3 5 -- - 01 +2·n 3 5 -10+2·n 2 5_.- -- -- 1--Mn11 +2·n 2 5 - - - O--MnBranchTestCondition CodeH I N Z CMn=1• • • • /\Mn=O• • • • /\-• • • • •- • • • • •.,.HITACHI503

HD6305Y1,HD6305Y2------------------~------------____________________ __Table 9 Control InstructionsAddressing ModesOperations Mnemonic Implied Boolean OperationCondition CodeOP # - H I N Z CTransfer A to X TAX 97 1 2 A--+X Transfer X to A TXA 9F 1 2 X--+A •Set Carry Bit SEC 99 1 1 1--+C 1Clear Carry Bit CLC 98 1 1 O--+C • 0Set Interrupt Mask Bit SEI 9B 1 2 1--1• 1 • • •Clear Interrupt Mask Bit CLI 9A 1 2 0--+1 0 Software Interrupt SWI 83 1 10 1 Return from Subroutine RTS 81 1 5• • • • •Return from Interrupt RTI 80 1 8 ? ? ? ? ?Reset Stack Pointer RSP 9C 1 2 $FF--+SP• • • • •No-O.peration NOP 90 1 1 Advance Prog. Cntr. Only • • •Decimal Adjust A oAA 80 1 2 Converts binary add of BCD charcters intoBCD format A A A*Stop STOP 8E 1 4 Wait WAIT 8F 1 4• • • • •Symbols: Op· Operation41 - Number of bytes- • Number of cycles• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)Table 10 Instruction Set (in Alphabetical Order)Addressing ModesBit BitMnemonic Indexed Indexed Indexed Set! Test &Condition CodeImplied Immediate Direct Extended Relative (No Offset) (S-Bit) (16-Bit) Clear Branch H I N Z CADC x x x x x X 1\ 1\ 1\ 1\ADD x x x x x X 1\ /\ 1\ 1\•AND x x x x x x •1\ 1\ASL x x x x 1\ 1\ 1\ASR x x x x 1\ 1\ 1\BCC x BCLR x BCS x BEQ x BHCC x BHCS x • • • • •BHI x (BHS) x BIH x BIL x• • • • •BIT x x x x x x 1\ 1\(BLO) x BL'S x BMC x BMI x • • • • •BMS x BNE x BPL x BRA x• • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry/BorrowI Interrupt Mask 1\ Test and Set if True. Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack(to be continued)504$ HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2Table 10 Instruction Set (in Alphabetical Order)Addressing ModesMnemonic Indexed Indexed Indexed SetlIrnplied Immediate Direct Ext!:: .. ,ad Relative (No Offset) (S·Bit) (16·Bit) ClearBRNxBRCLRBRSETBSETBSRCLCxCLIxCLR x x x xCMP x x x x x xCOM x x x xCPX x x x x x xDAAxxBitxBitTest 8&Condition CodeB~nch H I N Z C• • • • •xx• • • • •• • • • 0.0. . .• .01 •• • !\ !\ /\DEC x x x x • • !\ 1\ •EOR x x x x x x • • /, !\ •-1-N-C-------+----x----+-------~---x--~-------r------+----x----+---x---1------~------+------~.~-.~-,-\-+-~-r;-·. /\ /' '.-----+-.-+--.~-. -.-~Condition Code Symbols:H Half Carry (From Bit 3)I Interrupt MaskN Negative (Sign Bit)Z ZeroC!\•?Carry BorrowTest and Set if True. Cleared OtherwiseNot AffectedLoad CC Register From Stack_HITACHI505

HD6305Y1,HD6305Y2------------------------------------------------------(NOTES)1. "-" is an undefined operation code.2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).The number of cycles for the mnemonics asterisked (-) is as follows:ATI 8 TAX 2ATS 5 ASP 2SWI 10 TXA 2DAA 2 BSA 5STOP 4 eLi 2WAIT 4 SEI 23. The parenthesized numbers must be edded to the cycle count of the particular instruction.• Additional InstructionsThe following new instructions are used on the HD6305Y:DAA Converts the contents of the accumulator into BCDcode.WAIT Causes the MCU to enter the wait mode. For this mode,see the topic, Wait Mode.STOP Causes the MeU to enter the stop mode. For this mode,see the topic, Stop Mode.506 _HITACHI

HD63L05F1-------------­CMOS MCU (Microcomputer Unit)The HD63L05Fl is a CMOS single-chip microcomputer suitablefor low-voltage and low-current operation. Having CPUfunctions similar to those of the HMCS6800 family, theHD63L05Fl is equipped with a 4k bytes ROM, 96 bytes RAM,I/O, timer, 8 bits A/D, and LCD (7 x 7 segments max.) drivers,all on one chip.HD63L05F1P• HARDWARE FEATURES• 3V Power Supply• 8-B it Architecture• Built-in 4k Bytes ROM (Mask ROM)• Built-in 96 Bytes RAM• 20 Parallel I/O Ports• Built-in 7 x 7 Segments LCD Driver Capability• Built-in 8-Bit Timer• Built-in 8-Bit A/D Converter• Program Halt Function for Low Power Dissipation• Stand-by Input Terminal for Data HoldingHD63L05F1F(DP-64S)• SOFTWARE FEATURES• An Instruction Set Similar to That of The HMCS6800Family (Compatible with The HD6805S)• HMCS6800 Family Software Development System is Applicable• PIN ARRANGEMENT (Top View)XOUT r; 0NUM ~TIMER 'iVRH tVRL iCC I ~CC2 ~NC ~E 9VCH ~CHilIVtlCH,/OI9 12SEG1'7/CH2SEG 16 /CH 3 1V2 /CHs /OIS 'SEG 15 /CH 4 1NCSEG I4 /CHs 1SEG 13 /CH 6 1SEG 12SEG ll 1SEG IOSEG,SEG 8SEG,SEG 6SEGsSEG 4SEG 3SEG2HD63L05F1PSEGI ~NC -~"'-______ ..r-XINVeeSB1 INTRESVssEXTALXTALNCA,A6AsA41 A3A2I AlAoB,4' ::~ B4B3B21 BlBoC3C237 ClCoCOM 3COM 2COM INCNCVssRESiNTS8NCVccXINNCNCVAHVALCC,CC,NCEVCH(FP·80)HD63L05F1F64 NC638,62 8,, NC6 C,• C,s C,!l1 CoS COM,S NCS COM,S COM,4, SEG.~HITACHI507

HD63L05F1-----------------------------------------------------------• BLOCK DIAGRAMXINXOUTFiESCommonDriverOutputCOM.COMaCOM,DataSEG.LatchLCD1SEGa8 SEG,LCD2SEG.8 ; SEG,g. SEG6LCD3 ;:,0 SEG,SEG.,~LCD4 0 SEG,7 E SEG.o•7LCD5LCD6~ SEG ..SEG.aJJSEG.,SEGI.NUM SEG ..TIMER 7 LCD7 SEG 164 LCDS SEG.,Sc0O;;;ca~;cOAccumulator8 !A -CHi8~:5 (CHz)(JIndex(CH,)0Register(CH.)AoSystem oe

---------------------------------------------------------------HD63l05F1• ABSOLUTE MAXIMUM RATINGSItemSupply VoltageInput VoltageOutput VoltageOperating TemparatureStorage TemparatureSymbolVeeYinVoutToprTstgValue-0.3'" +5.5-0.3'" V ee+0.3-0.3'" Vee+o.3Unit-20'" +75 °c-55'" +125 °cVVV(NOTE IPermanent LSI damage may occur if maximum ratings are exceeded.Normal operation should be under recommended operating conditions.If these conditions are exceeded. it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS (Vee = 3.0V ±O.SV, Vss = OV, Ta = -20'" +75"C, typ means typical value at Vee = 3.0V,unless otherwise noted.)• DC CHARACTERISTICSItem Symbol Test Condition min typ max UnitXTAL, XINConnect CL - 0.5~F toVee -O·3 - Vee VVeHInput "High" RES, INT, S8 V IH 0.5Vee+0.9 - Vee VLevel VoltageTIMER O.aVee - Vee VNUM (Normal Mode) Vee -O·2 - Vee VXTAL, XINConnect CL = 0.5~F toVee -2.1V eH- Vee-1.a VInput "Low" RES,INT, S8 V IL Vss - 0.2Vee VLevel VoltageTIMER Vss - 0.2Vee VSelf Check InputVoltage---Input Pull·UpCurrentInput LeakageCurrentNUM (Test Mode) Vss - 0.2 VNUM (Self Check Mode) VIM 0.5Vee-0.2 - 0.5Vee+0.2 Vm (TNT: Mask Op·tion) -IR1 Vee = 3.0V, Yin = OV 3 15 30 ~ANUMTIMER, S8 IIINI V in = OV '" Vee - - 1.0 ~ADuringSystemf = 400kHz - 100 200 ~AOperationCrystal*No load.Oscilla· At Halt lee1 Tested after setting - 40 ao ~Ation At Standby up the internal status - 2 5 ~AAt AIDby self check.Current Dissipa' Operation - 200 600 ~AtionDurIngSystemR = 100kil - 120 200 ~AOperationRC*No load.Oscilla· At Haltlee2 Tested after setting - 60** 100** ~Ation At Standby up the internal status - 2 5 ~AAt AIDby self check.Operation- 220 600 ~AOutput "Low"Level VoltageE VOL IOL = 30~A - - 0.3 V* Depends on the mask-option.** 60j.lA ~ 30j.lA and 1 OOj.lA ~ 60j.lA when OSC1 is stopped by Halt.$ HITACHI 509

HD63L05F1---------------------------------------------------------------• AC CHARACTERISTICSItem Symbol Test Condition min typ max UnitOperating Clock Frequency fel 100 400 500 kHzCycle Time teye 8 10 40 p.sOscillation Frequency •(Resistor Option)fOSCR R = 100kn ±1% 300 400 500 kHzExternal Clock Duty Duty 45 50 55 %Oscillation Start Time •(Crystal Option)tOSCf Co = 10pF ±20%, Rs = lkn max - - 150 msOscillation Start Time •R = 100kn ±1%,(Resistor Option)tOSCR- - 2 msConnect CL = 0.5J,LF to V CHOscillation Start Time (32kHz)· tOSC1 CD = 10pF ±20%, Rs = 20kn max - - 1 sI nternal Capacitance I EXTAL - 10 - pFof OscillatorCD- 10 - pFJ XOUTDelay Time of Oscillation DelayTime •toLY Selected by mask option0 - 1 sReset Delay Time tRLH External Capacitance = 2.2p.F 200 - - msRES Pulse Width·INT Pulse Width·tRwLtlWLWith 32kHz OSC 48 - - p.sWithout 32kHz OSC 1.5tcyc + 1 - - p.sWhen OSCl is not stopped by Halt tcye+ 1 - - J,LsWhen OSCl is stopped by Halt 32 - - J,LSTIMER Pulse Width tTWL In the case of counter tcye+ 1 - - J,Ls* Depends on mask-option.• PORT CHARACTERISTICSOutput "High" Level Voltage *Item Symbol Test Condition min typ max UnitPort A, a, C CMOS Output, IOH = -100J,LA Vcc-O·3 - - VPort A, a, CVOH Key Load CMOS Output Vcc-O·3 - - VIOH = .-10J,LAOutput"Low" Level Voltage Port A, a, C VOL IOL = 100J,LA - - 0.3 VInput "High" Level Voltage Port A, a, C V IH 0.8Vce - Vee VInput "Low" Level Voltage Port At at C V IL Vss - 0.2Vcc VInput Leakage Current Port A, at C IIINI V in = OV ..... Vee - - 1.0 J,LA._._------Input Pull-Up Current· Port At at C -IR2 Vee = 3.0Vt V in = OV 4 20 40 J,LA• Depends on mask-option.510 ~HITACHI

-----------------------------------------------------------------HD63L05F1• LCD DRIVER OUTPUT CHARACTERISTICS (Vee = 3.0V, Vss = OV, Ta = -20'" +75°C, unless otherwise noted,)Item Symbol Test Condition min typ max UnitVOHl 2.8 - - VV I = 1 .OOV, V 2 = 2.00VOutput "High" Level Voltage Segment VOH21.8 - - VIOH = -11lAVOH3 0.8 - - VV OL1 - - 2.2 VV I = 1 .OOV, V 2 = 2.00VOutput "Low" Level Voltage Segment VOL2- - 1.2 VIOL = 11lAVOL3 - - 0.2 V----V OHl 2.8 - - V----- VIOutput "High" Level Voltage Common= 1.00V, V 2 = 2.00VVOH21.8 VIOH = - --51lAV OH3 0.8 - - VOutput "Low" Level Voltage Common VOL2--------_.--_.---VOLl - - 2.2 VVI = 1.00V, V 2 = 2.00V- - 1.2 VIOL = 51lAVOL3 - - 0.2 VDividing Resistor RLcc Tested between V I and V 2 45 90 180 kilOutput "High" Level Voltage * SegmentV OHOutput "Low" Level Voltage* Segment VOL• Depends on mask-option.In the case of Output Port,IOH = -301lAIn the case of Output Port,IOL = 30llAVcc-0.3 - - V- - 0.3 VVeeVOHlO.l/1FV2Common OutputVOH2VOH3VtSegment OutputVssOutput Level of SEG and COMPower Supply Circuit for LCD Display$ HITACHI 511

HD63L05F1---------------------------------------------------------------• AID CONVERTER CHARACTERISTICSConversion AccuracyItemResolutionAbsolute Accuracy"High" Side(Vee· 3.0V, Vss • OV, Ta· _20°C - +7SoC, unles. otherwise noted.)SymbolV RHReference Voltage "Low" Side V RLInput Voltage RangeLadder Resistor (V RH - VRdConversion TimeProgrammableVoltage ComparisonV RH - V RLInput RangeInput Dynamic RangeJudge ErrorJudge Time~VREFVINVOYNRHLtCNVtCMPTest Condition min typ max- - 8V RL = 0.2V

-----------------------------------------------------------HD63L05F1• SIGNALSThe input and output signals of the MCV are described inthe following:• Vee, VssPower is applied to the MCV at these two terminals. Veeis a positive power input port and V ss is grounded.• INTThis terminal is used to envoke an external interruption tothe MCV. For details, see the information given under the title,"Interruptions" (LNegative going edge type).• XT AL, EXT ALThese are control input ports to the built-in clock circuit.A crystal or a resistor is connected to each of them dependingon the degree of stability of the internal oscillation. For themethod of using the input terminals, see the information,"Internal Oscillator Option".• XIN, XOUTThese terminals are con"nected to a crystal for the oscillatoron the time base. A clock operation is possible by using a32.768kHz crystal. For details, see "Internal Oscillator Option".• TIMERAn external input terminal at which the internal timer iscounted down. For details, see the information, "Timer".• RESVsed to reset the MCV. For details, see "Reset".• STANDBY (SB)An external input terminal used to stop the MCV and holddata. For details, see "Internal Oscillator Option".• AID Input Terminals (CH I .... CHs)Input terminals for analog voltages needed for A/D conversion.These may also be used as level check inputs under programcontrol. For details, see the information, "A/D Converter".Mixing segment driver with output port is not available inmask-option.• VI, V 2These are terminals for LCD driver. V I and V 2 are connectedto Vee via capacitors (O.I/-LF each). These two terminals can beused as output or analog inputs by mask-option when segmentsare used as output ports.• VCHOutput terminal from internal voltage regulator. A capacitor(O.S/-LF) is connected between VCH and Vee. Don't draw currentfrom this terminal.• ESystem clock output (cycle clock 100kHz typ.)This NMOS open-drain output stays at "Low" level when theMCV is in halt mode, standby mode or reset.• MEMORYThe MCV memory is configured as shown in Figure 1. Duringthe processing of an interrupt, the contents of the MCV resistersare pushed onto the stack in the order shown in Figure 2. Sincethe stack pointer decrements during pushes, the low order byte(PCL) of t~e program counter is stacked first; then the highorder fou.r bits (PCH) are stacked. This ensures that the programcounter IS loaded correctly as the stack pointer incrementswhen it pulls data from the stack. A subroutine call will causeonly the program counter (PCH, PCL) contents to be pushedonto the stack.110 PortsTimerAIDLCD, SVSAAMsooof---------I S07F$080Page ZeroADM112B By •• ,)1-_____ --1 ::FFPort A0SOOOPort B $0011 I 1 I I Port C $002Not Used $003Port A OOR- $004Port B OOA' $005No. Used I PortCOOA' SOO6No. Used $007TIMER Data Reg.SOOBTIMER CTRL Reg. $009500ANot Used• VRH, VRLReference voltages for AID conversion are applied to thesetwo terminals. For details, see "A/D Converter".• CC I , CC2These are not intended for user applications. Open them.• NUMThis is not intended for user applications. Connect it to Vee·• Input/Output Terminals (Ao .... A 7 , Bo"" B 7 , Co"" C])Each of these 20 terminals consists of two 8 bits ports andone 4 bits ports. It may be used as an input or output underprogram control of the data direction register. For details, see"Input/Output" .• Liquid Crvstal Driver Terminals (COM I - COM3 , SEG I ,..,SEGdCOM I - COM] are for driving tomrtlon electrodes I whileSEG 1 - SECl? are for driving segments. SEG I - SEG I1 can beused as outpub by mask-option and SEGu -- SEG I " can beused as analog inputs for A/D converter by mask-option.Main ROM(3632 By"')t--------l SF2FSFlOSelf CheckADM1196 By •• ,)I--_____ ~ SFF3Int.rr"'JjtIIlItl0"110M(12I1Ylo.)SFF4t-______ ~5000t-__ A ,;.,/0...:.0..:;8':..,:8 A..:.eg::" _---I 500Et-__ A/_O_CT_A_L_Aeg":"_--l :~No. UsedS013LCOI Oat. Reg.- S014LC02 Oat. Reg.- S015LC03 Oat. Reg.- S016LC04 Oat. Reg.- S017LC05 Oat. Reg.- S018LC06 Oat. Reg.- S019LC07 O.t.Reg.- SOIANot Used I LC080,R. SOIBSVS CTAL Aeg,No. UsedAAM (96 By'.')SOICSOlOSOIFS020-----~------- $060STACK•S01;• WIll. Only AtgiilOlFigure 1 MCU Memory Map_HITAOHI 513

HD63L05F1-------------------------------------------------------------(Cautions)It is not possible to change the contents of the Write OnlyRegister (For example, the Data Direction Register of the I/Oport) of the HD63LOSFI by applying the Read/Modify/Writeinstructions, BSET, or BCLR;For preventing the system from wild runnine '\on't readthe Not Used area of the memory map.Push° PullConditionn-4 1 1 11n+1Code Reg.n-3 Accumulator n+2n-2 I ndex Register n+3n-1 1 1 1 1 1 PCH* n+4PCl* n+5• Only the PCH and PCl are stackedin the case of a subroutine call.Figure 2 Interruption Stack Sequence• REGISTERThe CPU has five registers that can be operated by the programmer.They are shown in Figure 3.11L-____ A ____...I Accumulator7 °101 _____°x ____ ~llndex Register'--_______ PC ______..... I Program Counter11 5 4 °sP_---.l1 Stack PointerI ... 0_10_1_0 ..l.I_o....l_o..&,I_1_I_l..&,I __°pulations when using read/modify/write instructions. When notrequired by a code sequence being executed, the index registercan be used as a temporary storage register.• Program Counter (PC)The program counter is a 12-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 12-bit register that contains the addressof the next free location on the stack. Initially, the stack pointeris set to location $07F and is decremented as data is beingpushed onto the stack and incremented as data is being pulledfrom the stack. The most significant bits of the stack pointerare permanently set to 00000 II. During a MCU reset or thereset stack pointer (RSP) instruction, the stack pointer is setto location $07F. Subroutines and interrupts may be nesteddown to location $061 which allow the programmer to use15 levels of subroutine calls.• Condition Code Register (CC)The condition code register is a S-bit register in which eachbit is used to indicate or flag the results of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained in the followingparagraphs.Half Carry (H)Used during arithmetic operations (ADD and ADC) toindicate that a carry occurred between bit 3 and bit 4.Interrupt (J)This bit is set to mask the internal interrupts and externalinterrupt (iNT). If an interrupt occurs while this bit is set, it islatched and will be processed as soon as the interrupt bit isreset.(Note)CLI (clear interrupt mask bit) is used to allow the interruptionfrom the instruction after next. SEI (set interrupt maskbit) masks the interruption from next instruction.Condition Code RegisterCarry/BorrowZeroFigure 3 Programming ModelNegativeInterrupt MaskHalf Carry• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datamanipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddreSSing mode. It contains an 8-bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for limited calculations and data man i-514 ~HITACHINegative (N)Used to indicate that the result of the last arithmetic, logicalof data manipulation was negative (bit 7 in result equal tological one).Zero (Z)Used to indicate that the result of the last arithmetic, logicalof data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the arithmeticlogic unit (ALU) occurred during the last arithmetic operation.This bit is also affected during bit test and branch instruction,shifts, and rotates.• SYSTEM CONTROL REGISTERApart from the registers for program operation explainedabove, there is a register that controls system operation. Itsconfiguration is shown in Figure 4.

-----------------------------------------------------------------HD63L05F17 SYS eTR L Register oFigure 4 System Control Register Configuration"LCD Circuit"(Note)The EXT bit and the LCD DUTY bits have to be initializedin 1 milli second from the start of CPU operation when thestatic drive signal or output port is selected.A Time Base counter is built in the MCU to generate twokinds of time base interrupts (I second cycle and 1/16 secondcycle). Clock signal to this counter is provided from the OSC 1or OSC2 depending on the mask-option. This counter is afrequency divider behind the 32 kHz oscillator.• Time Base Interrupt Request Flag,(TB INT)Stores an interrupt request from the time base which isselected by the TB select bit and is cleared by system reset orby software. If the TB MASK bit or I (Interrupt bit in the CCR)is set, the interrupt request is not acknowledged. Only logical"0" can be written into this bit by software.• Time Base Interrupt Mask,(TB MASK)If this bit is set, an interrupt request from the time baseis not acknowledged.• Time Base Select Bit (TB SELECT)This bit selects the time base. In logical "1", an interruptfrom the I-second cycle time base is acknowledged. In logical"0",1/16 second cycle time base is acknowledged.• Time Base Reset Bit (TB RESET)This bit resets the frequency divider behind the 32kHzoscillator. When this bit is set, one shot reset pulse is generatedby the hardware. Then it resets the frequency divider and afterthat, the frequency divider restarts. The CPU always reads thisbit as logical "0".Since the frequency divider also provides the system clocksto the A/D converter and LCD drivers etc., writing "1" to "TBRESET" bit during execution of A/D converter and TIMER(when 1/>32k is selected) causes different data from the correctresult and writing "1" to this bit causes flicker of the LCDdisplay.• Halt (HALT)Used to halt the CPU. When this bit is set, the registers aresaved onto the stack in the same sequence as interrupt processing.After all registers have been saved, the CPU haltsand is wait-for-interrupt state.If this bit is reset by an external interrupt or an internalinterrupt, the CPU restarts operating. By using the Halt functionwith Time Base Interrupt, the CPU can operate intermittentlyitself.• EXTWhen the form of output port is selected by DUTY selectingbit and the mask-option, I/>WRITE is available at the specifiedterminal (SEGI to 019) according to the designation of pinlocation. I/>WRITE clock can be got on every writing data intoLCD register 1 and be used as the write clock in the case oftransferring data of LCD register 1 to the outside. Normally,EXT must be reset.• Duty Select Bit (LCD DUTY)The LCD drive signal is based on 1/3 bias - 1/3 duty. However,there are switching circuits built in for static drive signaland output ports. For details, see the information given in• TIMERThe MCU timer circuitry is shown in Figure 5. The 8-bitcounter is loaded under program control and counts downtoward zero as soon as the clock input is applied. When thetimer reaches zero the timer interrupt request bit (bit 7) inthe timer control register is set. The CPU responds to thisinterrupt by saving the present CPU state in the stack, fetchingthe timer interrupt vector from locations $FF8 and $FF9 andexecuting the interrupt routine. The- timer interrupt can bemasked by setting the timer interrupt mask bit (bit 6) in thetimer control register. The interrupt bit (I bit) in the conditioncode register will also prevent a timer interrupt from beingprocessed.The clock input to the timer can be from an external sourceapplied to the TIMER input terminal (active at negative edge) orit can be the internal signal (1/>2 or 1/>32 k). When the internalclock signal is used as the source, the clock input is gated by theinput applied to the TIMER input terminal; this permits easymeasurement of its pulse width. 1/>2 is provided from aSCI andthe frequency is 1/4 of aSCI. 1/>32 k is provided from aSCI (thefrequency is 1/12 of aSCI) or OSC2 (32.768 kHz crystal)depending on the mask-option. If the OSCI continues tooscillate during the halt mode, 32.768 kHz crystal is selectedas the clock source or external clock is applied, the timer can beactive in the halt mode. Note that the timer operation isasynchronous to the CPU when the mask-option which theOSC 1 stops oscillating in the halt mode is selected.A 7 -bit prescaler is provided to extend the timing intervalup to a maximum of 128 counts before being applied to thetimer. The number of prescaling counts can be program controlledby the lower 3 bits within the TIMER CTRL register. Thetimer continues to count past zero and its present count can bemonitored at any time by monitoring the TIMER Data register.This allows a pr,ogram to determine the length of time sincea timer interrupt has occurred and not disturb the countingprocess.At the time of resetting, the prescaler and the counter areall initialized to logical "1". The timer interrupt request bit iscleared and the timer interrupt mask bit is set. The timerinterrupt request bit (bit 7 of TIMER CTRL Register) is set tological "1" when timer count reaches zero, and is cleared byprogram or by system reset. Only logical "0" can be writteninto this bit by program. The bit 6 of Timer Control Registeris writable by program. Both of these bits can be read byCPU.• RESETSThe MCU can be reset either by initial power-up or by theexternal reset input (RES). All the I/O ports are initialized toInput mode (DDRs are cleared) during reset.Upon power-up, a minimum of 150 milliseconds is neededbefore allowing the reset input to go "High". This time allowsthe internal oscillator (aSCI) to stabilize. Connecting a capacitorto the RES input as shown in Figure 8 will provide sufficientdelay.~HITACHI 515

HD63L05F1-------------------------------------------------------------7 bits PrescalerTimerInput Terminalr--------------, Timer Outputr----,I-__ --t~ (Timer Interrupt Request): :I : L _____ JSoftwareControlWriteFigure 5 Timer Block DiagramReadPRESCALERBIT000001010011100101110111Prescaler2°21222 3242'2 627TIMER CTR RegisterReset~(-0~1~-1~----~~----~)JL Interrupt -.----J I L-_ Indicates FrequencyRequest at "1" ~ Bit CountTIMER interrupt--Mask at "1" TIMER (Internal clock (I/>. or 1/>3.k)) at "1"COUNTER (External clock) at "0"------------- 1/>. (frequency is 1/4 of OSC1) at "1"l/>31k (frequency is 1/12 of OSC1 or 32.768 k Hz) at "0"Figure 6 Timer Control Register Configuration_ ;fv." *=VIL 1. VIHHD63L05F1RES T"m;~1 'I 1- -VeeMCUBuilt-in Reset~--------~I-----Figure 7 Application of Power and Reset TimingFigure 8 Input Reset Delay Circuit516 ~HITACHI

---------------------------------------------------------------HD63L05F1• SELF CHECKThe self check capability of the MCU provides an internalcheck to detennine if the port is functional. Connect the MCUas shown in Figure 9 and monitor the output of port C bit 3for an oscillation of approximately O.5Hz. This self checkcapability also provides the internal state of the MCV to measurethe LSI current. After a system reset, the MCU goes intoeach current measurement mode by the combination of thecontrol switches. The LSI current can be measured when theNUM is returned to Vee after setting of the current mode.+3VveeLED1/2Vee~ S.S,• The connection of OSC1 and OSC2depend on their mask option.LSI FunctionLSICurrentDuringoperationHaltAIDStandbySo S,XX0 X0 00 00 0Selection of SwitchSl S3 S. S. S. S7X X X X (1) 0X X O-+X X (')-+@ X0 X O-+X X (1)-+@-XX X O-+X X (1)-+0 X-~1---0 X O-+X X-+O (i)-+0 __ L- XX: OFFo :ON-+ : Change the stateFigure 9 Self Check Connections~HITACHI517

HD63l05F1-------------------------------------------------------------• INTERNAL OSCILLATOR OPTIONSThe MCV incorporates two oscillators: Oscillator 1 for systemclock supply and Oscillator 2 for peripheral modules suchas time base, AID converter, LCD drivers, etc ..• Oscillator 1 (OSC1; XT AL, EXTAL)The internal oscillator circuit can be driven by an externalcrystal or resistor depending on the stability. A manufacturingmask option is available to provide better matching betweenthe external components and the internal oscillator. The oscillator1 can stop when power is applied in either Halt or Standbymode. Figure 10 shows the connection. A resistor selectiongraph is given in Figure 11.Vee10pF -1Rs = 1 kfl c:::JEXTALXTALHD63LOSF1MCU• Oscillator 2 (OSC2; XIN, XOUT)Clocks for time base, LCD drivers, an AID converter, anda timer can be supplied by the OSC2 (32.768kHz crystal) or bythe OSCI through the frequency divider. In Halt mode, oscillator2 operates and permits the operation of the peripheralmodules with low power consumption. In Standby mode,only OSC2 keeps on running. Figure 12 shows the connectionand the relation between oscillator 1 and oscillator 2 is shownFigure 13 and Table 1.(Note)When OSC2 is not available or OSCI is the crystal option,OSCI is not allowed to stop at Halt mode. The accuracy ofthe time base is kept only when OSC2 is 32.768kHz crystaloscillator.100kflXTALHD63LOSF1MCUCrystal OscillatorRC OscillatorExt. ClockInputEXTALXTALHD63L05F1MCUExt. ClockInputEXTALXTALHD63L05F1MCUExt. ClockExt. ClockCrystal OptionFigure 10 Mask Option for Oscillator 1Resistor Option500400N:r~ 300u>c:GI~200~II..100\" '"--..IVee=3.0VTa = 25°Cr-- r--~~o 100 200 300 400 500 600 700Resistance. (kOIFigure 1 1 Typical Resistor Selection Graph518 $ HITACHI

---------------------------------------------------------------HD63L05F1As = 20k!l c::J10pFvee6XOUTXINHD63L05FlMCUCPU ClockCrystal OscillatorHALT----JSTANDBYTime baseInterrupt(Open)VeeXOUTXINHD63L05FlMCUFigure 13 Relation between Oscillator 1 and Oscillator 2Not UsedFigure 12 Connection of Oscillator 2Table 1 Oscillator 2 Mask-option and System OperationWhen OSC 1 is CrystalWhen OSC1 is RCMask Option OSC2 OSC2 OSC2 OSC2Not Available Available Not Available AvailableOSC1~~StateCPU Peripheral OSC1 CPU Peripheral OSC1 CPU Peripheral OSCl CPU PeripheralDuring SystemOperation0 0 0 0 0 0 0 0 0 0 '0 0At Halt 0 X 0 0 X 0 0 X 0 X X 0At Standby X X X X X X X X X X X X(NOTE) 0 ..... run x ..... stopTable 2 Mask-options of Oscillation Circuits and the Delay TimeType of OSC1 Use of OSC2 ConditionUsedStandby modeDelay Time of Restart (second)0 1/16 1/2 1Used X X 0 0~tused 0 0 0 0Crystal Option Used X X 0 0Not usedStandby modeNot used 0 0 0 0Oscillation Stop 0 X X XUsed of OSC1 .-at HALT Continue 0 0 0 0CR OptionOscillation Stop X X X XNot usedof OSC1at HALT Continue 0 0 0 0Note) Combinations of the mask-option indicated X is not available.• STANDBYWhen the STANDBY (SB) terminal becomes "High" level,the MCU goes into standby mode at its instruction fetch cycle.On standby mode, only 32 kHz oscillator (OSC2) keeps onrunning while the others are stopped with holding the currentdata except A/D converter, timer, and time base. Restartingof the MCU from standby mode is controlled by the Delay Timewhich is available by counting the OSC2 oscillation or 1/12frequency of the OSC 1 in frequency divider after the STAND­BY terminal turned to "Low" level. Therefore, the CPU restartsoperation from the previous state after the Delay Time (0 sec,1/16 sec, 1/2 sec, or I sec), and the accuracy of the Delay Time~HITACHI 519

HD63L05F1---------------------------------------------------------------is kept when aSC2 is 32.768 kHz crystal oscillator. When 1/12frequency of aSCI is provided to the frequency divider, theDelay Time depends on the stability of aSCI after restartingfrom standby mode and is not acculate.• DelayTimeSince aSCI stops in standby mode, it is needed to inhibitrestarting of CPU untill the asc 1 oscillation is stabilized afterthe STANDBY terminal has turned to "Low" level. To takethis stabilizing time of aSCI, user can select the Delay Timeout of 0 sec, 1/16 sec, 1/2 sec or 1 sec by mask-option dependingon a combination in the Table 2. STANDBY terminal has tobe kept at "Low" when resetting the MCU and has to be keptat "Low" during the Delay Time. Starting of the MCU by resetis also controlled by the Delay Time.HARDWARE RESET.. 1 ..... '$7F .. SP"0" ""!...Q.DR•CLR INT Logic$FF .. Timor Data Rag.$7F ... Timer PrncI',rS7F .. Timer Control Rag.$48 .. AID Control Reg.$63 .. System Control Rag."0" .. LCD1, LCD2, LCD3 Rag.• INTERRUPTSThere are six different interrupts to the MCU: externalinterrupt via external interrupt terminal (I NT), internal timerinterrupt, interrupt by termination of AID conversion, timebase interrupt, and software interrupt by an instruction (SWI).When any interrupt occurs, processing is suspended, the presentMCV state is pushed onto the stack, the interrupt bit (I) inthe condition code register is set, the address of the interruptroutine is obtained from the appropriate interrupt vectoraddress, and the interrupt routine is executed. The interruptservice routines normally end with a return from interruptinstruction (RTI) which allows the MCU to resume processingof the program prior to the interrupt. Table 3 provides a listingof the interrupts, their priority, and the vector address thatcontains the starting address of the appropriate interruptroutine.Figure 14 shows the system operation flow, in which theportion surrounded with dot-dash lined contains interruptionexecution sequence.(Note)A clear interrupt bit instruction (CLI) allows to suspend theprocessing of the program by an interruption after executionof the next instruction while a set interrupt bit instruction(SEI) inhibits any interrupts before execution of the nextinstruction. When a mask bit of a control register is cleared byan instruction, interruption is allowed before execution of thenext instruction.Figure 14 System Operation FlowchartStandbvOperationSequenceTable 3 Interruption PriorityInterruption Priority Vector AddressRES 1 $FFE,$FFFSWI 2 $FFC,$FFDINT 3 $FFA, $FFBTIMER 4 $FF8,$FF9AID S $FF6,$FF7TIME BASE 6 $FF4,$FFS• Acknowledging an INT in Halt modeIn HALT mode, the CPU is not operating but the peripheralsare operating. When an interruption is acknowledged, the CPUis activated and executes interruption service matching theinterruption condition by means of vectoring.• Acknowledging an INT in Standby modeIn Standby mode, the system is not operating with powersupplied to it. therefore. any interruption request (includingRES) is not acknowledged,520 ~HITACHI

-------------------------------------------------------------HD63L05F1• INPUT IOUTPUTThere are 20 input/output terminals, which are programcontrolled by data direction registers for use as either input oroutput. If an I/O port has been programmed as an output andis read, then the latched logical level data is read even thoughthe output level changes due to the output load.If a port is to be used as an input terminal. the user mustspecify whether or not it will be equipped with a pull-up PMOS.Figure 15 shows the port I/O circuit.Figure 15 Port I/O CircuitBits ofData Bit of Out· Output Input toDirection put Data StateRegisterCPU0 0 010 x 3·State Pin• Configuration of PortFigure 16 shows the configuration of I/O ports. As theoutput is on/off controlled by a data direction register. an I/Oport may directly be applied as an input terminal. No problemis involved with the input if both "High" and "Low" levelsare applied. For only one level. the user must specify the useof a pull-up PMOS for "Open/Low" input application.J1J-{>-Pull·up PMOS not available, ,r­Vss~i-----1 __ :......: __ ...Pull·up PMOS availableVee,II.JVssVssFigure 16 Selection of Input Configuration for I/O Port_HITACHI 521

HD63l05F1-----------------------------------------------------------___• AID CONVERTERThe MCU incorporates an 8 bits AID converter based on theresistor ladder system. Figure 17 shows its block diagram.The "High" side of reference voltage is applied to Y RH.while the "Low" side of reference voltage is applied to Y RL'The reference voltage is divided by resistors into voltages matchingeach bit. which is compared with analog input voltage forAID conversion. As the analog input voltage is applied to theMOS gate of the comparator through the analog multiplexer.this voltage comparison system achieves high input impedance.The AID Data Register stores the results of an AID conversionor can be set 8 bit data for programmed comparator.These functions are controlled by software-controlled AIDCTRL Register. The result of AID conversion is not assuredif the conversion is interrupted by STANDBY. Figure 18 showsthe configuration of the AID control register.• AID Interrupt Request Flag (AID INTIThe AID INT bit is set to logical "1" after completion ofAID conversion and is cleared by program or by system reset.Only logical "0" can be written into this bit by software .• AID Interrupt Mask (AID MASK)If this bit is set, interrupt from the AID converter is notacknowledged. This bit can be written by program.• AID Conversion Flag (CNV)To start auto AID conversion, set this bit to logical "1 ".During conversion, data of this bit stays at "1". The bit isautomatically reset to "0" when the auto AID conversion ends.In auto AID conversion, supply voltage is applied to the comparatoronly when CNY = "1". The digital data which is obtainedby the AID conversion is held in the AID Data Register.This data is reset when the CNY is set to "I" again.• AID Operation Mode Select Bit (Auto/Program)Used to select either auto-run 8 bits AID conversion or8 bit programmed comparator operation (Auto 8 bits AIDconversion at ''0'').Offset Compo CapacitorAnalog InputReferenceInput___---'101

HD63L05Fl• Comparator Output (COMP OUT)The result of comparator operation under program controlcan be read from this bit (Logical" 1 " means that input voltageis higher than programmed reference voltage).• Analog Input Channel Select Bits (MPX)Used to select 8-channel analog inputs. The multiplexer isan analog switch based on CMOS. Note that the analog inputsfrom CH 2 to CHs are mask option while CHI is exclusive.When 1/3 bias - 1/3 duty or static LCD is used, CH 7 andCHs are not available because these two terminals are used forLCD power supply as V I and V 2 •• LCD CIRCUITThe system configuration of the LCD circuits is shown inFigure 19. Segment data for display are stored in data registersLCDI to LCD8. Since the circuits are connected to the outputterminals via pin location block, the· user may specify a combinationof data to be mUltiplexed to the segment output terminals.The bit data of the LCD register is combined with the timingclock (tPl , tP2 or 4>3) and three combined bit data are gathered tomake a segment output data for 1/3 bias - 1/3 duty driving inthe pin location block. In case of static LCD drive of outputport, timing is always fIXed at tPl (always "High") and one bitdata of the LCD register is transferred for an output terminal.Note that the output terminals from SEG 13 to SEG I7 aremask option while the others (SEG I to SEG 12) are always availablewhen the Duty bits are "0 I" or "II".When the form of output port is selected by Duty bit ("00"),tP WRITE can be got every time data is written into LCD 1register in the case that EXT bit is "I". As LCDI register has8 bits latches, it is easy to transfer the internal 8 bits data toexternal devices via output por~s. with automatically generatedwrite clock tPWRITE. The cycle clock pulse can be also availableas an internal data source for the output terminal when outputport is selected as 1/4 OSC I.Assignment of segment terminals to the bits of the LCDdata register, including the case where they are used as outputterminals, is to be specified by the user when he orders masks.In case of static LCD or output ports, only LCDI, LCD2, andLCD3 are allowed to be used. These registers are initialized at"0" by system resetting.• LIQUID CRYSTAL DRIVER WAVEFORMSThe LCD circuit is based on 1/3 bias - 1/3 duty driving.Figure 20 shows the common electrode output signal waveforms(COM I , COM 2 , COM 3 ), segment signal waveforms (SEG I toSEG I7 ) and LCD bias waveforms (between COM and SEG­MENT).Oala Rag.SYS CTRL Rag.Pin LocationBlockSEG,SEG,SEG,SEG.SEG,SEG.SEG,SEG.SEG.SEG,.SEG"SEG"SEG"SEG,.SEG ..SEG ..SEG"COM,COM,COM,SEG"-SEG,,Mask OplionSystemCont.DutyContents ofSEG. -SEG1700 OUTPUT PORT01 STATIC LCD10 ---111/3 Bias1/3 Duty LCDNote)Both of mask-option and softwarecontrol are needed to specify thecontents of SEG • - SEG".Figure 19 LCD Circuit System Configuration~HITACHI 523

HD63L05F1---------------------------------------------------------------Vcc213VCC- - ••. -1I3VCC' •GND"- .•••COMMON 1COMMON 2COMMON 3SEGMENT11.2.31COM, -SEGMENTCOM,·SEGMENTCOM, ·SEGMENTOUTPUT PORTVCC Fb:: Output Ilvel."1" "0" matching Data inGNDRegilterSTATIC LCD ~~-~z ...--. VeeJ U U L VssFigure 20 LCD Driving Waveforms• BIT MANIPULATIONThe MCU has the ability to set or clear any single randomaccess memory or input/output bit (except the data directionregisters) with a single instruction (BSET, BCLR). Any bit inthe page zero read only memory can be tested, using the BRSETand BRCLR instructions, and the program branches as a resultof its state. This capability to work with any bit in RAM, ROMor I/O allows the user to have individual flags in RAM or tohandle single I/O bits as control lines.(Note)It is needed to pay attention to the system control register,the timer control register, and A/D control register whenBSET, BCLR, or Read/Modify/Write instructions are appliedto them. If own interrupt request occured onto the interruptrequest bit (bit 7) of the control register between read cycle andwrite cycle of these instructions, the bit 7 might be cleared inthe write cycle and not acknowledged by CPU.• ADDRESSING MODEThere are 10 addressing modes available to the MCU forprogramming. Familiarize yourself with these modes by readingthe information and referring to the diagrams that follow.• ImmediateSee Figure' 21. In immediate addressing mode, constantsthat will not change during execution of a program are accessed.The instruction used for that purpose has a length of 2 bytes.The effective address (EA) is PC. The operand is fetched fromthe byte that follows the OP code.• DirectSee Figure 22. In direct addressing mode, the address of theoperand is contained in the second byte of the instruction.The user can gain direct access to the LSB 256 of memory. AllRAM bytes, I/O registers, and 128 bytes of ROM are locatedon page 0 in order to utilize this useful addressing mode.• ExtendedSee Figure 23. The extended addressing mode is used forreferencing to all addresses of memory. The EA consists ofthe contents of the two bytes that follow the OP code. Theinstruction used for extended addressing has a length of 3bytes.• RelativeSee Figure 24. Only Branch instructions are used in relativeaddressing mode. When a branching takes place, the contentsof the byte next to the OP code are added to the programcounter. EA = (PC) + 2 + ReI., where ReI. indicates signed 8 bitsdata at the address following the OP code. When no branchingtakes place, ReI. = O. When a branching occurs, the programjumps to any byte of + 129 to -127 of the current instruction.The length of the Branch instruction is 2 bytes.524 _HITACHI

---------------------------------------------------------------HD63L05F1• Indexed (without Offset)See Figure 25. In this addressing mode, the lower 256 bytesof memory are accessed. The length of the instruction usedfor this mode is one byte. The EA consists of the contents ofthe index register.• Indexed (8 Bits Offset)See Figure 26. The EA consists of the contents of the bytefollowing the OP code, and the contents of the index register.In this mode, the lower addresses of memory up to 511 can beaccessed. Two bytes are required for the instruction.• Indexed (16 Bits Offset)See Figure 27. The EA consists of the contents of the twobytes following the OP code. and the contents of the indexregister. In this mode. the whole of the memory can be accessed.The instruction using this addressing mode has a length of3 bytes.• Bit Set/ClearSee Figure 28. This addressing mode can be applied to anyinstruction that permits any bit on page 0 to be set or cleared.The byte following the OP code indicates an address withinpage O.Memoryi8IIIIIIIIPROG LOA # $F8 OSBE A61------1OSBF F8§@IIIII I• Bit Test, BranchSee Figure 29. This addressing mode can be applied to instructionsthat test bits at the first 256 addresses ($00 to $FF)and are branched by relative qualification. The byte to be testedis addressed by the contents of the address next to the OP code.The individual bits of the byte to be tested are designated bythe lower 3 bits of the OP code. The third byte indicates arelative value that is to be added to the program counter whena branch condition is satisfied. The instruction has a lengthof 3 bytes. The value of the bit that has been tested is writtenat the carry bit of the condition code register.• ImpliedSee Figure 30. There is no EA for this mode. All informationneeded for execution of instructions is contained in the OPcode. Operations that are carried out directly on the accumulatorand index register are included in the implied addressingmode. In addition, the SWI and RTI instructions are also includedin the group of this operation. The instruction usingthis addressing has a length of one byte.AIndr:9Stack PointProg CountOS COCCF8Figure 21Example of Immediate Addressing$ HITACHI 525

HD63L05F1-------------------------------------------------------------IIIIiICAT FeB 32 004BIPROG LOA CAT 0520052EfMemory20B64BiIIIIIII/lEA004B1Adder'"o!oIIIAI1 20 IIndex Reg.IStack PointIProg Count052FCCIII~IIII,Figure 22 Example of Direct AddressingMemory• I§I0000IIPROGLOA CAT 0409 ~6040A 06 J ____---'040B E5IIIICAT FCB 64 06E5 401-------1A40Index RegStack PointProg Count040CCCFigure 23 Example of Extended Addressing526 ~HITACHI

---------------------------------------------------------------HD63L05FlMemoryiI,~ ,PROG BEQ PROG2 04A7 2704A8 180000AStack PointIndex Reg§. , ,Figure 24 Example of Relative AddressingMemoryTABL FCC/LI/ OOB8 J... __!4C:...__,----;;..;...;.""'---------i--------4.___A4_C __.....49 Index RegB8PROGStack PointProg Count05F5ccFigure 25' Example Of Indexed (without Offset) Addressing$ HITACHI 527

HD63L05F1---------------------------------------------------------------TABL FCB # BF 0089FCB # 86 008AFCB # DB 008BFCB # CF 008CPROG LOA TA8L.X 075B075CMelorv,iI ,IIIIIBF86DBCFE689IIIlEAI ooac IfAdder/'" IIIAJICFIIndex RegJ 03IStack PointIProg Count0750ICCI~I, ,IFigure 26 Example of Indexed (8 Bits Offset) Addressing§IMemorvIPROG LOA TABL.X 0692 ~60693 070694 7EiI1-------'ADBIndex Reg02Stack PointProg Count0695IICCTABL FCB # BF 077EBFFCB # 86 077F 86FCB # DB 0780 J-_....!O~B!.__-t--------------...JFCB # CF 0781CFFigure 27 Example of Indexed (16 Bits Offset) Addressing528 ~HITACHI

-----------------------------------------------------------------HD63L05FlMemoryPORT B EQU 1 0001BF0000AIndex RegPROG BCLR 6. PORT B 058F1 D......----~0590 01Stack PointProg Count0591I~11I,ICCFigure 28 Example of Bit Set/Clear AddressingPORT C EQU 2 0002PROG BRCLR 2. PORT C. PROG 2 057405750576,II1MemJOryFOII1 I1 I05021DI'/Bit2H~10 00ORI 1J~ ~,IlEA0002tAdderIAdder/I~t0000IIAIIIStack PointIndex RegIIIProg Count0594Iccr C-,Figure 29 Example of Bit Test and Branch Addressing~HITACHI529

HD63l05F1---------------------------------------------------------------IIIMemory~IIIIPROG TAX "SA ~I , ,§AProg Count05BBccE5Index RegE5Figure 30 Example of Implied Addressing• INSTRUCTION SETThere arc Sq instructions available to the MCV. They canbe divided into five groups: Register/Memory. Read/Modify/Write. Branch. Bit Processing. and Control. All of these instructionsare explained below according to the groups. and arcsummarized in individual tables.• Register/MemoryMost of these instructions use two operands. One operandis either the accumulator or index register. while the other isacquired from memory using one of the addressing modes.No operand of register is available in the unconditional Jump(JMP) and Subroutine Jump (JSR) instructions. See Table 4.• ReadlModifylWriteThese instructions read a memory address or register. modifyor test its contents. and writes a new value into the memory orregister. Negative or Zero instructions (TST) do not providewriting. and are exceptions for the Read/Modify/Write. SeeTable 5.• BranchA Branch instruction will branch from the program sequencein progress if the specific branch condition is satisfied. SeeTable 6.• Bit ProcessingThis instruction can be used for any bit of the first 256bytes of memory. One group is used for setting or clearing.while the other is used for bit testing and branching. See Table 7.• ControlThe Control instruction controls the operation of the MCVfor which a program is being executed. See Table 8.• A List of Instructions Arranged in Alphabetical Or.rAll instructions are listed in Table 9 in the alphabeticalorder.• OPCodeMapTable 10 shows an OP code map of the instructions usedwith the MCV.530 _HITACHI

-~--------~-----------------------------------------------------------------HD63L05FlOperationTable 4 Register/Memory InstructionsAddressing ModeInde)(ed Inde)(ed Inde)(edImmediate Direct E)(tended(No Offset) (8-8itOffset) (16·8itOffset)--Op # # -~T,---r----Op # # Op # # Op # # Op # # Op # #MnemonicCode 8ytes Cycles Code 8ytes Cycles Code Bytes Cycles Code 8ytes Cycles Code Bytes Cycles Code Bytes CyclesLoad A from Memory LOA A6 2 2 B6 2 3 C6 3 4 F6 1 2 E6 2 4 06 3 5-- ----------Load X from Memory LOX AE 2 2 BE 2 3 CE 3 4 FE 1 2 EE 2 4 DE 3 5----- -_.-_.- ---- -_._- f---------Store A in Memory STA - - - B7 2 4 C7 3 5 F7 1 3 E7 2 5 07 3 6------ ----f---Store X in Memory STX - - - BF 2 4 CF 3 5 FF 1 3 EF 2 5 OF 3 6-----r--- ----Add Memory to A ADD AB 2 2 BB 2 3 CB 3 4 FB 1 2 EB 2 4 DB 3 5Add Memory andAoC A9 2 2 B9 2 3 C9 3 4 F9 1 2 E9 2 4 09 3 5Carry to A--- -- ~Subtract Memory SUB AO 2 2 BO 2 3 CO 3 4 FO 1 2 EO 2 4 DO 3 5--- ---f------- -- ---- -------Subtract Memory fromSBC A2 2 2 B2 2 3 C2 3 4 F2 1 2 E2 2 4 02 3 5A with Borrow--f------r--AND Memory to A AND A4 2 2 B4 2 3 C4 3 4 F4 1 2 E4 2 4 04 3 5-- --- ----OR Memory with A ORA AA 2 2 BA 2 3 CA 3 4 FA 1 2 EA 2 4 oA 3 5--r----~---- --E)(clusive OR MemoryEOR A8 2 2 BB 2 3 C8 3 4 F8 1 2 E8 2 4 08 3 5with AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory withA (Logical Compare)CMP Al 2 2 Bl 2 3 Cl 3 4 Fl 1 2 El 2 4 01 3 5CPX A3 2 2 B3 2 3 C3 3 4 F3 1 2 E3 2 4 03 3 5BIT A5 2 2 B5 2 3 C5 3 4 F5 1 2 E5 2 4 05 3 5Jump Unconditional JMP - - - BC 2 2 CC 3 3 FC 1 1 EC 2 3 DC 3 4Jump to Subroutine JSR - - - Bo 2 4 CD 3 5 Fo 1 3 ED 2 4 DO 3 5Symbols: Op· ()peration# = InstructionOperationMnemonicTable 5 Read/Modify/Write InstructionsAddressing ModeImplied (A) Implied (X) DirectInde)(ed(No Offset)Inde)(ed(8-BitOffset)Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Byles Cycles Code Bytes Cycles Code Byles Cycles Code Byles CyclesIncrement INC 4C 1 1 5C 1 1 3C 2 4 7C 1 3 6C 2 5--!---Decrement DEC 4A 1 1 5A 1 1 3A 2 4 7A 1 3 6A 2 5Clear CLR 4F 1 1 5F 1 1 3F 2 4 7Fc---- .-1 3 6F-2 5Complement COM 43 1 1 53 1 1 33 2 4 73 1 3 63 2 5-----Negate(2's Complement)NEG 40 1 1 50 1 1 30 2 4 70 1 3 60 2 5Rotate Left Thru Carry ROL 49 1 1 59 1 1 39 2 4 79 1 3 69 2 5Rotate Right Thru Carry ROR 46 1 1 56 1 1 36 2 4 76 1 3 66 2 5------- ---------- . __ ._- ----Logical Shift Left LSL 48 1 1 58 1 1 38 2 4 78 1 3 68 2 5Logical Shift Right LSR 44 1 1 54 1 1 34 2 4 74 1 3 64 2 5--- - -- ---Arithmetic Shift Right ASR 47 1 1 57 1 1 37 2 4 77 1 3 67 2 5Arithmetic Shift Left ASL 48 1 1 58 1 1 38 2 4 78 1 3 68 2 5--- --------------Tes! for Negative orTST 40 1 1 50 1 1 3D 2 4 70 1 3 60 2 5ZeroSymbols; Op" Operation# .. Instructioni_HITACHI 531

HD63L05F1---------------------------------------------------------------Table 6 Branch InstructionsOperationMnemonicOpCodeBranch Always BRA 20Branch Never BRN 21Branch IF Higher BHI 22Branch I F lower or Same BlS 23Branch I F Carry Clear BCC 24__(~B~~~~J:iJ~~~~~~) (BHS) 24Branch I F Carry Set BCS 25(Branch IF lower) (BlO) 25Branch I F Not Equal BNE 26_____ !3~n~!'_~~_~

---------------------------------------------------------------HD63L05F1OperationTable 8 Control InstructionsImpliedOp #Mnemonic#Code Bytes CyclesTransfer A to X TAX 97 1 1Transfer X to A TXA 9F 1 1Set Carry Bit SEC 99 1 1Clear Carry Bit ClC 98 1 1Set Interrupt Mask Bit SEI 9B 1 1Clear Interrupt Mask Bit CLI 9A 1 1Software Interrupt SWI 83 1 9Return from Subroutine RTS 81 1 4Return from Interrupt RTI 80 1 7Reset Stack Pointer RSP 9C 1 1No-Operation NOP 90 1 1Symbol: Op = Operation# = InstructionMnemonic Imme- Ex- Re-ImpliedDirectdiatetended lativeTable 9 Instruction SetAddressing ModesCondition CodeIndexed Bit BitIndexed Indexed(No(8 Bits) (16 Bits)Setl Test & H I N Z COffset) Clear BranchADC x x x x x xADD x x x x x x" AND x x x x x x "•ASl x x x x ASR x x x x• • " " "BCC x BClR x BCS x BEQ x BHCC x BHCS x• • • • •BHI x• • • • •BHS x• • • • •BIH x• • • • •Bil x• • • • •BIT x x x x x x• •" " •BlO x BlS x BMC x BMI x BMS x BNE x BPl x BRA x • • • • •Symbols for condition code:H Half Carry (From Bit 3) C Carry/BorrowI Interrupt Mask " Test and Set if True, Cleared Otherwise(Continued)N Negative (Sign Bit) • Not AffectedZ Zero$ HITACHI 533

HD63L05F1---------------------------------------------------------------Table 9Instruction Set (Continued)MnemonicImpliedAddressing ModesImme- Ex- Re-Directdiatetended lativeCondition CodeIndexedBit Bit(NoIndexed Indexed(8 Bits) (16 Bits)Set I Test & H I N Z COffset) Clear BranchBRN x• • • • •BRCLR x• • • • /\BRSET x /\BSET x BSR x •CLC x • 0CLI x • 0 • • CLR x x x x it 0 1 •CMP x x x x x x /\ /\ /\COM x x x x /\ 1\ 1CPX x x x x x x /\ /\ /\DEC x x x x /\ /\ EOR x x x x x x /\ /\ INC x x x x /\ /\ JMP x x x x x JSR x x x x x • • LOA x x x x x x /\ /\ LOX x x x x x x /\ 1\ •LSL x x x x /\ /\ /\LSR x x x x 0 /\ /\NEG x x x x /\ /\ /\NOP x • • ORA x x x x x x /\ /\ •ROL x x x x /\ /\ 1\ROR x x x x /\ 1\ 1\RSP x • • • • •RTI x ? ? ? ? ?RTS x • • •SBC x x x x x x 1\ 1\ 1\SEC x • 1SEI x 1 • • STA x x x x x 1\ 1\ STX x x x x x /\ 1\ •SUB x x x x x x • 1\ 1\ 1\SWI x 1 TAX x • • TST x x x x /\ 1\ TXA x • • • • •Symbols for condition code:H Half Carry (From Bit 3) C Carry/BorrowI Interrupt Mask /\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack534 _HITACHI

---------------------------------------------------------------------HD63L05F1Table lOOP Code MapBit Manipulation Branch Read/Modify/Write Control Register/MemoryTest &BranchSet/ClearRei DIRI A I X I ,X1 I ,XO IMP IMP IMM I DIR I EXT I ,X2I ,X10 1 2 3 I 4 I 5 I 6 I 7 8 9 A I 8 I C I 0 I E0 BRSETO BSETO BRA NEG RTI* - SUB1 BRCLRO BCLRO BRN - RTS* - CMP2 BRSEn BSEn BHI - - SBC--r-------3 BRCLR1 BCLR1 BLS COM SWI* - CPX-- -- --1--------- --4 BRSET2 BSET2 BCC LSR - - AND5 BRCLR2 BCLR2 BC~~---- - ---BIT6 BRSET3 BSET3 BNE ROR - - LOA---7 BRCLR3 BCLR3 BEQ ASR - TAX - I STA(+lI8 BRSET4 BSET4 BHCC LSL/ASL - CLC EOR9 BRCLR4 BCLR4 BHCS ROL - SEC ADC--- --- _._-- --~-------------f---A BRSET5 BSET5 BPL DEC - CLI ORA--_._----B BRCLR5 BCLR5 BMI - - SEI ADD---~---- --_._-- -- -----.-------~--1-----C BRSET~ BSET6 BMC -_ ...•INC-- -----1----=--- r-B~ --- IJMP(-1)---- -- _._- - ----0 BRCLR6 BCLR~_ BMS TST - NOP BSR* I JSR(+1) I JSR------------------------E BRSET7 BS~ _£!!!O_--------=--- - - LOXF BRCLR7 BCLR7 BIH CLR - TXA - I STX(+1)3/40r5 2/4 2/20r3 2/4 11/1 I 1/1 I 2/5 I 1/3 1/* 1/1 2/2 I 2/3 I 3/4 I 3/5 I 2/4I ,XOI FIJSR(+1I 1/2+-H IGH0123 L4 o5 W6789ABC0EF(NOTES)1. "-" is an undefined operation code.2. The figure in the lowest row of each column gives the number of bytes and the cycles needed for the instruction.The number of cycles for the asterisked (*) mnemonics is a follows:RT! 7RTS 4SWI 9BSR 43. The parenthesized figure must be added to the cycle count of the associated instruction.4. If the instruction is branched, the cycle count is the larger figure.$ HITACHI535

HD63L05F1-------------------------------------------------------------HD63L05FMASK OPTION LIST* Select one type for each item and check •DATE OF ORDERCUSTOMERDEPT.ACCEPTED BYROM CODE ID.LSI TYPE NO.HD63L05F(1) OSC OPTIONType Use Delay Time ofof of Condition Restart (sec.)OSCl OSC2 0 1/16 1/2 1STANDBY Used *** ***UsedXTALmode Not UsedOption STANDBY Used *** ***Not used mode Not UsedOscillation Stop *** *** ***Used of OSC1CR at HALT ContinueOption Oscillation Stop *** *** *** ***Not Used of OSClat HALT Continue• Specify a type ofOSC option.• Crystal option of OSC1is not allowed to stopat HALT.• If OSC2 is not used,the Delay Time is notacculate.(2) I/O OPTIONMask OptionMask OptionPortPinA B C 0E I F PinAo INT I SEGI3/CH6AlSEGI4/CHsA2SEG1S/CH4-A3SEGI6/CH3A4SEG17/CH2As0Is/CHs/V2A6019/CH7/V1A7BoA CMOS output without input pull-up PMOSBl B CMOS output with input pull-up PMOSC CMOS output for key scanningB2o NMOS open-drain outputB3 E Input without pull-up PMOSF Input with pull-up PMOSB4G AID InputBs H Segment outputK Terminals for LCD displayB6B7• Specify an 1/0 option for each terminal.CoClC2C3(3) LCD DRIVERMask OptionL I S I PSegment I IMas~ options Indicated as **. are not available.LSP1/3 bias-1/3 duty LCDStatic LCDOutput port* Specify a type of LCD driver.536 _HITACHIGMask optionH K***************

-------------------------------------------------------------HD63L05F1(4) LCD PIN LOCATIONLCD 11;1 Timing Segment Output Terminal/Regl.l. l COM, COM, COM. SEG, SEG. SEG, SEG. SEG. SEG. SEG, SEG. SEG, SEG,. SEG" SEG" SEG" SEG .. SEG" SEG, SEG"OutP~~0" 0 ..LCOlrO~--i_--t_--t_~r__i---t--_r--_r--i_--t_--r_~--~---+--~--~--+---+_~~--~--~~~--_r--~--r_-t--1_--+_~--_+--~--r__+--~--+__1--_r--~--r_-+--4---+--~--~~~--_+--_+--~--+_--+_--~~--_4--_4--~--~-- ~-~-- ---+--_r--~--4_--+_--+_--+_---7 T---~~O _~_ ~~H~_4--_+--_+--~--+_-+_--I__._--l~~ .. ~~~~~~=-----4:------:+:-----+-.--+--_+_--+_--1---+ -~~ =--t-::-~~--_+-_+--_+_-~+_-+---_j_- - .... ---~ ---- f----r-=-I__+-__+-_+--+-+_-+_--+_----i----t-,--~!_-f_- ----f---- f--I-:-:=-+----~_+--_+--_+--_+_--+_-+_--~---j-.-- I_ --- ---!--"-- --+---jf-_+---+---+--+--+---+_--+_--+-------iLC03t- 0 _+_--+_--+---+--4I--_+----+- -1------­f--~_+--_+--_+-_+_--+_-+_--~--t_--.-...- ---~---4_I_----+---+------+-==:===:===~~=--~4----1_-- -I---~ ---_+--_+_--_+_--_+_--_+_----16rL-:C:-::O-4+-0-+---+---+---+--4I---+·--+~·~ ~- .-- f--- ---1--.- .. --r----~1__+--__+-_+--+--+_-+_--+_----i----4---+--~--~--~--~--~~---4--~-.~---.---I___--~r__+--_+-_+--+---~-+_--r-___1-_+-__+-_r-_+_--+_--+_-I____1-_+-_+-+-+-+---LC05f-0+_+_-+_--+____l--__+-.~--+--_+_--+_--+_--I____l----+--+._-- ____ _ -_ ___ _ ___ 1--__ -~-=:=--1'21---+---- - -----11--- - -.-- --- ~LC06rO~-+---+---+-~---+--+--+--+--+_--+_--I____l--_+-+--+-+-+---+_____i---~--~~6~C07 0~,I--+--+---+--~---+--~-+-~~---l--+--r--+-4---+---I-~~-+---+--+--+-+----2~-.+--I-~I----l----+---+----+---+---+---+----l---+---+---+---4---+---+---I---4---+----+---+---LCOS 0r,~--+---I-~---+--+--+-~~-+--+---+---+--j---+--+--+---+----l---+---+--·+--+----1-~;;-t---+--+---+---t--1--+-+--+--+--+--+----1I----+--+--+--+--+----I----jf---f---~- --~hc/J'W-R--.LTE=+--O-+--- 1----Ir,~~~O=S=Cl~~O-+---+---+---+---+---I---I--+---+---+---+----+---+---I----l---+----+---+----+----+----r-~* Specify the multiplex timing and segment terminal for each bit of LC01 to LCOS.* When static or output port is selected, the Multiplex timing is fixed at COM 1 •* If there are unspecified bits, Hitachi specifies them as dummy.* c/JWRITE is generated when data is written into the LC01.* 1/4 OSC1 is a quarter of the OSC1 clock speed. When the MCU is in standby mode, it becomes "Low".~HITACHI 537

HD63L05EOI-------------­Evaluation Chip for HD63L05F 1HD63LOSE is a CMOS evaluation chip for the HD63LOSF.Connecting an external EPROM (HN462732) to the chip. itcan be operated as a single chip microcomputer HD63LOSF.Interface signals are 12 bit Address Bus (Eo - E 7 • Fo - F 3). 8bit Data Bus (Do - D 7 ) and Chip Enable (eE).It is easy to debug the HD63LOSF user program with thisevaluation chip.• PIN ARRANGEMENT• FEATURES• 3V Power Supply• 96 Bytes RAM• EPROM (HN462732) Interface• LCD Driver• 8-bit Programmable Timer with 7-bit Prescaler• 8-bit AID Converter• 20 parallel I/O Port• Same Instruction Set as HD63L05F• NMOS Open-drain Output• 100 Pin Flat Package (FP-l00)HD63L05EO• TERMINALSAo "" A7 I/O PortBo "" B7 I/O PortCo "" C3 I/O PortDo "" D7 Data Bus (Input)Eo "" E7 Lower 8 bit Address Bus (Output)Fo "" F3 Upper 4 bit Address Bus (Output)U/M Test TerminalCE/WR Chip Enable, Read/Writern Instruction Fetch SignalADCLK E ClockRAtT External clock control signalMS"ET Connected to V cc51 CoNC: No Connection(Top View)538 eHITACHI

--------------------------------------------------------HD63L05EO• BLOCK DIAGRAMHALTJllR----tADClK~CE. VfflMSETIXINXOUTDRIVEROUTPUTDATAlATCHLCD1 8LCD2LCD4SEGISEG 2SEG3SEG.SEG,SEG 6SEG,SEG.TIMER1.0Al1.2A3A4AsA6A,ACCUMULATOR8 AINDEX REGISTER8 IXCONDITION CODES REG. CCRSTACK POINTERSSPPROGRAMCOUNTERHIGH PCHPROGRAMCOUNTERlOW PClCPUU/MINTCONTROL8SYS CTRlAlUSEG9LCDS 7SEG lo(SEGIIILCD6 7(SEG 12 1(SEG 13 ILCD7 7(SEG I4 1(SEG 15 ILCD8 4(SEG 16 1......_-_.....-'--_ (SEG 17Il- e(0 0:WI-0:W"'---CHI.... ---(CH21"'---(CH31> "'---(CH41Z0 ....---(CHsIU...---(CH610< "'---(CH71L._J...-t---(CHe IIIIIi:oQ.....---80....---81...."'---8 2---83....---84...---85....---86~ __ ~~""---'87cII.cW0-W~HITACHI539

HD68P01 V07 ,HD68P01 V07-1-HD68P01 MO ,HD68P01 MO-1MCU (Microcomputer Unit)The HD68POI is an 8-bit single chip microcomputer unit(MCU) which significantly enhances the capabilities of theHMCS6800 family of parts. It can be used in production sys·terns to allow for easy firmware changes with minimum delay orit can be ,used to emulate the H06801 for software development.If includes 128 bytes of RAM, Serial Communications Interface(SCI), parallel 1/0 and a three function Programmable Timer onchip, and 2048 bytes, 4096 bytes or 8192 bytes of EPROM onpackage. It includes an upgrade H06800 microprocessing unit(MPU) while retaining upward source and object code com·patibility. Execution times of key instructions have been im·proved and several new instructions have been added includingan unsigned 8 by 8 multiply with 16-bit result. The H068PO Ican function as a monolithic microcomputer or can be ex·panded to a 65k &yte address space. It is TTL compatible andrequires one +5 volt power supply. A summary of H068POIfeatures includes:• FEATURES• Expanded HMCS6800 Instruction Set• 8 x 8 Multiply Instruction• Serial Communications Interface (SCI)• Upward Source and Object Code Compatible with HD6800• 16-bit Three·function Programmable Timer• Applicable to All Type of EPROM4096 bytes; HN482732A8192 bytes; HN482764• 128 Bytes of RAM (64 bytes Retainable on Powerdown)• 29 Parallel I/O and Two Handshake Control Line• Internal Clock Generator with Divide·by·Four Output• Full TTL Compatibility• Full Interrupt Capability• Single-Chip or Expandable to 6Sk Bytes Address Space• Bus compatible with HMCS6800 Family- The specifications for HD68P01V07·1 andHD68P01MO·1 are preliminary. -HD68P01V07, HD68P01V07-1,HD68P01MO, HD68P01MO-l• PIN ARRANGEMENT (Top View)HD68P01V07, HD68P01V07.1• TYPE OF PR

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1• BLOCK DIAGRAM~--4---1r-+"'P2nM-+-.---',,--+_ P21M-+-+--.-----.. PnI*+-+--HP--'" P23M-+-+-~t--r ... P 24541EPROM(HN482732AIlHN482764 )01 :02 IOJ I04 I0; :Ofi I01 IIIL __________ -.JAnAIA2A:.A~AddressA;,Ah OutputA7AMA~ 1_Alnl_AIII_A121_CEi-· ....--...II00 IDataInput~HITACHI

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1----------------• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee.-0.3 - +7.0 VInput Voltage Yin.-0.3 -+7.0 VOperating Temperature Topr 0 -+70 °cStorage Temperature Tltu -55 - +150 °c- With respect to VSS (SYSTEM GND)(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operatingconditions. If these conditions are exceeded, it could affect reliability of LSI.• ELECTRIC~L CHARACTERISTICS• DC CHARACTERISTICS (Vee -5.0V±5%, Vss • OV, Ta • 0"'" +70°C; unless otherwise noted.)Item Symbol Test Condition min typ max Unit4.0VeeInput "High" VoltageVOther Inputs· 2.0VeeInput "Low" Voltage All Inputs· -0.3 0.8 V0.5Yin = 0- 2.4VInput Load Current SCI0.8 mA~--.---.----+----1r---_+---~EXTAL Vin=O-Vee - - 1.2Input Leakage Current NMI, IRa~. RESYin = 0 - 5.2_5_V_._~r--=-+--=--.+---21-0.5-+-IJ~A--Three State (Offset) PIO -P17 ,P30 '-P37~ II I V 05 24V ALeakage Current P ..... P ,TSI in = . ..... . - - 100 IJlO l4Output "High".VoltageP lO- P J7 t- --. I LOAD = -2051JA 2.4P40 - P47 , E, SCI, SCl ---1 VOH I LOAD = -145-'-IJ_A._-+-_2_.4-+__- __--II--_-_-i___--------~_O-t_h-er-O-u-t-p_ut-s----+i---+___'1 L=-:O::..:.A..:::D::...-= -100 IJA 2.4Output "Low" Voltage All Outputs VOL ILOAD = 1.6 mA0.5 vDarlington Drive Current PIO - PI7 -IOH V out = 1.5V 1.0 10.0 mAPower Dissipation 1200 mWCin Yin = OV. Ta = 25°C. ~-_-+--_-__ +-__ 1_2_.5---iInput CapacitancepFOther Inputs f = 1.0 MHz - - 12.5---------+---..----.-.--.-..- r------ f----... --.-.-------+----+-----t----+----PowerdownVSBB 4.0 - 5.25Vee StandbyvOperating VSB4.755.25Standby Current Powerdown ISBB VSBB = 4.0V 8.0 mA-Except Mode Programming Levels: See Figure 8.V542 _HITACHI

----------------H D68P01 V07, H D68P01 V07-1, H D68P01 MO, H D68P01 M0-1• AC CHARACTERISTICSBUS TIMING (Vee - 5.0V±5%, Vss = OV, Ta = 0 - +70 o C, unless otherwise noted.)ItemSymbolTest ConditionH D68POl V07/MOH068P01V07-1/MO-lmin typ max min typ maxCycle Time tcyc 1 - 10 0.8 - 10 IlSAddress Strobe Pulse width "High" PWASH 200 - - 150 - - nsAddress Strobe Rise Time tASr 5 - 50 5 - 50 nsAddress Strobe Fall Time tASf 5 - 50 5 - 50 nsAddress Strobe Delay Time tAsD 60 - - 30 - - nsEnable Rise Time t Er 5 - 50 5 - 50 nsEnable Fall Time tEf 5 - 50 5 - 50 nsEnable Pulse Width "High" Time PWEH 450 - - 340 - - nsEnable Pulse Width "Low" Time PWEL 450 - - 350 - - nsAddress Strobe to Enable Delay Time tASED 60 - - 30 - - nsAddress Delay Time tAD Fig. 1 - - 260 - - 260 nsAddress Delay Time for Latch (f = 1.0MHz) tADL Fig.2 - - 270 - - 260 nsData Set-up Write Time tDsw 225 - - 115 - - nsData Set-up Read Time toSR 80 - - 70 - - nsI Read tHR 10 - - 10 - -Data Hold TimensI WritetHW 20 - - 20 - -Address Set-up Time for Latch tASL 60 - - 50 - - nsAddress Hold Time for Latch tAHL 20 - - 20 - - nsAddress Hold Ti,!,e tAH 20 - - 20 - - nsPeripheral Read I Non-Multiplexed Bus (tACCN) - - (610) - - (420)Access Time I Multiplexed Bus (tACCM) - - (600) - - (420)Oscillator stabilization Time tRC Fig. 11 100 - - 100 - - msProcessor Control Set-up Time tpcs Fig. 12 200 - - 200 - - nsUnitnsPERIPHERAL PORT TIMING (Vee = 5.0V ±5%, Vss = OV, Ta '" 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition min typ max UnitPeripheral Data Setup Time Port 1,2,3,4 tposu Fig. 3 200 - - nsPeripheral Data Hold Time Port 1, 2,3,4 tpOH Fig.3 200 - - nsDelay Time, Enable Positive TransitiontOS01 Fig. 5 - 350 nsto 0S3 -Negative Transition--I--.Delay Time, Enable Positive Transitiontos02 Fig. 5 350 nsto 0S3 Positive Transition- -Delay Time, Enable NegativeTransition to Peripheral Data Port 1, 2*,3,4 tpwo Fig. 4 - - 400 nsValidDelay Time, Enable Negative*Transition to Peripheral Port 2**, 4 tCMOS Fig.4 - - 2.0 IlSCMOS Data ValidInput Strobe Pulse Width tPWIS Fig. 6 200 - - nsInput Data Hold Time port 3 tlH Fig. 6 50 - - nsInput Data Set-up Time Port 3 tiS Fig. 6 20 - - ns··10kn pull up register required for Port 2_HITACHI 543

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO·1----------------TIMER, SCI TIMING (Vee'" 5.0V ±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition minTimer Input Pulse Width tpwT 2tcyc+2ooDelay Time, Enable Positive Transition totTOD Fig. 7 -Timer Out--SCI Input Clock Cycle tscvc 1SCI Input Clock Pulse Width tpWSCK 0.4MODE PROGRAMMING (Vee = 5.0V ±5%. Vss" OV, Ta = 0 - +70°C, unless otherwise noted.)ItemMode Programming Input "low" VoltageMode Programming Input "High" VoltageRES "Low" Pulse WidthMode Programming Set-up TimeMode ProgrammingHold TimeAddress Strobe(AS)Enable(E)R/W .Ar-AU(Sell (Port4)MeUW,iteOn-O,.A.-A,(Port 3)MCU R.ad0.-0,. A.-A,(Port 3)2.4 v)VMPL -VMPH 4.0PW RSTL Fig. 8 3.0tMPS 2.0100tcyc .-J..-'\PWEH---O.SV ~r- ., IJ"'\""- -tEr -Symbol Test Condition minI RES Rise Time ~ 11ls0tMPHI RES Rise Time < 11ls.''V ,..\I-PWASH-06Vr--I-tASr -tASf-tASD- - r- ASED-\. pW EL-tEf-tADj~~--tAH2.2VAddress Valid\ O.6V.,'{.tASL-' I--'- ~tAHLtosw-- -tHW--~22V) i;~ess .l~JData Valid~) Valid06V if ~ O.6V-J--tADL--tOSR-I-tHR2.2V JI);1J.2.0VAddress.JI~Valid, Data Valid) .,1( ""O.6V ...l O.8V"jl(It ACCM)typ----typ------max Unit- ns600 ns- tcvc0.6 tScYCmaxUnit1.7 V- V- tcyc- tcyc--ns544Figure 1 Expanded Multiplexed Bus Timing$ HITACHI

----------------H068P01V07, H068P01V07-1, H068P01MO, H068P01M0-1EnlblelEI.O.SV -f\2~r-~tAO-PWELtcvc .~~PWEH :r~{~~- - -tEr - I--tEf-tAHAcr-A~Port4 IRm (SC21lOS (SCII22Vj~O.6V'Address Valid~MCUWrite0.-0,IPort 31MCU ReadO.6V\-ifi-tosw---tHWData Valid.. ~,'f...2.2V Jr--tOSR-ItACCNI . - -tHROala Valid0.-0, ----------------------------------------------(1IPort 31O.SV 1'---------'12.0VEFigure 2 Expanded Non-Multiplexed Bus Timingr- MCUWriter-MCUReadp •• -'.,p,. - Pt.' •• - P.,InputsPso - P"Inputs··Port 3 Non-Latched Operation ILATCH ENABLE = 01Figure 3Data Set-up and Hold TimesIMCU Read)All DataPort Outputs _________ JCMOSt -}_IPWO­" ----O.7VCC2.2V 0 .O.6V ata Valtd(NOTE) 1. 10 kfl Pullup.resistor required for Port 2 to reach 0.7 Vee2. Not applicable to PlI3. Port 4 cannot be pulled above VeeFigure 4Port Data Delay TimingIMCUWritelAddr ..,Bu.OS3-----....• Ace ... mltch .. Output Strobe Select lOSS" 0, I reed;OSS • 1, I writ.)Figure 5Port 3 Output Strobe Timing(Single Chip Mode)Figure 6Port 3 Latch Timing(Single Chip Mode)_HITACHI545

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1----------------T,me,Counte, ____ _J '----i~---J '-__ _P"Output(p~~d~2:~PP2t: )-----.:.::;:;..~['------""fFigure 7 Timer Output TimingFigure 8 Mode Programming TimingVecTest POint O~----I'" 30pFTest POInt 0-..-....-1 ....CRIS2074 ®0' EquIYC = 90 p F fo, P 3. -p .. , P 40 -P" ' E, SC I ' SC,= 30pF fo, P,. -P",P,.-P,.R = 12k Il fo, P 30 -P 37 . p •• - P" ' E, SC I ' SC,~ 24 kn for P,. -P", P,. -P,.(a) CMOS load(b) TTL loadFigure 9 Bus Timing Test Loads• INTRODUCTIONThe HD68POI is an 8-bit monolithic microcomputer whichcan be configured to function in a wide variety of applications.The facility which provides this extraordinary flexibilityis its ability to be hardware programmed into eight differentoperating modes. The operating mode controls the configurationof 18 of the MeU's 40 pins, available on-chip resources,memory map, location (internal or external) of interruptvectors, and type of external bus. The configuration of the remaining22 pins is not dependent on the operating mode.Twenty-nine pins are organized as three 8-bit ports and one5-bit port. Each port consists of at least a Data Register and awrite-only Data Direction Register. The Data Direction Registeris used to define whether corresponding bits in the Data Registerare configured as an input (clear) or output (set).The term "port", by itself, refers to all of its associated hardware.When the port is used as a "data port" or "I/O port", it iscontrolled by its Data Direction Register and the programmerhas direct access to its pins using the port's Data Register. Portpins are labled as Pij where i identifies one of four ports and jindicates the particular bit.The Microprocessor Unit (MPU) is an enhanced HD6800MPU with additional capabilities and greater throughput. It isupward source and object code compatible with the HD6800.The programming model is depicted in Figure 10 where AccumulatorD is a concatenation of Accumulators A and B. Alist of new operations added to the HMCS6800 instruction setare shown in Table 8.The basic difference between the HD6801 and the HD68POIis that the HD6801 has an on-chip ROM while the HD68POI has546 ~HITACHIan on the package EPROM. The HD68POI is pin and code compatiblewith the HD6801 and can be used to emulate theHD680 I, allowing easy software development using the onpackageEPROM. Software developed using the HD68POI canthen be masked into the HD6801 ROM.7r- - - _A.. - - -OUo~ _ - - .!3 ___ OOOJ A and B8-Bit Accumulators~ 1s~ Or 16-Bit DoubleFigure 10x 01SP 01PC 01Accumulator 0Index Register (X)Stack Pointer (SPIProgram Counter (PCICondition CodeRegister (CCRICarry/Borrow from MSBOverflowZeroNegativeInterruptHalf Carry (From Bit 3)HD68P01 Programming Model

_______----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1• INTERRUPTSThe MCU supports two types of interrupt requests: maskableand non-maskable. A Non-Maskable Interrupt (NMI) is alwaysrecognized and acted upon at the completion of the currentinstruction. Maskable interrupts are controlled by the ConditionCode Register's I-bit and by individual enable bits. The I-bitcontrols all maskable interrupts. Of the maskable interrupts,there are two types: IRQ, and IRQ2 . The Programmable Timerand Serial Communications Interface use an internallRQ2 interruptline, as shown in BLOCK DIAGRAM. External devices(and ISJ) use IRQ,. An IRQ, interrupt is serviced before IRQ2if both are pending.All mo; interrupts use hardware prioritized vectors. Thesingle SCI interrupt and three timer interrupts are serviced· in aprioritized order where each is vectored to a separate location.All MCU interrupt vector locations are shown in Table I.The Interrupt flowchart is depicted in Figure 13 and is commonto every MCU interrupt excluding Reset. The ProgramCounter, Index Register, A Accumulator, B Accumulator, andCondition Code Register are pushed to the stack. The I-bit isLa" InuruCllon -ICycle.1set to inhibit maskable interrupts and a vector is fetched correspondingto the current highest priority interrupt. The vectoris transferred to the Program Counter and instruction executionis resumed. Interrupt and RES timing is illustrated in Figure 11and 12.Table 1Interrupt Vector LocationsMSB lSB InterruptFFFE FFFF RESFFFC FFFO NMIFFFA FFFB Software Interrupt (SWI)FFF8 FFF9 IRQ, (or IS3)FFF6 FFF7 ICF (Input Capture)FFF4 FFF5 OCF (Output Compare)FFF2 FFF3 TOF (Timer Overflow)FFFO FFF1 SCI (RORF + ORFE + TORE)'nternalAdd'e .. Bus"""--+"--....,·-_.J~""-_"'''~'~_-'...__,'-_____,~_'''''_...J'___,,,"-_-,,,__NiMlo'IR;--------~\'_~ _____________________________________________ ___-II-'-'pcsInlernal_,~-"'---..,.--__ ,.--__ ~-'V""-........ .,..-""""~--v--""--v---~r----.v--"""",..--....,--v-­Do'. Bu • ..J\,--""-_-.J"'O-P-C-Od-.~O-P C-od-.. """P-C-O--P....Inlernal RfW• IRQ.; Internal InterruptC7'~P-C-8 ,-p-C 1"'~---.... "---"""---''''''-AC-C-8.J ... ---''-Ir-'.-I.-v.-nl.J .... -V.-CI-O'.J~--''' .... --.J'--\""' _____________________________ -J/0.1. MSB In""up. Rout,orFigure 11Interrupt SequenceA';;::"Sn;~.E ~\\~\\\\\\\\\~ ~\\\\\\\\\\\\\\\\ LJ1J"4 ~ ~--!>.7!>V . I l'Va:. 747!>V ')-l-----------------\\ , \ ~ I',------'RC------aL-'PCS .~ _IpcsREs 'l , r--7"4.0V "'\ 1..;O;,;;:.8;..;.V ______ _\\§\\\\\\\\\\\\\\\\\~ }sSS\\\\\\\SS\\\\\\\\\\S\\\\v-V ~ t:::x:::::x:::x~~ FFFEFFFEIn'ffn.1 RtW \\\\\\\\W.\\\\\\\\\\'{ ~\\\\\\S\\\\\SS\\\\\\\\\SSSY ~ ~~:,':r;~: &\\\\\\%\\\\\\\\~ '\%\\\\\\\\\\\\\S\\\\\\\\\\\\1G ~--.J-""""\..o'--""""r-~v--v--V'-~~NO'V"hdFigure 12Reset Timing~HITACHI 547

0::::tC1I~ 000 0)00~g

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1• FUNCTIONAL PIN DE~CRIPTIONS• Vee and VssVee and Vss provide power to a large portion of the MCU.The power supply should provide +5 volts (±5%) to Vee, andVss should be tied to ground. Total power dissipation (includingVee Standby), will not exceed PI) milliwatts.• Vee StandbyVee Standby provides power to the standby portion ($80through $BF) of the RAM and the STBY PWR and RAME bitsof the RAM Control Register. Voltage requirements depend onwhether the MCU is in a powerup or powerdown state. In thepowerup state, the power supply should provide +5 volts (±5%)and must reach VSB volts before RES reaches 4.0 volts. Duringpowerdown, Vee Standby must remain above VSBB (min) tosustain the standby RAM and STBY PWR bit. While in power·down operation, the standby current will not exceed ISBB.It is typical to power both Vee and Vee Standby from thesame source during normal operation. A diode must be usedbetween them to prevent supplying power to Vee duringTpowerdown operation. Vec Standby should be tied to eitherground or Vee in Mode 3.Vee 'tond'" Po~' Un.Figure 14Battery Backup for Vee Standby• RAM Control Register ($14)The RAM Con\rol Register includes two bits which can beused to control RAM accesses and determine the adequacy ofthe standby power source during powerdown operation. It isintended that RAME be cleared and STBY PWR be set as partof a powerdown procedure.• XTAL and EXTALThese two input pins interface either a crystal or TTL compatibleclock to the MCU's internal clock generator. Divide-byfourcircuitry is included which allows use of the inexpensive3.58 MHz Color Burst TV crystals. A 22 pF capacitor is requiredfrom each crystal pin to ground to ensure reliable startup andoperation. Alternatively, EXT AL may be driven with an externalTTL compatible clock with a duty cycle of 50% (±IO%)with XTAL connected to ground.The internal oscillator is designed to interface with an AT -cutquartz crystal resonator or a ceramic resonator operated in parallelresonance mode in the frequency range specified for 3.2 -4 MHz. The crystal should be mounted as close as possible tothe input pins to minimize output distortion and startup stabilizationtime. The MCU is compatible with most commerciallyavailable crystals and ceramic resonators and nominal crystalpa·rameters are shown in Figure 15.• RESThis input is used to reset the MCU's internal state and providean orderly startup procedure. During powerup, RES mustbe held below 0.8 volts: (I) at least tRC after Vee reaches 4.75volts in order to provide sufficient time for the clock generatorto stabilize, and (2) until V ce Standby reaches 4.75 volts. RESmust be held low at least three E-cycles if asserted during powerupoperation.When a "High" level is detected, the MCU does the following:I) All the higher order address lines will be forced "High".2) I/O Port 2 bits, 2, I, and 0 are latched into programmedcontrol bits PC2, PCI and PCO.3) The last two ($FFFE, $FFFF) locations in memory willbe used to load the program addressed by the programcounter.4) The interrupt mask bit is set; must be cleared before theCPU can recognize maskable interrupts ..• E (Enable)This is an output clock used primarily for bus synchronization.It is TTL compatible and is the slightly skewed divide-byfourresult of the MCU input frequency. It will drive oneSchottky TTL load and 90 pF, and all data given in cycles is referencedto this clock unless otherwise noted.I sp~; I RAME I XBit 0-5 Not UsedBit 6 RAMEBit 7 STBY PWRRAM Control Register6 5 4 3 2 oxRAM Enable. This Read/Write bit can beused to remove the entire RAM from theinternal memory map. RAME is set (enabled)during Reset provided standby~er is available on the positive edge ofRES. If RAME is clear, any access to aRAM address is external. If RAME is setand not in Mode 3, the RAM is includedin the internal map.Standby Power. This bit is a Read/Writestatus bit which is cleared whenever VeeStandby decreases below VSBB (min). Itcan be set ~ by software and is notaffected by RES.x• NM" (Non-Maskable Interrupt)An NMI negative edge request an CPU interrupt sequence,but the current instruction will be completed before it respondsto the request. The CPU will then begin an interrupt sequence.Finally, a vector is fetched from $FFFC and $FFFD, transferredto the Program Counter and instruction execution resumes.NMI typically requires a 3.3 kn (nominal) resistor toVee. There is no internal NMI pullup resistor. NMI must beheld low for at least one E-cycle to be recognized under allconditions.• IRQ1 (Maskable Interrupt Request 1)IRQt is a level-sensitive input which can be used to requestan interrupt sequence. The CPU will complete the current instructionbefore it responds to the request. If the interrupt maskbit (I-bit) in the Condition Code Register is clear, the CPU willbegin an interrupt sequence. Finally, a vector is fetched from$FFF8 and $FFF9, transferred to the Program Counter, andinstruction execution is resumed.tROt typically requires an external 3.3 kn (nominal) resistorto Vee for wire-OR application. tROt has no internalpullup resistor.~HITACHI 549

H D68P01 V07, HD68P01 V07-1, H D68P01 MO, HD68P01 M0-1----------------• SC1 and SC2 (Strobe Control 1 and 2)The function of SCI and SC 2 depends on the operatingmode. SC I is configured as an output in all modes exceptsingle chip mode, whereas SC 2 is always an output. SCI andSC 2 can drive one Schottky load and 90 pF.SC1 and SC2 in Single Chip ModeIn Single Chip Modes, SCI and SC 2 are configured as an in·put and output, respectively, and both function as Port 3 con·trol lines. SC I functions as IS3 and can be used to indicate thatPort 3 input data is ready or output data has been accepted:Three options associated with IS3 are controlled hy Port 3'sControl and Status Register and are discussed in Port 3's des·cription. If unused, IS3 can remain unconnected.SC 2 is configured as OS3 and can be used to strobe outputdata or acknowledge input data. It is controlled by OutputStrobe Select (OSS) in Port 3's Control and Status Register. Thestrobe is generated by a read (OSS= 0) or write (OSS = I) toPort 3's Data Register. OS3 timing is shown in Figure 5.Nominal Cryltll Parameter4 MHz5MHz~ ItemCo7 pF max. 4.7 pF max.Rs60n max.30n typoSC1 and SC2 in Expanded Non-Multiplexed ModeIn the Expanded Non-Multiplexed Mode, both SCI and SC 2are configured as outputs~ SC I functions as Input/Output Select(lOS) and is asserted only when $0100 through $OIFF is sensedon the internal address bus.SC 2 is configured as Read/Write and is used to control thedirection of data bus transfers. An CPU read is enabled whenRead/Write and E are high.SC1 and SC2 in Expanded Multiplexed ModeIn the Expanded Multiplexed Modes, both SCI and SC 2 areconfigured as outputs. SC I functions as Address Strobe and canbe used to demultiplex the eight least significant addresses andthe data bus. A latch controlled by Address Strobe captures addresson the negative edge, as shown in Figure 20.se 2 is configured as Read/Write and is used to control thedirection of data bus transfers. An CPU read is enabled whenRead/Write and E are high.2-----------~IO~1 -------------3XTAL 1---4.-----,2 3EXTAL ~--41"".....,CL1 = CL2 = 22pF ±20%(3.2 - 5 MHzl(Notel These are representativeAT cut parallel resonancecrystal parameters.CoEquivalent Circuit(al Nominal Recommended Crystal ParametersVee----------------'~1~4-.7-5-V------~:J~(-----------------------------ERES------------------+-----------~,~~-----tRe------~OscillatorStabil izationTime, tRef(b) Oscillator Stabilization Time hRC)Figure 15 Oscillator Characteristics550 $ HITACHI

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1• PORTSThere are four I/O ports on the MeU; three 8·bit ports andone S-bit port. There are two control lines associated with olleof the 8-bit ports. Each port has an associated write only DataDirection Register which allows each I/O line to be programmedto act as an input or an output. A "I" in the correspondingData Direction Register bit will cause that I/O line to be an out·put. A "0" in the corresponding Data Direction Register bit willcause the I/O line to be an input. There are four ports: Port 1.Port 2, Port 3, and Port 4. Their addresses and the addresses oftheir Data Direction registers are given in Table 2.two lines, IS3 and OS3, which can be used to control Port 3data transfers.Three Port J options are controlled by the Port 3 Controland Status Register and available only in Single-Chip Mode: (1)Port 3 input data can be latched using IS3 as a control signal,(2) OSJ can be generated by either an CPU read or write toPort J's Data Register, and (3) an IRQI interrupt can be en·abled by an IS3 negative edge. Port 3 latch timing is shown inFigure 6.Port 3 Control and Status RegisterTable 2 Port and Data Direction Register AddressesPortsPort AddressData DirectionRegister AddressI/O Port 1 $0002 $0000I/O Port 2 $0003 $0001I/O Port 3 $0006 $0004I/O Port 4 $OOQ1 $0005• P'0-P17 (Port 1)Port 1 is a mode independent 8-bit I/O port where each lineis an input or output as defined by its Data Direction Register.The TTL compatible three-state output buffers can drive oneSchottky TTL load and 30 pF, Darlington transistors, orCMOSdevices using external puUup resistors. It is configured as a datainput port by RES. Unused lines can remain unconnected.• Pau-PM (Port 2)Port 2 is a mode independent S-bit I/O port where each lineis configured by its Data Direction Register. During RES, alllines are configured as inputs. The TTL compatible three·stateoutput buffers can drive one Schottky TTL load and 30 pF orCMOS devices using external puUup resistors. P 20 , P 21 and P 22must always be connected to provide the operating mode., Iflines P 23 and P 24 are unused, they can remain unconnected.P 20 , P 2 ., and P 22 provide the operating mode which islatched into the Program Control Register on the positive edgeof RES. The mode may be read from Port 2 Data Register asshown where Pe2 is latched from pin 10.Port 2 also provides an interface for the Serial Communica·tions Interface and Timer. Bit I, if configured as an output, isdedicated to the timer's Output Compare function and cannotbe used to provide output from Port 2 Data Register.Port 2 Data RegisterI PC21 PCl I PCO I P24 I P23 I P22 I7 6 54321 0P21 I P20 $0003• P30-P37 (Port 3)Port 3 can be configured as an I/O port, a bidirectional 8·bitdata bus, or a multiplexed address/data bus depending on theoperating mode. The TTL compatible three·state output bufferscan drive one Schottky TTL load and 90 pF. Unused lines canremain unconnected.Bit 0-2Bit 3Bit 4Bit 5Bit 6Bit 7SOOOFNot used.LATCH ENABLE. This bit controls the inputlatch for Port 3. If set, input data islatched by an IS3 negative edge. The latchis transparent after a read of Port 3's Data~ster. LATCH ENABLE is cleared byRES.OSS (Output Strobe Select). This bit determineswhether OS3 will be generated by aread or write of Port 3's Data Register.When clear, the strobe is generated by aread; when set, i~eneratedby a write.OSS is cleared by RES.Not used.IS3 IRQ. ENABLE. When set, an IRQ.interrupt will be enabled whenever mFLAG is set; when clear, the interrupt isinhibited. This bit is cleared by RES.IS3 FLAG. This read-only status bit is setby an IS3 negative edge. It is cleared by aread of the Port 3 Control and StatusRegister (with lS3 FLAG set) followed bya read or write to Port 3's Data Register orby RES.Port 3 in Expanded Non·Multiplexed ModePort 3 is configured as a bidirectional data bus (Do - 0,) inthe Expanded Non·Multiplexed Mode. The direction of datatransfers is controlled by Read/Write (SC 2 ) and clocked by E(Enable).Port 3 in Expanded Multiplexed ModePort 3 is configured as a time multiplexed address (Ao"" A,)and data bus (0 0 -0,) in Expanded Multiplexed Mode whereAddress Strobe (AS) can be used to demultiplex the two buses.Port 3 is held in a high impedance state between valid addressand data to prevent potential bus conflicts.• P40-P47 (Port 4)Port 4 is configured as an 8-bit I/O port, address outputs, ordata inputs depending on the operating mode. Port 4 can driveone Schottky TTL load and 90 pF and is the only port withinternal pullup resistors. Unused lines can remain unconnected.Port 3 in Singl.-Chip ModePort 3 is an 8-bit I/O port in Single-Chip Mode where eachline is configured by its Data Direction Register. There are alsoPort 4 in Single Chip ModeIn Single Chip Mode, Port 4 functions as an 8-bit I/O portwhere each line is configured by its Data Direction Register.~HITACHI 551

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1----------------Internal pull up resistors allow the port to directly interface withCMOS at 5 volt levels. External pullup resistors to more than 5volts, however, cannot be used.Port 4 in Expanded Non-Multi.e!!!.ed ModePort 4 is configured from RES as an 8-bit input port whereits Data Direction Register can be written to provide any or allof address lines, Ao to A,. Internal pullup resistors are intendedto pull the lines high until its Data Direction Register isconfigured.Port 4 in Expanded Multiplexed ModeIn all Expanded Multiplexed modes except Mode 6. Port 4functions as half of the address bus aE!Erovides As to Als .InMode 6, the port- is configured from RES as an 8-bit parallel inputport where its Data Direction Register can be written toprovide any or all of address lines, As to Als . Internal pullupresistors are intended to pull the lines high until its Data Direc·tion Register is configured where bit 0 controls A8 .• OPERATING MODESThe MCU provides eight different operating modes which areselectable by hardware programming and referred to as Mode 0through Mode 7. The operating mode controls the memorymap, configuration of Port 3, Port 4. sr I ,sr 2. and the physicallocation of interrupt vectors.• Fundamental Mode.The MCU's eight modes can be grouped into three fundamentalmodes which refer to the type of bus it supports: SingleChip, Expanded Non-Multiplexed, and Expanded Multiplexed.Single chip modes include 4 and 7. Expanded Non-Multiplexedis Mode 5 and the remaining five are Expanded Multiplexedmodes. Table 3 summarizes the characteristics of the operatingmodes.Single Chip Mode. (4, 7)In Single-Chip Mode, the MCU's four ports are configured asparallel input/output data ports, as shown in Figure 16. TheMCU functions as a monolithic microcomputer in these twomodes without external address or data buses. A maximum of29 I/O lines and two Port 3 control lines are provided. In additionto other peripherals, another MCU can be interfaced toPort 3 in a loosely coupled dual processor configuration. asshown in Figure 17.In Single-Chip Test Mode (4), the RAM responds to $XX80through $XXFF and the ROM is removed from the internal addressmap. A test program must first be loaded into the RAMusing modes 0, 1, 2, or 6. If the MCV is Reset and then programmedinto Mode 4, execution will begin at $XXFE: XXFF.Mode 5 can be irreversibly entered from Mode 4 without goingthrough Reset by setting bit 5 of Port 2's Data Register. Thismode is used primarily to test Ports 3 and 4 in the Single-Chipand Non-Multiplexed Modes.552 $ HITACHIExpanded Non-Multiplexed Mode (5)A modest amount of external memory space is provided inthe Expanded Non-Multiplexed Mode while retaining significanton-chip resources. Port 3 functions as an 8-bit bidirectionaldata bus and Port 4 is configured as an input data port. Anycombination of the eight least-significant address lines may beobtained by writing to Port 4's Data Direction Register. Stated.alternatively, any combination of Ao to A, may be providedwhile retaining the remainder as input data lines. Internal pullupresistors are intended to pull Port 4's lines high until it isconfigured.Figure 18 illustrates a typical system configuration in theExpanded Non-Multiplexed Mode. The MCU interfaces directlywith HMCS6800 family parts and can access 256 bytes ofexternal address space at $100 through $IFF. lOS provides anaddress decode of external memory ($100-$1 FF) and canbe used similarly to an address or chip select line.Table 3 Summary of H06S00 Operating ModesCommon to all Modes:Reserved Register AreaPort 1Port 2Programmable TimerSerial Communication InterfaceSingle Chip Mode 7128 bytes of RAM; 2048 bytes of ROMPort 3 is a parallel I/O port with two control linesPort 4 is a parallel I/O portSCI is Input Strobe 3 (lS31SC2 is Output Strobe 3 (0531Expanded Non·Multiplexed Mode 5128 bytes of RAM; 2048 bytes of ROM256 bytes of external memory spacePort 3 is an 8·bit data busPort 4 is an input port/address busSCI is Input/Output Select (lOSISC2 is read/write (R/WIExpanded Multiplexed Modes 1, 2, 3, 6Four memory space options (65k address space I :(11 No internal RAM or ROM (Mode 31(21 Internal RAM, no ROM (Mode 21(31 Internal RAM and ROM (Mode 11(41 Internal RAM, ROM with partial address bus (Mode 61Port 3 is a multiplexed address/data busPort 4 is an address bus (inputs/address in Mode 61SCI is Address Strobe (ASISC2 is ReadlWrite (RMITest Modes 0 and 4Expanded Multiplexed Test Mode 0May be used to test RAM and ROMSingle Chip and Non·Multiplexed Test Mode 4(1) May be changed to Mode 5 without going thr')ugh Reset(21 May be used to test Ports 3 and 4 as I/O portsExpanded-Multiplexed Modes (0, 1,2, 3, 6)In the Expanded-Multiplexed Modes, the MCV has the abilityto access a 65k bytes memory space. Port 3 functions as a timemultiplexed address/data bus with address valid on the negativeedge of Address Strobe (AS) and the data bus valid while E ishigh. In Modes 0 to 3, Port 4 provides address line~ to Al s.In Mode 6, however, Port 4 is configured during RES as dataport inputs and the Data Direction Register can be changed toprovide any combination of address lines, As to Ais . Statedalternatively, any subset of As to Al S can be provided whileretaining the remainder as input data lines. Internal pullupresistors are intended to pull Port 4's lines high until softwareconfigures the port.Figure 19 depicts a typical configuration for the Expanded­Multiplexed Modes. Address Strobe can be used to control atransparent D-type latch to capture addresses Ao to A" asshown in Figure 20. This allows Port 3 to function as a Data Buswhen E is high.In Mode 0, the Reset vector is external for the first two E­cycles after the positive edge of RES and internal thereafter. In

-----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1addition, the internal and external data buses are connected andthere must be no memory map overlap to avoid potential busconflicts. Mode 0 is used primarily to verify the ROM patternand monitor the internal data bus with the automated testequipment.VeeVee.. - XTAL --·.eXTALVeePorI 18110 LinesPort 381/0 LinesI'orll81/0LinesPort 181/0LinesPorI 48110 LinesPorI 25 I/O LinesSerial 11016·Bit TimerPort 251/0 LinesSCI16-Bil TimerVssVssLinesFigure 16 Single Chip Mode 16-Bil TimerFigure 17VssSingle Chip Dual Processor ConfigurationPort 481/0LinesVeeVeePorI 181/0 LinesPort 251/0LinesSerilil/O16·Bil TimerVssPort 38 Dala LinesPort 4To8PorI 181/0Port 25110SCITimerH068POIVssFigure 18Expanded Non·Multiplexed ConfigurationVeeVeeXTALPorI 18110 LinesPort 25110 LinesSerial 1/016-8il TimerPort 38 LinesMultiplexed DatalAddressPOrt 48 linesAddress BusPort 25S~~ 4II •• HTimerL..--r--~~~~--1'6~'-~------r1-------'-+--~~:~~~~SHD68POI A/W A/ViVssVssFigure 19Expanded Multiplexed Configuration4!)HITACHI 553

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------GNDASPort 3 [Address/DataIG OCD. a.74LS373(Typical)08 a" -) A .... u A"-~'FunctionTableOutput Enable OutputControl G 0 aL H H HL H L LL L X 00-H X X Z-Figure 20Typical Latch Arrangement• Programming The ModeThe operating mode is programmed by the levels asserted onP 22 , P 2 t, and P 20 which are latched into PC2, PCI, and PCO ofthe program control register on the positive edge of RES. Theoperating mode may be read from Port 2 Data Register asshown below, and programming levels and timing must be metas shown in Figure 8. A brief outline of the operating modes isshown in Table 4.Circuitry to provide the programming levels is dependentprimarily on the normal system usage of the three pins. If configuredas outputs, the circuit shown in Figure 21 may be used;otherwise, three-state buffers can be used to provide isolationwhile programming the mode.Port 2 Data Register7 6 543 2 1 0\ PC2\ PCl \ PCO \ P24\ P23\ P221 P21 I P20 I $0003Table 4 Mode Selection SummaryMode76S43210P 22(PC2)HHHHP 2 •(PC1)HHLLHHLLLegend:I - InternalE - ExternalMUX - MultiplexedNMUX - Non-MultiplexedL - Logic "0"H - Logic "1"LLLLP 20 Interrupt BusROM RAM(PCO)Vectors ModeOperating ModeH I.- ._-------_.I IISingle ChipL I I IMUXl5,61 MultiplexedlPartial DecodeH I I INMUX(5,61 Non·Muitiplexed/Partiai DecodeL 1(21 1111 IISingle Chip Test--H E E EMUX(41 Multiplexed /No RAM or ROML E I EMUXI41 Multiplexed /RAMH I I EMUX(41 Multiplexed/RAM & ROML I I 1131 MUX(41 Multiplexed TestNotes:(1) Internal RAM is addressed at $XX80(2) Internal ROM is disabled(3) RES vector is external for 2 cycles after RES goes high(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3(5) Addresses associated with Port ~ are considered external in Modes 5 and 6(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register554~HITACHI

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1Vee(R ,~ ~~:RI RI RII I I6RESA B CXoHD6BPOlVo X8P 20 (PCO)9~ Zo V P 21 (PC1)XIVIZI( ( (C1 ??? ModeControl~ SwitchFigure 21InhJ,ZHD14053B10 P22 (PC2)[NOTES]Recommended Circuit for Mode Selection1) Mode 7 as shown2) RC :::::: Reset time constant3) RI = 10knInhABCBinary to 1·of·2Decoder withInhibitXO~----------------~~~~4-+---'XI~-------------------K~~4-+-~VO~--------------------~~4-+---'VI~----------------------~H-+-~Zo~------------------------~~~Zlcr------------------------~C*~XVZTruth TableControl InputOn SwitchSelectInhibitC B A HD14053B-0 0 0 0 Zo Vo Xo0- -0 0 1 Zo Vo XI0-----0 1 0 Zo VI Xo0 0 1 1 Zo VI XI0 1 0 0 ZI Vo Xo0 1 0 1 ZI Vo XI0 1 1 0 ZI VI Xo0 1 1 1 ZI VI XI1 X X X -Figure 22HD14053B Multiplexers/Demultiplexers~HITACHI555

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------• MEMORY MAPSThe MeV can provide up to 65k bytes address space dependingon the operating mode. The HD68POI provides 8k bytes addressspace for EPROM, but the maps differ in EPROM types asfonows.1) HN482732A (a 4k.byte EPROM)In order to support the HD6801VO, EPROM of theHD68POIV07/HD68POIV07·1 must be located at $FOOO·$FFFF.2) HN482764 (a 8k·byte EPROM)The HD68PO 1 MO/HD68PO 1 MO·l can provide up to8k bytes address space using HN482764 instead ofHN482732A. In this case, EPROM of the HD68POIMO/HD68POIMO·I is located at $EOOO·$FFFF.A memory map for each operating mode is shown in Figure23. The first 32 locations of each map are reserved for theMeV's internal register area, as shown in Table 5, with excep·tions as indicated.Refer to "Precaution when emulating the HD6801 Family".Table 5 Internal Register AreaRegisterAddressPort 1 Data Direction Register--· 00Port 2 Data Direction Register··· 01Port 1 Data Register 02Port 2 Data Register 03Port 3 Data Direction Register-·· 04·Port 4 Data Direction Register···OS··Port 3 Data Register 06·Port 4 Data Register 07··Timer Control and Status Register 08Counter (High Byte) 09Counter (low Byte)OAOutput Compare Register (High Byte)OBOutput Compare Register (low Byte)OCInput capture Register (High Byte) 00Input capture Register (low Byte)OEPort 3 control and Status RegisterOF·Rate and Mode Control Register 10Transmit/Receive Control and Status Register 11Receive Data Register 12Transmit Data Register 13RAM Control Register 14Reserved1S·1F• External address in Modes 0, 1, 2, 3, 5, 6; cannot be eccessed inMode S (No iOS)•• External addresses in Modes 0, 1, 2, 3••• 1 • Output, 0 • Input556 ~HITACHI

-----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1Multiplexed Test modeHD68POlModeoMultiplexed/RAM & EPROMHD68POlMode1$0000(1)$OOlFInternal RegistersExternal Memory Space$0000(1)$OOlFInternal RegistersExternal Memory Space$0080$0080$OOFFInternal RAM$OOFFInternal RAMExternal Memory SpaceExternal Memory Space$EOOO$FFFF(2)EPROMInternal Interrupt Vectors(2$EOOO$FFEF$FFFO$FFFF----...EPROMExternal Interrupt Vectors(NOTES(1) Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and $OF2) Addresses $FFFE and $FFFF are consideredexternal if accessed within 2 cycles alter apositive edge of RES and internal at all othertimes.3) After 2 CPU cycles, there must be no over·lapping of internal and external memoryspaces to avoid driving the data bus with morethan one device.4) This mode is the only mode which may be usedto examine the interrupt vectors in EPROMusing an external Reset vector.[NOTES]1) Excludes the following addresses which maybe used externally; $04, $05, $06, $07 and$OF.2) EPROM addresses $FFFO to $FFFF arenot usable.Figure 23HD68POl Memory Maps~HITACHI 557

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO·1----------------HD68POlMode2HD68POlMode3Multiplexed/RAM$0000(1)Internal Registers$001FExternal Memory Space$0080Internal RAMMultiplexed/No RAM or EPROM$0000(1)} Internal Registers$001F$ooFFExternal Memory SpaceExternal Memory Space$FFFO ~----t:$FFFF '-___....} External Interrupt Vectors$FF FO I-----t ~$FFFF .....___ } External Interrupt Vectors....(NOTE)11 Excludes the following addresses which maybe used externally: $04, $05, $06, $07, and$OF.(NOTE)11 Excludes the following addresses which maybe used externally: $04, $05, $06, $07 and$OF.Figure 23HD68POl Memory Maps (Continued)558 $ HITACHI

----------------H D68P01 V07, H D68P01 V07-1, H D68P01 MO, H D68P01 M0.1HD68P014ModeHD68P01Mode5Single Chip TestNon-Multiplexed/Partial Decode$0000$001F} Internal RegistersUe(1)(4)$0080$OOFFInternal RAM}$0100 }----t......_"" External Memory Space$01FF L$EOOOEPROM$XX80$XXFF}Internal RAMInternal Interrupt Vectors$FFFFInternal Interrupt Vectors[NOTES]1) The internal ROM is disabled.2) Mode 4 may be changed to Mode 5 withouthaving to assert RESET by writing a "1" intothe peo bit of port 2 Data Register.3) Addresses A. to AI 5 are treated as "don'tcares" to decode internal RAM.4) Internal RAM will appear at $XX80 to $XXFF.[NOTES]1) Excludes the following addresses which maynot be used externally: $04, $06, and $OF.(No 105)2) This mode may be entered without goingthrough RESET by using Mode 4 and subsequentlywriting a "1" into the peo bit ofPort 2 Data Register.3) Address lines Ao -A, will not contain addressesuntil the Data Direction Register for Port 4has been written with "1 's" in the appropriatebits. These address lines will assert "1 's" untilmade outputs by writing the Data DirectionRegister.Figure 23HD68P01 Memory Maps (Continued)~HITACHI 559

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1----------------HD68P01Mode6HD68P01Mode7Multiplexed/Partial DecodeSingle Chip$0000(1)$OOlF$0080$OOFFInternal RegistersExternal Me",ory SpaceInternal RAM$0000SOOlF$0080$OOFF} Internal RegistersExternal Memory Space$EOOO$FFFFIEPROMInternal Interrupt Vectors$EOOO$FFFFEPROMInternal Interrupt Vectors[NOTES)1) Excludes the following address which may beused externally: $04, $06, $OF.2) Address lines A. -A,s will not containaddresses until the Data Direction Register forPort 4 has been written with "l's" in theappropriate bits. These address lines willassert "l's" until made outputs by writing theData Direction Register.Figure 23 HD68P01 Memory Maps (Continued)560$ HITACHI

----------------HD68POl V07, HD68POl V07-1, HD68P01MO, HD68POl MO-l• PROGRAMMABLE TIMEThe Programmable Timer can be used to perform input waveformmeasurements while independently generating an outputwaveform. Pulse widths can vary from several microseconds tomany seconds. A block diagram of the Timer is shown in Figure24.• Counter ($09:0A)The key timer element is a 16-bit free-running counter whichis incremented by E (Enable). It is cleared during RES and isread-only with one exception: a write to the counter ($09) willpreset it to $FFF8. This feature, intended for testing, can disturbserial operations because the counter provides the SCI'sinternal bit rate clock. TOF is set whenever the counter containsaliI's.• Output Compare Register ($OB:OC)The Output Compare Register is a 16-bit Read/Write registerused to control an output waveform or provide an arbitrarytimeout flag. It is compared with the free-running counter oneach E-cycle. When a match is found, OCF is set and OLVL isclocked to an output level register. If Port 2, bit I, is configuredas an output, OLVL will appear at P 21 and the Output CompareRegister and OLVL can then be changed for the next compare.The function is inhibited for one cycle after a write to its highbyte of the Compare Resister ($08) to ensure a valid compare.The Output Compare Register is set to $FFFF by RES.• Input Capture Register ($00: OE)The Input Capture Register is a 16·bit read-only register usedto store the free-running counter when a "proper" input transitionoccurs as defined by IEOG. Port 2, bit 0 should be configuredas an input, but the edge detect circuit always senses P 20even when configured as an output. An input capture can occurindependently of ICF: the register always contains the most currentvalue. Counter transfer is inhibited, however, between accessesof a double byte CPU read. The input pulse width mustbe at least two E-cycles to ensure an input capture under allconditions.• Timer Control and Status Register ($08)The Timer Control and Status Register (TCSR) is an 8-bitregister of which all bits are readable while bits 0-4 can bewritten. The three most significant bits provide the timer'sstatus and indicate if:• a proper level transition has been dtected,• a match has been found between the free-running counterand the output compare register, and• the free-running counter has overflowed.Each of the three events can generate an IRQ2 interrupt andis controlled by an individual enable bit in the TCSR.HD68P01 Internal BusTimer bJr---+-i,..------'ControlAnd Ip-..... --'....... ~.,....l...,....a...~--.... II StatusRegister$08 Bit 1Port 2DDRII_____: Output InputLevel EdgeBit 1 Bit 0Port 2 Port 2Figure 24Block Diagram of Programmable TimerC!)HITACHI 561

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1----------------Timer Control and Status Register (TCSR)7 6 543 2 1 0IrcF I OCF I TOF I Ercrl Eocrl ETOrlrEDGloLVL I $0008Bit 0 OLVLBit I IEDGBit 2 ETOIBit 3 EOCIBit 4 EICIBit 5 TOFBit 6 OFCOutput level. OLVL is clocked to the outputlevel register by a successful output compare andwill appear at P 21 if Bit I of Port 2's Data DirectionRegister is set. It is cleared by RES.Input Edge. IEDG is cleared by RES and controlswhich level transition will trigger a counter transferto the Input Capture Register:IEDG 0 Transfer on a negative-edgeII~DG = 1 Transfer on a positive-edge.Enable Timer .overflow Interrupt. When set, anIRQ2 interrupt is enabled for a timer overflow;when clear, the interrupt is inhibited. It is clearedby RES.Enable Output Compare Interrupt. When set, anIRQ2 interrupt is enabled for an output compare;when clear, the interrupt is inhibited. It iscleared by RES.Enable Input Capture Interrupt. When set, anIRQ2 interrupt is enabled for an input capture;when clea~the interrupt is inhibited. It iscleared by RES.Timer Overflow Flag. TOF is set when thecounter contains all I's. It is cleared by readingthe TCSR (with TOF set) followed by thecounter's high byte ($09), or by RES.Output Compare Flag. OCF is set when the OutputCompare Register matches the free-runningcounter. It is cleared by reading the TCSR(withOCF set) and then writing to the Output CompareRegister ($OB or SOC), or by RES., Bit 7 ICF Input Capture Flag. ICF is set to indicate aproper level transition; it is cleared by readingthe TCSR (with ICF set) and then the InputCapture Register High Byte (SOD), or by RES.• SERIAL COMMUNICATIONS INTERFACE (SCI)A full-duplex asynchronous Serial Communications Interface(SCI) is provided with a data format and a variety of rates. TheSCI transmitter and receiver are functi!Jnally independent, butuse the same data format and bit rate. Serial data format isstandard mark/space (NRZ) and provides one start bit, eightdata bits, and one stop bit. "Baud" and "bit rate" are usedsynonymously in the following description.• clock: external or internal bit rate clock- Baud (or bit rate): one of 4 per E-clock frequency, or externalbit rate (X8) input• wake.up feature: enabled or disabled• interrupt requests: enabled individually for transmitterand receiver• clock output: internal bit rate clock enabled or disabledto P 22• Port 2 (bit 3,4): dedicated or not dedicated to serial I/Oindividually for transmitter and receiver.• Serial Communications RegistersThe Serial Communications Interface includes four addres·sable registers as depicted in Figure 25. It is controlled by theRate and Mode Control Register and the Transmit/Receive Controland Status Register. Data is transmitted and received utilizinga write-only Transmit Register and a read-only ReceiveRegister. The shift registers are not accessible to software.Port 2C~~k ..... --=.I=-O ______ ..2Bit 7 Rate and Mode Control Reginer Bit 0I X I X I X I X I CCI I CCO 1551 1 SSO IS10TIC~t ~~12~ _________ __Transmit/Receive Control and Status RegisterFigure 25Receive Shift RegisterTransmit Shift RegisterTransmit Data RegisterSCI Registers...... ---E$12$13• W.ke-Up F •• tur.In a typical serial loop multi-processor configuration, thesoftware protocol will usually identify the addresse(s) at thebeginning of the message. In order to permit uninterested MCU'sto ignore the remainder of the message, a wake-up feature isincluded whereby all further SCI receiver flag (and interrupt)processing can be inhibited until its data line goes idle. An SCIreceiver is re-enabled by an idle string of ten consecutive 1 '5 orby RES. Software must provide for the required idle stringbetween consecutive messages and prevent it within messages.• Progr.mm.bI. Option,The foUowing features of the SCI are programmable:• format: Standard mark/space (NRZ)562 _HITACHIRat. and Mode Control Register (RMeR) ($10)The Rate and Mode Control Register controls the SCI bitrate, format, clock source, and under certain conditions, theconfiguration of P22 . The !!S!.ster consists of four write-onlybits which are cleared by RES. The two least significant bitscontrol the bit rate of the internal clock and the remaining twobits control the format and clock source.Rate and Mode Control Register (RMCR)7 654 3 2 1 0x x I x I x I CC1 I cco I SS1 I sso I $001 0

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1Bit I: Bit 0 SSI: SSO Speed Select. These two bits select theBaud when using the internal clock. Four ratesmay be selected which are a function of the MCUinput frequency. Table 6 lists bit time and ratesfor three selected MCU frequencies.Bit 3: Bit 2 CCI :CCO Clock Control Select. These two bitsselect the serial clock source. If CCI is set, theDDR value for P22 is forced to the complementof CCO and cannot be altered until CCI iscleared. If CCI is cleared after having been set,its DDR value is unchanged. Table 7 defines theclock source, and use ofP22 .If both CCI and CCO are set, an external TTL compatibleclock must be connected to P22 at eight times (8X) the desiredbit rate, but not greater than E, with a duty cycle of 50% (±10%). If CC I :CCO = 10, the internal bit rate clock is provided atPH regardless of the values for TE or RE.(Note) The source of SCI internal bit rate clock is the timer's free run·ning counter. An CPU write to the counter can disturb serialoperations.Transmit/Receive Control and Status Register (TRCSR) ($11)The Transmit/Receive Control and Status Register controlsthe transmitter, receiver, wake-up feature, and two individualinterrupts and monitors the status of serial operations. All eightbits are readable while bits 0 to 4 are also writable. The registeris initialized to $20 by RES.Transmit/Receive Control and Status Register (TRCSR)BitOWUBit I TE7 6 543 210"Wake-up" on Idle Line. When set, WU enablesthe wake-up function; it is cleared by ten consecutivel's or by RES. WU will not set if the lineis idle.Transmit Enable. When set, P 24 DDR bit is set,cannot be changed, and will remain set if TE issubsequently cleared. When TE is changed fromclear to set, the transmitter is connected to P 24Bit 2 TIEBit 3 REBit 4 RIEBit 5 TOREBit 60RFEBit 7 RDRFand a preamble of nine consecutive I's is trans-­mitted. TE is cleared by RES.Transmit Interrupt Enable. When set, an IRQ2interrupt is enabled when TDRE is set; whenclear, the interrupt is inhibited. TE is cleared byRES.Receive Enable. When set, P23 's DDR bit iscleared, cannot be changed, and will remain clearif RE is subsequently cleared. While RE is set,~SCI receiver is enabled. RE is cleared byRES.Receiver Interrupt Enable. When set, an IRQ2interrupt is enabled when RDRF and/or ORFE isset; when clear, the interrupt is inhibited. RIE iscleared by RES.Transmit Data Register Empty. TDRE is setwhen the Transmit Data Register is transferred tothe output serial shift register or by RES. It iscleared by reading the TRCSR (with TDRE set)and then writing to the Transmit Datil Register.Additional data will be transmitted only if TDREhas been cleared.Overrun Framing Error. If set, ORFE indicateseither an overrun or framing error. An overrun isa new byte ready to transfer to the Receiver DataRegister with RDRF still set. A receiver framingerror has occurred when the byte boundaries ofthe bit stream are not synchronized to the bitcounter. An overrun can be distinguished from aframing error by the value of RDRF: if RDRF isset, then an overrun has occurred; otherwise aframing error has been detected. Data is nottransferred to the Receive Data Register in anoverrun or framing error condition_ ORFE iscleared by reading the TRCSR (with ORFE set)then the Receive Data Register, or by RES.Receive Data Register Full. RDRF is set whenthe input serial shift register is transferred to theReceive Data Register. It is cleared by readingthe TRCSR (with RDRF set), and then the ReceiveData Register, or by RES.Table 6 SCI Bit Times and RatesXTAL 2.4576 MHz 4.0 MHz 4.9152 MHz*SSl : SSO E 614.4 kHz 1.0 MHz 1.2288 MHz0 0 E + 16 26 /ls/38.400 Baud 16 /ls/62,500 Baud 13 J,Ls/76,800 Baud0 1 E+ 128 20Sl-ts/4,800 Baud 128/ls/7812.5 Baud 104.2 J,Ls/9,600 Baud1 0 E + ~024 1.67ms/600 Baud 1.024ms/976.6 Baud 833.3 J,Ls/l,200 Baud1 1 E + 4096 6.67ms/150 Baud 4.096ms/244.1 Baud 3.33 ms/300 Baud* HD68P01V07-1, HD68P01MO-l onlyTable 7 SCI Format and Clock Source ControlCC1: CCO Format Clock Source Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 40 0 - - - ** **0 1 NRZ Internal Not Used ** **1 0 NRZ Internal Output* ** **1 1 NRZ External Input ** **• Clock output is available regardless of values for bits RE and TE .•• Bit 3 is used for serial input if RE .. "'" in TRCS; bit 4 is used for serial output if TE = "'" in TRCS.~HITACHI 563

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------• Internilly G,nerated ClcokIf the user wishes for the serial I/O to furnish a clock, the fol·lowing requirements are applicable:• the values of RE and TE are immaterial.• CC1, CCO must be set to 10• the maximum clock rate will be E + 16.• the clock will be at 1 X the bit rate and will have a risingedge at mid·bit.• Externilly G,nerlted ClockIf the user wishes to provide an external clock for the serialI/O, the following requirements are applicable:• the CCl, CCO, field in the Rate and Mode Control Re·gister must be set to 11,• the external clock must be set to 8 times (X8) the desiredbaud rate and• the maximum external clock frequency is 1.0 MHz.• Strill OperationsThe SCI is initialized by writing control bytes first to theRate and Mode Control Register and then to the Transmit/Re·ceive Control and Status Register.The Transmitter Enable (TE) and Receiver Enable (RE) bitsmay be left set for dedicated operations.Transmit operationsThe transmit operation is enabled by TE in the Transmit/Re·ceive Control and Status Register. When TE is set, the output ofthe transmit serial shift register is connected to P 24 and theserial output by first transmitting to a ten·bit preamble of 1 'soFollowing the preamble, internal synchronization is establishedand the transmitter section is ready for operation.At this point one of two situation exist:I) if'the Transmit Data Register is empty (TORE = I), awn·tinuous string of ones will be sent indicating an idle line,or,2) if a byte has been written to the Transmit Data Register(TDRE.= 0), it is transferred to the output serial shift reg·ister and transmission will begin.During the transfer itself, the start bit (0) is first transmitted.Then the 8 data bits (beginning with bit 0) followed by the stopbit (1), are transmitted. When the Transmitter Data Register hasbeen emptied, the TORE flag bit is set.If the MCU fails to respond to the flag within the pro·per time, (TORE is still set when the next normal transfer fromthe parallel data register to the serial output register shouldoccur) then a 1 will be sent (instead of a 0) at "Start" bit time,followed by more 1 's until more data is supplied to the dataregister. No O's will be sent while TORE remains a 1.Receive OperltionsThe receive operation is enabled by RE which configuresP 23 • The receive operation is controled by the contents of theTransmit/Receive Control and Status Register and the Rate andMode Control Register.The receiver bit interval is divided into 8 sub·intervals forinternal synchronization. In the NRZ Mode, the received bitstream is synchronized by the first 0 (space) encountered.The approximate center of each bit time is strobed duringthe next 10 bits. If the tenth bit is not a I (stop bit) a framingerror is assumed, and ORFE is set. If the tenth bit is ai, thedata is transferred to the Receive Data Register, and interruptflag RDRF is set. If RDRF is still set at the next tenth bit time,ORFE will be set, indicating an over·run has occurred. When theMCU responds to either flag (RDRF or ORFE) by readingthe status register followed by reading the Data Register, RDRF(or ORFE) will be cieared.• INSTRUCTION SETThe HD68PO 1 is upward source and object code compatiblewith the HD6800. Execution times of key instructions havebeen reduced and several new instructions have been added,including hardware multiply. A list of new operations added tothe HD6800 instruction set is shown in Table 8.In addition, two new special opcodes, 4E and SE, are provid.ed for test purposes. These opcodes force the Program Counterto increment like a 16-bit counter, causing address lines usedin the expanded modes to increment until the device is reset.These opcodes have no mnemonics.InstructionABXADDDASLDBRNLDDLSRDMULPSHXPULXSTDSUBDTable 8 New InstructionsDescriptionUnsigned addition of Accumulator B to Index RegisterAdds (without carry) the double accumulator to memory and leaves the sum in the double accumulatorShifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C·bitBranch NeverLoads double accumulator from memoryShifts the double accumulator right (towards LSS) one bit; the MSS is cleared and the LSS is shifted into the C·bitUnsigned multiply; multiplies the two accumulators and leaves the product in the double accumulatorPushes the Index Register to stackPulls the Index Register from stackStores the double accumulator to memorySubtracts memory from the double accumulator and leaves the difference in the double accumulator564~HITACHI

-----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-l• Programming ModelA programming model for the HD68POI is shown in Figure10. Accumulator A can be concatenated with accumulator Band jointly referred to as accumulator D where A is the mostsignificant byte. Any operation which modifies the doubleaccumulator will also modify accumulator A and/or B. Otherregisters are defined as follows:Program CounterThe program counter is a 16-bit register which always pointsto the next instruction.Stack PointerThe stack pointer is a 16-bit register which contains the addressof the next available location in a pushdown/pullup(LIFO) queue. The stack resides in random access memory at alocation defined by the programmer.Index RegisterThe Index Register is a 16-bit register which can be used tostore data or provide an address for the indexed mode ofaddressing.AccumulatorsThe CPU contains two 8-bit accumulators, A and B, whichare used to store operands and results from the arithmetic logicunit (ALU). They can also be concatenated and referred to asthe D ( double) accumulator.Condition Code RegistersThe condition code register indicates the results of an instructionand includes the following five condition· bits: Nega·tive (N), Zero (Z), Overflow (V), Carry/Borrow from MSB (C),and Half Carry from bit 3 (H). These bits are testable by theconditional branch instruction. Bit 4 is the interrupt mask(I-bit) and inhibits all maskable interrupts when set. The twounused bits, b6 and b7 are read as ones.• Addressing Mod ..The CPU provides six addressing modes which can be usedto reference memory. A summary of addressing modes for allinstructions is presented in Table 9, 10, II, and 12 where executiontimes are provided in E-cycles. Instruction execution timesare summarized in Table 13. With an input frequency of 4 MHz,E-cycles are equivalent to microseconds. A cycle.by-cycledescription of bus activity for each instruction is provided inTable 14 and a description of selected instructions is shown inFigure 26.Immediate AddressingThe operand or "immediate byte(s)" is contained in the followingbyte(s) of the instruction where the number of bytesmatches the size of the register. These are two or three byteinstructions.Direct AddressingThe least Significant byte of the operand address is containedin the second byte of the instruction and the most significantbyte is assumed to be $00. Direct addressing allows the user toaccess $00 through $FF using two byte instructions and executiontime is reduced by eliminating the additional memory access.In most applications, the 256-byte area is reserved forfrequently referenced data.Extended AddressingThe second and third bytes of the instruction contain the absoluteaddress of the operand. These are three byte instructions.I ndexed AddressingThe unsigned offset contained in the second byte of the instructionis added with carry to the Index Register and used toreference memory without changing the Index Register. Theseare two byte instructions. .Pointer OperationsMnemonicTable 9 Index Register and Stack Manipulation InstructionsImmed Direct Index Extend ImpliedCondo Code Reg.Boolean/Arithmetic Operation 5 4 3 2 1 0OP - # OP - # OP - # OP - # OP - # H I N Z V CCompare Index Reg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 X - M: M+ 1 • • : : t tDecrement Index Reg DEX 09 3 1 X-1-X• • • t • Decrement Stack Pntr DES 34 3 1 SP - 1 - SP • • • • • •Increment Index Reg INX 08 3 1 X+1-X• • • t • Increment Stack Pntr INS 31 3 1 SP + 1- SP • • • • • Load Index Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M- XH. IM+1)- XL • : t R •Load Stack Pntr LOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M-+ SP H • IM+1)-SP L • • : : R •Store Index Reg STX OF 4 2 EF 5 2 FF 5 3 XH - M. XL -+ 1M + 1) • • t t R Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH - M. SPL - 1M + 1) • • t t R •Index Reg - Stack Pntr TXS 35 3 1 X-1-SP• • • • •Stack Pntr - Index Reg TSX 30 3 1 SP+1-X• • • • • Add ABX 3A 3 1 B+X- X• • • • •Push Data PSHX 3C 4 1 XL'" Msp. SP -1- SP • • • • • •XH-+ Msp. SP -1- SPPull Data PULX 38 5 1 SP + 1 - SP. MSp .... XH• • • • • •SP + 1 - SP. MSp .... XLThe Condition Code Register notes are listed after Table 12.~HITACHI 565

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------Implied AddressingThe operand(s) are registers and no memory referenGe is. required. These are single byte instructions.Relative AddressingRelative addressing is used only for branch instructions. Ifthe branch condition is true, the Program Counter is overwrittenwith the sum of a signed single byte displacement in the secondbyte of the instruction and the current Program Counter. Thisprovides a branch range of -126 to 129 bytes from the firstbyte of the instruction. These are two byte instructions.Table 10 Accumulator and Memory InstructionsAccumulator and Immed Direct Index Extend Implied Condo Code Reg.MnemonicMemory OperationsBoolean ExpressionOP - # OP - # OP - # OP - # OP - # H I N Z V CAdd Acmltrs ABA 1B 2 1 A+B~A ~--r- • ~ ~ ~ ~-.-" -- -~. - - ----Add B to X ABX 3A 3 1 B +X~X• • • • • •Add with Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C~A ~ • ~ ~ ~ ~ADCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C~B ~ • ~ ~ t tAdd ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M~A t • t t t tADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M~A t • t t t tAdd Double ADDD C3 4 3 03 5 2 E3 6 2 F3 6 3 D+M:M+1~D • t t t tAnd ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A 'M~A• • t t R •ANDB C4 2 2 04 3 2 E4 4 2 F4 4 3 B· M~B • t t R •Shift Left, Arithmetic ASL 68 6 2 78 6 3 • t t t tASLA 48 2 1 • t t t tASLB 58 2 1--r- • t t t t~-r----t--~- --Shift Left Obi ASLD 05 3 1• t t t tShift Right, Arithmetic ASR 67 6 2 77 6 3 ~ ~ ~ ~ASRA 47 2 1 • t t t tASRB 57 2 1• • t t t tBit Test BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A'M • • t t R •BITB C5 2 2 05 3 2 E5 4 2 F5 4 3 B'M--- • ~r-- --r--t R •Compare Acmltrs CBA 11 2 1 A-B• • t t t tClear CLR 6F 6 2 7F 6 3 OO~M-- --- r-- --• R S R RCLRA 4F 2 1 OO~A• • R S R RCLRB 5F 2 1 OO~B • R S R RCompare CMPA 81 2 2 91 3 2 A1 4 2 B1 4 3 A-M• • t ~ t tCMPB C1 2 2 01 3 2 E1 4 2 F1 4 3 B-M • • ~ t t t---- - 1----1 's Complement COM 63 6 2 73 6 3 ~~M ~ t R S-'--- I-----COMA 43 2 1 A~A• • R S---t--- --t---_.~ ~t t~ t t ~COMB 53 2 1 B~B• • R S-----I---I---t------ --1-----Decimal Adi. A DAA 19 2 1 Adj binary sum to BCD •Decrement DEC 6A 6 2 7A 6 3 M-1 ~M• ~ t t DECA 4A 2 1 A-1 ~A• • t t t •DECB 5A 2 1 B -1 ~B• • t t t •Exclusive OR EORA 88 2 2 98 3 2 A8 4 2 B8 4 3 A\i)M~A• ·t t R •EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 BG'lM~B • • t t R •--1---Increment INC 6C 6 2 7C 6 3 M+ 1 ~M• • t t t •INCA 4C 2 1 A+ 1 ~A• ! t t •INCB 5C 2 1 B+1~B • t t t •Load Acmltrs LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M~A• • t t R •LDAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M~B• ·~ t R •Load Double LDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M:M+1~D• • t t R •Logical Shift, Left LSL 68 6 2 78 6 3• • ~ t t ~LSLA 48 2 1• • t t t tLSLB 58 2 1 • t t t tLSLD 05 3 1• ~ t t tShift Right, Logical LSR 64 6 2 74 6 3• • R ~ t ~LSRA 44 2 1• • A t t tLSRB 54 2 1• • R t ~ tLSRD 04 3 1 • • Rt t t566 ~HITACHI(Continued)

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-1Table 10 Accumulator and Memory Instructions (Continued)Accumulator and Immed Direct Index Extend Implied Condo Code Reg.MnemonicBoolean ExpressionMemory OperationsOP OP OP OPOP - # - # - # - # - # H I N Z V CMultiply MUL 3D 10 1 AXB-+D • • • • • ~2's Complement NEG 60 6 2 70 6 3 OO-M-+M • • ~ ~ ~ ~(Negate)NEGA 40 2 1 OO-A-+A • • f ~ ~ ~NEGB 50 2 1 oo-B-+B • • ~ ~ ~ ~No Operation NOP 01 2 1 PC + 1 -+PC• • • • • •Inclusive OR ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+ M-+A • • ~ ~ R •ORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B+M-+B t ~ R •Push Data PSHA 36 3 1 A -+Stack • PSHB 37 3 1 B -+Stack • • •-~Pull Data PULA 32 4 1 Stack -+A • • •PULB 33 4 1 Stack -+ B • • • • •Rotate Left ROL 69 6 2 79 6 3 ~ ~ ~ ~f-- f---ROLA 49 2 1--- ---- • t ~ ~ ~f-- ----ROLB 59 2 1 • • t ~ ~ ~Rotate Right ROR 66 6 2 76 '6 3 • • ~ ~ ~ ~RORA 46 2 1 • • ~ ~ ~ ~RORB 56 2 1• • ~ ~ ~ ~Subtract Acmltr SBA 10 2 1 A-B-+A • • t ~ ~ ~Subtract with Carry SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C-+A • • ~ ~ ~ ~SBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-+B • • ~ ~ t ~Store Acmltrs STAA 97 3 2 A7 4 2 B7 4 3 A-+M • • t t R •STAB 07 3 2 E7 4 2 F7 4 3 B-+M • • t ~ R •STD DO 4 2 ED 5 2 FD 5 3 D-+M:M+1 • • ~ ~ R •Subtract SUBA 80 2 2 90 3 2 AO 4 2 BO 4 3 A - M-+A • ~ t t ~SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B-M-+B • ~ ~ t tSubtract Double SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 0- M:M + 1-+0----- - --- _~ ~ ~ ~.. - -Transfer Acmltr - - - -TA8 16 2 1 A-+B • t ~ Ac--- ---- -- -•TBA 17 2 1 B-+A • •A •- c-- -- --f---Test, Zero or Minus TST 60 6 2 70 6 3 M -00 • • A RThe Condition Code Aegister notes are listed after Table 12.TSTA 40 2 1 A -00 • • t t A ATSTB 50 2 1 B - 00 • • ~ ~ A A~ tt ~$ HITACHI 567

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------Table 11Jump and Branch InstructionsOperationsMnemonicDirect Relative Index Extend ImpliedOP - # OP - # OP - # OP - # OP - #Branch Always BRA 20 3 2 NoneBranch Never BRN 21 3 2 NoneBranch If Carry Clear BCC 24 3 2 C"OBranch If Carry Set BCS 25 3 2 C=1- Branch If - Zero BEQ 27 3 2 Z .. 1Branch TestBranch If ~ Zero BGE 2C 3 2 N

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-lTable 13 Instruction Execution Times in E·CyclesAddressing ModeTI "iI»"i1oJ~ "'C >ce)( .!! .;:;B I» -aftII)(! 0-g Qjw.§ a::Addressing ModeBftII "iI»~oJ~ "iu C )( :i .~E I! S I» ftII-a)( ~Qj.§ 0 w .: ! a::A8A 2 INX • • 3 A8X • • • • 3 JMP • 3 3 ADC 2 3 4 4 JSR • 5 6 6 ADD 2 3 4 4 LOA 2 3 4 4 ADDD 4 5 6 6 • • LOO 3 4 5 5 • •AND 2 3 4 4 • LOS 3 4 5 5 ASl 6 6 2 LOX 3 4 5 5 • ASlD • • 3 LSL 6 6 2 ASR 6 6 2 • LSLO • • 3 8CC 3 LSR 6 6 2 8CS 3 LSRO 3 8EQ 3 MUL • • 10 8GE 3 NEG 6 6 2 8GT 3 NOP • • • • 2 8HI 3 ORA 2 3 4 4 • 8HS • • • • 3 PSH 3 81T 2 3 4 4 •PSHX 4 8lE 3 PUL 4 8lO 3 PULX • • 5 8lS 3 ROL 6 6 2 8lT 3ROR--1------1------1--6 6 2 8MI 3RTI 10 8NE 3 RTS 5 8PL 3 SBA • • • • 2 BRA 3 SBC 2 3 4 4 • BRN 3 SEC 2 BSR 6 SEI 2 BVC 3 SEV • • • 2 BVS • 3 STA 3 4 4 C8A 2 STO 4 5 5 CLC 2 STS 4 5 5 Cli • • 2 STX • 4 5 5 CLR 6 6 2 SUB 2 3 4 4 ClV • • • • 2 SUBO 4 5 6 6 • CMP 2 3 4 4 • SWI 12 COM • • 6 6 2 TAB 2 CPX 4 5 6 6 • TAP 2 OAA • •2 TBA 2 DEC 6 6 2 TPA • • 2 DES 3 TST 6 6 2 OEX • • • • 3 TSX 3 EOR 2 3 4 4 TXS 3 INC 6 6 • WAI • • • • 9 •INS • • • • 3 •_HITACHI 569

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01MO-l----------------• SUMMARY OF CYCLE BY CYCLE OPERATIONTable 14 provides a detailed description of the informationpresent on the Address Bus, Data Bus, and the Read/Write(R/W) line during each cycle of each instruction.The information is useful in comparing actual with expectedresults during debug to both software and hardware as theprogram is executed. The information is categorized in groupsaccording to addressing mode and number of cycles per instruc-tion. In general, instructions with the same addressing modeand number of cycles execute in the same manner. Exceptionsare indicated in the table.Note that during MeU reads of internal locations, the resultantvalue will not appear on the external Data Bus except inMode O. "High order" byte refers to the most significant byteofa 16-bitvalue.Address Mode &InstructionsTable 14 Cycle by Cycle OperationAddress BusData Bus570IMMEDIATEADC EORADD LOAAND ORABIT SBCCMP SUBLOSLOXLDDCPXSUBDADDDDIRECTADC EORADD LOAAND ORABIT SBCCMP SUBSTALOSLOXLDDSTSSTXSTDCPXSUBDADDDJSR2 123 1234 12343 1233 1234 12344 12345 123455 12345Op Code Address 1 Op CodeOp Code Address + 1 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Operand Data (High Order Byte)Op Code Address + 2 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Operand Data (High Order Byte)Op Code Address + 2 1 Operand Data (Low Order Byte)Address Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of OperandAddress of Operand 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Destination AddressDestination Address 0 Data from AccumulatorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of OperandAddress of Operand 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of OperandAddress of Operand 0 Register Data (High Order Byte)Address of Operand + 1 0 Register Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of OperandOperand Address 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Address Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Irrelevant oltlSubroutine Address 1 First Subroutine Op CodeStack Pointer 0 Return Address (Low Order Byte)Stack Pointer + 1 0 Return Address (High Order Byte)(Continued)$ HITACHI

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1Table 14 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusEXTENDEDJMPADC EORADD LDAAND ORABIT SBCCMP SUBSTALDSLOXLDDSTSSTXSTDASL LSRASR NEGCLR ROLCOM RORDEC TST*INCCPXSUBDADDDJSR3 1234 12344 12345 123455 123456 1234566 1234566 123456Op Code Address 1 Op CodeOp Code Address + 1 1 Jump Address (High Order Byte)Op Code Address + 2 1 Jump Address (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Destination Address (High Order Byte)Op Code Address + 2 1 Destination Address (Low Order Byte)Operand Destination Address 0 Data from AccumulatorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Operand Data (High Order Byte)Address of Operand + 1 1 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 0 Operand Data (High Order Byte)Address of Operand + 1 0 Operand Data (Low Order Byte)Op Code Address 1 Op CodeOp Code Address + 1 1 Address of Operand (High Order Byte)Op Code Address + 2 1 Address of Operand (Low Order Byte)Address of Operand 1 Current Operand DataAddress Bus F F F F 1 Low Byte of Restart VectorAddress of Operand 0 New Operand DataOp Code Address 1 Op CodeOp Code Address + 1 1 Operand Address (High Order Byte)Op Code Address + 2 1 Operand Address (Low Order Byte)Operand Address 1 Operand Data (High Order Byte)Operand Address + 1 1 Operand Data (Low Order Byte)Address Bus F F F F 1 Low Byte of Restart VectorOp Code Address 1 Op CodeOp Code Address + 1 1 Address of Subroutine (High Order Byte)Op Code Address + 2 1 Address of Subroutine (Low Order Byte)Subroutine Starting Address 1 Op Code of Next InstructionStack Pointer 0 R~turn Address (Low Order Byte)Stack Pointer - 1 0 Return Address (High Order Byte)• In the TST ins.ruction, the line condition of the sixth cycle does the following: R/iii = "High", AB = FFFF, DB = Low Byte of Reset Vector.(Continued)$ HITACHI 571

HD68P01V07, HD68P01V07-1,'HD68P01MO, HD68P01M0-1----------------Table 14 Cycle by Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusINDEXEDJMPAOC EORADD LDAAND ORABIT SBCCMP SUBSTALOSlOXlODSTSSTXSTD~SL LSRASR NEGCLR ROlCOM RORDEC TST·INCCPXSUBDADDDJSR344556661 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register Plus Offset 1 Operand Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register Plus Offset 0 Operand Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register Plus Offset 1 Operand Data (High Order Byte)5 Index Register Plus Offset + 1 1 Operand Data (Low Order Byte)1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus FFFF 1 Low Byte of Restart Vector4 Index Register Plus Offset 0 Operand Data (High Order Byte)5 Index Register Plus Offset + 1 0 Operand Data (Low Order Byte)1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register Plus Offset 1 Current Operand Data5 Address Bus F F F F 1 Low Byte of Restart Vector6 Index Register Plus Offset 0 New Operand Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register + Offset 1 Operand Data (High Order Byte)5 Index Register + Offset + 1 1 Operand Data (Low Order Byte)6 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Offset3 Address Bus F F F F 1 Low Byte of Restart Vector4 Index Register + Offset 1 First Subroutine Op Code5 Stack Pointer 0 Return Address (Low Order Byte)6 Stack Pointer - 1 0 Return Address (High Order Byte)• In the TST instruction, the line condition of the sixth cycle does the following: R/W = "High", AB = FFFF, DB = Low Byte of Reset Vector,(Continued)572 $ HITACHI

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1Table 14 Cycle by Cycle Operation (Continued)Address Mode &InstructionsIMPLIEDABA DAA SECASL DEC SEIASR INC SEVCBA LSR TABCLC NEG TAPCLI NOP TBACLR ROL TPACLV ROR TSTCOM SBAABXASLDLSRDDESINSINXDEXPSHAPSHBTSXTXSPULAPULBPSHXPULXRTS233333334455Address BusData Bus1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Previous Register Contents 1 Irrelevant Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Stack Pointer 0 Accumulator Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Stack Pointer 1 Irrelevant Data1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Op Code of Next Instruction3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Operand Data from Stack1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 0 Index Register (Low Order Byte)4 Stack Pointer + 1 0 Index Register (High Order Byte)1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Index Register (High Order Byte)5 Stack Pointer +2 1 Index Register (Low Order Byte)1 Op Code Address 1 OpCode2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Address of Next Instruction(High Order Byte)5 Stack Pointer + 2 1 Address of Next Instruction(Low Order Byte)(Continued)$ HITACHI 573

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------Table 14 Cycle by Cycle Operation (Continued)Address Mode &CycleCyclesAddress BusR/WInstruction # LineData BusWAI** 9 1 Op Code Address 1 OpCode2 Op Code Address + 1 1 Op Code of Next Instruction3 Stack Pointer 0 Return Address (low Order Byte)4 Stack Pointer - 1 0 Return Address (High Order Byte)5 Stack Pointer - 2 0 Index Register (low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 StaLk Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code RegisterMUL 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Address Bus FFFF 1 Low Byte of Restart Vector4 Address Bus FFFF 1 Low Byte of Restart Vector5 Address Bus FFFF 1 Low Byte of Restart Vector6 Address Bus FFFF 1 Low Byte of Restart Vector7 Address Bus FFFF 1 low Byte of Restart Vector8 Address Bus F F F F 1 low Byte of Restart Vector9 Address Bus FFFF 1 low Byte of Restart Vector10 Address Bus FFFF 1 low Byte of Restart VectorRTI 10 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Irrelevant Data3 Stack Pointer 1 Irrelevant Data4 Stack Pointer + 1 1 Contents of Condo Code Reg.from Stack5 Stack Pointer + 2 1 Contents of Accumulator Bfrom Stack6 Stack Pointer + 3 1 Contents of Accumulator Afrom Stack7 Stack Pointer + 4 1 Index Register from Stack(High Order Byte)8 Stack Pointer + 5 1 Index Register from Stack(low Order Byte)9 Stack Pointer + 6 1 Next Instruction Address fromStack (High Order Byte)10 Stack Pointer + 7 1 Next Instruction Address fromStack (low Order Byte)SWI 12 1 Op Code Address 1 Op Code2 Op Code Address + 1 1 .Irrelevant Data3 Stack Pointer 0 Return Address (low Order Byte)4 Stack Pointer - 1 0 Return Address (High Order Byte)5 Stack Pointer - 2 0 Index Register (low Order Byte)6 Stack Pointer - 3 0 Index Register (High Order Byte)7 Stack Pointer - 4 0 Contents of Accumulator A8 Stack Pointer - 5 0 Contents of Accumulator B9 Stack Pointer - 6 0 Contents of Condo Code Register10 Stack Pointer - 7 1 Irrelevant Data11 Vector Address FFFA (Hex) 1 Address of Subroutine(High Order Byte)12 Vector Address FFFB (Hele) 1 Address of Subroutine(low Order Byte)•• While the MCU is in the "Weit" state, its bus state. will appear IS e series of the MCU reid. of an Iddress which il seven locationsless then the original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedanceItete by a WAI instruction.(Continued)574 _HITACHI

----------------HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1Table 14 Cycle by Cycle Operation (Continued)Address Mode &InstructionRELATIVEBee BHT BNEBeS BlE BPLBEQ BLS BRA BRNBGE BLT BVeBGT BMT BVSBSR36Address BusData Bus1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Branch Offset3 Address Bus F F F F 1 Low Byte of Restart Vector1 Op Code Address 1 Op Code2 Op Code Address + 1 1 Branch Offset3 Address Bus FFFF 1 Low Byte of Restart Vector4 Subroutine Starting Address 1 Op Code of Next Instruction5 Stack Pointer 0 Return Address (Low Order Byte)6 Stack Pointer - 1 0 Return Address (High Order Byte)• SUMMARY OF UNDEFINED INSTRUCTIONS OPERA­TIONThe MeU has 36 undefined instructions. When these arecarried out, the contents of Register and Memory in MCUchange at random.When the op codes (4E. SE) are used to execute. the MCUcontinues to increase the program counter and it will not stopuntil the Reset signal enters. These op codes are used to test theLSI.Table 15 Op Codes MapH068P01 MICROCOMPUTER INSTRUCTIONSOP ACC ACC ACCA or SP ACCB or XINO EXTCODE A BIMM 1 DIR liND J EXT IMM T DIR liND 1 EXT0000 0001 0010 0011 0100 0101 0110 0111 1000 11001 11010 [1011 110011101 11110 11111LO 0 1 2 3 4 5 6 7 B J 9 1 A 1 B C I---- ---0 1 E 1 F0000 0SBA BRA TSX NEG SUB0001 1 NOP CBA BRN INS CMP0010 2----- ./ BHI PULA (+1) SBC./ BLS PULB (+11 COM I SUBO (+21· ·: AODO (+210100 4 LSRD (+1) .,./ BCC DES LSR ANDBIT0110 6 TAP TAB BNE PSHA ROR LOA0111 7 TPA TBA BEQ PSHB ASR ~I STA /--I STA1000 8 INX (+1) /----BVC PULX (+21 ASL EOR1001 9 DEX(+1) OAA BVS RTS (+21 ROL ADC1010 A CLV / BPL ABX DEC ORA1011 B SEV ABA BMI RTI (+71 ADD1100 C CLC / BGE PSHX (+11 INC CPX (+21 lDD (+11· ·1101 0 SECV BlT MUL (+7) TST BSR I(+41JSR (+21 ;(+1~ STD (+111110 E Cli ./ BGT WAI (+61 _..- JMP (-31·II LOS (+11·I lOX (+1)1111 F SEa /" BlE SWI (+9) CLR • (+111 STS (+1) • (+1)1 STX (+1)~0011 3---0101 5 ASLO (+11 ./ BCS TXS----BYTE/CYCLE 112 1/2 2/3 113 1/2 1/2 2/6 3/6 2/2 I 2/3 1 2/4 1 3/4 2/2 I 2/3 I 2/4 I 3/4(NOTES) 1. Undefined Op codeS are marked with ~.2. ( I indicate that the number in parenthesis must be added to the cycle count for that instruction.3. The instructions shown below are all 3 bytes and are marked with ......Immediate addressing mode of SUBO, CPX, lOS, AODO, LOO and LOX instructions, and undefined op codes(8F, CO, CFI.4. The Op codes C4E, 5E) are 1 byte/- cycles instructions, and are marked with .......0123456789ABC0EF_HITACHI575

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1-------------------• PRECAUTIONS WHEN EMULATINGTHE HD6801 FAMILYThe H068POI series has 8k-byte EPROM space internally inlocation $EOOO to $FFFF. Note the following when emulatingthe H06801S0 (2k-byte ROM on-chip) and the H06801VO(4k-byte ROM on-chip) with the H068POI series.I) Mode 0, 1, 6Table 16 shows the address which may be used for the internalROM space.(Note 1) In Table 16, the following addresses are external like the ROMon-chip type:$FFFO to $FFFF in Mode 1$FFFE and $FFFF (reset vectorl just after releasing reset inMode 0(Note 2) In Mode 0, data will not appear at Port 3 if accessing theEPROM addresses. It is different from the ROM on-chip type.2) Mode 5, 7Table 18 shows the addresses which may be used for theinternal ROM space without any limitations.Table 16Table 18H06801SOH06801VO'$F800 to $FFFF (2k bytes)$FOOO to $FFFF (4k bytes)HD6801S0H06801VO$F800 to $FFFF (2k bytes)$FOOO to $FFFF (4k bytes)Mode 0, 1 and 6 are expanded modes. When emulating theH06801S0 and the H06801VO, the addresses shown in Table17 should not be used externally be-cause they are the internalspace in the EPROM on the package type. (See Fig. 26)3) Mode 2,3,4In these modes, the internal ROM is disable. The EPROMon the package type may be used equivalently as the ROM onchiptype.Table 17HD6801S0HD6801VO$EOOO to $F7FF (6k bytes)$EOOO to $EFFF (4k bytes)(Example)I ROM On-chip Type II EP ROM on the Package Type IExternalMemory Space$EOOO~----------------I~®4k-Byte EPROM SpaceInternalAddressesFigure 26$FFF}Internal AddressesCorresponding to theROM On-chip TypeMemory Map Example when Emulating the H06801S0with the H068P01MO and the 4k-Byte EPROM576 $ HITACHIFigure 26 shows an address map example when emulating theH06801S0 with the H068POIMO and the 4k·byte EPROM inmode 0, 1 and 6. In the emulation of expanded modes, theaddresses for memories and peripherals may be used externallyin space A, but not in space Band C which are internal addressesin the EPROM on the package type.Figure 27 and 28 show the memory maps when emulatingthe H06801S0 and HD6801VO with the EPROM on the packagetype and the EPROM.

-----------------H068P01V07, H068P01V07-1, H068P01MO, H068P01M0-1EPROM on the Package TypeHD68P01 V07/-1HD68P01MO/-1EPROMHN482732AHN482732AHN482764Memory Map,------, IExternalAddressi @ :~ _____ ~ UnusableIWWi~I."W!1AddressMCU EPROMAddress Address!~$EOOO@MCU EPROMAddress Address$Elaa~@MCU EPROMAddress Address1 ®~$EOIOO):~"i $0000$FOIQOrTITTl $000InternalROM Address$17FF$1800$FFFFigure 27 Memory Map When Emulating the HD6801S0EPROM on the Package TypeHD68P01V07/-1HD68P01MO/-1EPROMHN482732AHN482732AHN482764Memory Maplir------ ...@ :L __ -- _ . .JExternalAddressUnusable1"::::::::::::"::1 AddressHH©HTMCU EPROMAddress Address~~$EOOO@MCU EPROMAddress Address~[!J$EOOO,@MCUAddressEPROMAddress~ ® ~$EOOO$FOOO $000$FOOO ~~ ~~EFFF$FOOO$OFFF$1000InternalROM Address~~~~$FFFF ~ $FFF$FFFF~i ~~ $FFF$lFFFFigure 28 Memory Map When Emulating the HD6801VO~HITACHI 577

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1----------------• PRECAUTION TO USE EPROM ON THE PACKAGE 8-BITSINGLE-CHIP MICROCOMPUTERAs this microcomputer takes a special packaging type withpin sockets on its surface, pay attention to the followings;(l) Do not apply higher electro-static voltage or serge voltageetc. than maximum rating, or it may cause permanentdamage to the device.(2) There are 28 pin sockets on its surface. When using 32kLet the index·side four pins open.When uSing 24 pin EPROM, matchits index and insert it into lower24 pin sockets.EPROM (24 pins), let the index-side four pins open.(3) When assembling this LSI into user's system products aswell as the mask ROM type 8-bit single-chip microcomputer,pay atte~tion to the followings to keep the good ohmiccontact between EPROM pins and pin sockets ..(a). When soldering on a printed circuit board, etc., keep itscondition under 250°C within 10 seconds. Over-time/temperature may cause the bonding solder of socketpins to meet and the sockets may drop.(b) Keep out detergent or coater from the pin sockets ataft-solder flux removal or board coating. The flux orcoater may make pin socket contactivity worse.(c) Avoid the permanent use of this LSI under the evervibratoryplace and system.(d) Repeating insertion/removal of EPROMs may damagethe contactivity of the pin sockets, so it is recommendedto assemble new ones to your system products.(4) In order to perform the normal operation at 1.25 MHz, itis recommended to use the EPROM whose access time isless than 300 ns.Ask our sales agent about anything unclear.578 ~HITACHI

HD68P05V07------------­MCU (Microcomputer Unit)The HD68POSV is the 8-bit Microcomputer Unit (MCU)which contains a CPU, on-chip clock, RAM, I/O and timer. It isdesigned for the user who needs an economical microcomputerwith the proven capabilities of the HD6800-based instructionset. Setting EPROM on the package, this MCU has the equivalentfunction as the HD680SU and HD680SV. HD68POSV07uses HN482732A as EPROM. The following are some of the h­ardware and software highlights of the MCU.• HARDWARE FEATURES• 8-Bit Architecture• 96 Bytes of RAM• Memory Mapped I/O• Internal 8-Bit Timer with 7-Bit Prescaler• Vectored Interrupts - External, Timer and Software• 24 I/O Ports + 8 Input Port(8 Lines Directly Drive LEOs; 7 Bits Comparator Inputs)• On-Chip Clock Circuit• Master Reset• Complete Development System Support by Evaluation Kit• 5 Vdc Single Supply• SOFTWARE FEATURES• Similar to HD6800• Byte Efficient Instruction Set• Easy to Program• True Bit Manipulation• Bit Test and Branch Instructions• Versatile Interrupt Handing• Powerful Indexed Addressing for Tables• Full Set of Conditional Branches• Memory Usable as Registers/Flags• Single Instruction Memory Examine/Change• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM. RAM and I/O• Compatible Instruction Set with HD6805Note) EPROM is not'attached to the MCU.HD68P05V07• PIN ARRANGEMENT04 20(DC-40P)HD68P05V07o Vee Vee 0ONe Vee 0o ADR7 Vee 0OADRe ADRa 0o ADR5 ADR90OADR4 ADRll0OADR3 VssOOADR2 ADR'00OADRI CEOOADRo 07 0000 Oe 000, 05 0002 04 0OVss 03 0(Top View)~HITACHI 579

HD68P05V07-------------------------------------------------------------• BLOCK DIAGRAMRESNUM INTTIMERPort BI/O LinesA,PortAI/O LinesPort ARegDataInput LinesDataInputBuff"DataDirRegAccumulator8A8'S8IndexRegisterXConditionCodeRegister CCStackPointerSPProgramCounter"High" PCHProgramCounter"Low" PCLCPUCPU ControlDataDirRegPort BRegData Port CALU Dir RegRegPort CI/O LinesPort 0Input LinesAddressOutput LinesADR.ADR,ADR._ADR,ADR.ADR,ADR,ADR,AddressOutput~--~----------------~BufferAddressOutput LinesADA.ADR,ADR ••ADR ..CEAddressOutputBuffer580* HITACHI

---------------------------------------------------------------HD68P05V07• ABSOLUTE MAXIMUM RATINGSItem i Symbol ValueSUPPlY Voltage Vee * -0.3 - +7.0- .Input Voltage (EXCEPT TIMER)-0.3 - +7.0--- Vin*Input Voltage (TIMER) -0.3- +12.0----- -Operating Temperature T opr o -+70Storage Temperature T stg - 55 - +150UnitVVV°c°c• With respect to Vss (SYSTEM GND)(NOTE)Permanent LSI damage may occur if maximum rating~ are exceeded. Normal operation should be underrecommen'ded operating conditions. If these conditions are exceeded, it could affect reliability of LSI.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (VCC=5.25V ± 0.5V, VSS=GND, Ta=O-+70°C, unless otherwise noted.)Item Symbol Test Condition min typRES4.0 -.-Input "High" Voltage INT V ,H I3.0 -IAll Other2.0 -RES -0.3 -INT -0.3 -Input "Low" VoltageV ,LXTAL (Crystal Mode)-0.3 -All Other -0.3 -Power Dissipation Po - -Low Voltage Recover LVR - ---TIMER -20 -Input Leak Current INT I'L V in =0.4 V-Vee -50 -XTAL (Crystal Mode) -1200 -max UnitVee VVee VVee V0.8 V0.8 V0.6 V0.8 V700 mW4.75 V20 J.l.A50 J.l.A0 J.l.A• AC CHARACTERISTICS (VCC=5.25V ± O.5V, Vss=GND, Ta=O-+70°C, unless otherwise noted.)Item Symbol Test Condition min typClock Frequency fel 0.4 -Cycle Timetcyc~ .1.0 -INT Pulse WidthRES Pulse WidthTIMER Pulse Widtht ,WLtRWLt TWLtcyC +250-tcyC + -250tcyC + -250Oscillation Start-up Time (Crystal Mode)toscCL =22pF±20%,Rs=60n max.- -Delay Time Reset tRHL External Cap. = 2.2 J.l.F 100 -Input Capacitance I EXTAL - -I All OtherCinVin=OV- -max Unit4.0 MHz10 J.l.S- ns- ns- ns100 ms- ms35 pF12.5 pF$ HITACHI581

HD68P05V07--------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ± 0.5V, Vss = GNO, Ta = 0 "" +70°C, unless otherwise noted.)ItemOutput "High" VoltageOutput "Low" VoltageInput "High" VoltageInput "Low" VoltageInput Leak CurrentInput "High" VoltageInput "Low" VoltageThreshold Voltage..* Port 0 as digital mput** Port 0 as analog inputPort APort BPort CPort A and CPort BPort A, B, C,and 0*Port APort B, C,and 0Port 0**(Do"" 0 6 )Port 0**(Do"" 0 6 )Port 0**(0 7 )SymbolVOHVOLVIH1---VILIlLVIH----VilVTHTest Condition min typIOH = -10 lolA 3.5 -~9H = -100 lolA 2.4 -IOH = -200 lolA 2.4 -IOH = -1 mA 1.5 -IOH = -100 lolA 2.4 -~_=1.6mA - -~,,:,3.2mA - IOL = 10mA - -2.0 --0.3 -Yin = O.SV -500--Ȳin = 2V -300 -Yin = 0.4V "" Vee - 20 ----------.------i------.=---r----------+---i--VTH+0.2VTH-O.2i --maxUnit- V- V- V- V- V0.4 V0.4 V1.0 VVeeV0.8 V- lolA- lolA20 lolA-- V- VO.BxVeeVTest PointTTL Equiv. (Port B) TTL Equiv. (Port A and C)Vee1.2knIi = 3.2 mAIi = 1.6 mATest PointVee2.4kHVi40pF12 knVi30 pF 24 kH(NOTE)1. Load capacitance includes the floating capacitance of the probe and the jig etc.2. All diodes are 1S2074 ®or equivalent.• SIGNAL DESCRIPTIONThe input ilOd output signals for the MCV, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee and VssPower is supplied to the MCV using these two pins. Veeis +5.2SV ±O.5V. VSS is the ground connection.• INTThis pin provides the capability for asynchronously applyingan external interrupt to the MCV. Refer to INTERRUPTSfor additional information.• XTAL and EXTALThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4 MHz maximum) can be.connected to thesepins to provide a system clock with various stability. Refer toINTERNAL OSCILLATOR for recommendations about theseFigure 1 Bus Timing Test Loadsinputs.582 ~HITACHI• TIMERThis pin allows an external input to be used to decrementthe internal timer circuitry. Refer to TIMER for additionalinformation about the timer circuitry.• RESThis pin allows resetting of the MeV. Refer to RESETSfor additional information.• NUMThis pin is not for user application and should be connectedto VSS.

-------------------------------------------------------------HD68P05V07• InpUt/Output Lines (Ao '" A, • Bo '" B,. Co '" C,)These 24 lines are arranged into three 8-bit ports (A, BandC). All lines are programmable as either inputs or outputs undersoftware con trol of the Data Direction Register (DDR). Refer toINPUT/OUTPUT for additional information.• Input Lines (Do '" 0,)These are 8-bit input lines, which has two functions. Firstly.these are TTL compatible inputs, in location $003. The otherfunction of them is 7 bits comparator in location $007. Refer toINPUT for more detail.• REGISTERSThe MCU has five registers available to the programmer.They are shown in Figure 2 and are explained in the followingparagraphs.11L.... ______A. I Accumulator°L-. _____---.l 1Index Register°P_c ____ ~1 Program Counter11 5 4 °LI °..,JII...°..,JII...°..,JI ... °....L.,I °..,JI,--' .... 1 _'....1 __ s_p_---II Stack PointerFigure 2I N Z C Condition Code Register~_L ------------ Negative--- Carry/Borrow-- Zero------~- Interrupt Mask--~-- - ~-- Halt CarryProgramming Model• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datamanipulations.• Index Register (X)The index register is an 8-bit register used for the indexedaddressing mode. It contains an 8-bit address that may be addedto an offset value to create an effective address. The indexregister can also be used for limited calculations and datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is a 13-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 13-bit register that contains the addressof the next free location on the stack. Initially, the stack pointeris set to location $007F and is decremented as data is beingpushed onto the stack and incremented as data is being pulledfrom the stack. The six most significant bits of the stack pointerare permanently set to 00000011. During an MCU reset or thereset stack pointer (RSP) instruction, the stack pointer is setto location $007F. Subroutines and interrupts may be nesteddown to location $0061 which allows the programmer to use upto 15 levels of subroutine calls .• Condition Code Register (CC)The condition code register is a S-bit register in which eachbit is used to indicate or flag the rl?sults of the instruction justexecuted. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained in the followingparagraphs.Half Carry (H)Used during arithmetic operations (ADD and ADC) toindicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask the timer and external interrupt (INT)­If an interrupt occurs while this bit is set it is latched and will beprocessed as soon as the interrupt bit is reset.Negative (N)Used to indicate that the result of the last arithmetic, logicalor data manipulation was negative (bit 7 in result equal to alogical one).Zero (ZIUsed to indicate that the result of the last arithmetic, logicalor data manipulation was zero.Carry/Borrow (C)Used to indicate that a carry or borrow out of the arithmeticlogic unit (ALU) occurred during the last arithmetic operation.This bit is also affected dunng bit test and branch instructions,shifts. and rotates.• TIMERThe MCU timer circuitry is shown in Figure 3. The 8-bitcounter, the Timer Data Register (TDR), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the timer reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register (TCR) isset. The MeU responds to this interrpt by saving the presentCPU state on the stack, fetching the timer interrupt vector fromlocations $OFF8 and $OFF9 and executing the interrupt routine.The timer interrupt can be masked by setting the timerTIMER Input PinTCR bit 4tPl (Internal) ----'"""-......TCR bit 5Clock InputMultiplexTimer Control Register(TCR)b" } Prescalerb, Address Bitsb,8-bit CounterTimer Data Register (TOR)b,b.Timer Interrupt Req.Timer Interrupt MaskFigure 3b, } Clock Inputb.Source OptionTimer Block Diagram$ HITACHI 583

HD68P05V07----------------------------------------------~-------------interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) inthe Condition Code Register also prevents a timer interruptfrom being processed.The clock input to the timer can be from an external sourceapplied to the TIMER input pin or it can be the internal CP2signal. When the 1/>2 signal is used as the source, it can be gatedby an input applied to the TIMER input pin allowing theuser to easily perform pulse-width measurements. A prescaleroption can be applied to the clock input that extends the timingin terval up to a maximum of 128 counts before decrementingthe counter (TOR). The timer continues to count past zero,falling through to $FF from zero and then continuing thecount. Thus, the counter (TOR) can be read at any time byreading the TOR. This allows a program to determine the lengthof time since a time interrupt has occurred and not disturbthe counting process.The TOR is 8-bit read/write register in location $008. Atpower-up or reset, the TOR and the prescaler are initialize withall logical ones.The timer interrupt request bit (bit 7 of the TCR) is set byhardware when timer count reaches zero, and is cleared by programor by hardware reset. The bit 6 of the TCR is writable byprogram. Both of those bits can be read by MPU.The bit 5 and bit 4 of the TCR select a clock input source.The selections are shown in Table 1. Bit 3 is not used. Bit 2, bit1 and bit 0 are used to select the prescaler dividing ratio, shownin Table 2. At reset, an internal clock by the TIMER input pinis selected as clock source and "+ 1 mode" is selected as theprescaler dividing ratio.(NOTE) If the MCV Timer is not used, the TIMER input pinmust be grounded.• RESETSThe MCV can be reset two ways; by initial power-up andby the external reset input (RES), see Figure 4. All the I/Oports are initialized to input mode (DDRs are cleared) duringreset..Ouring power-up, a minimum 100 milliseconds is neededbefore allowing the IrnS input to go "High".This time allows the internal crystal oscillator to stabilize.Connecting a capacitor to the RES input, as shown in Figure5, typically provides sufficient delay.RES Pin --------¥Internal Reset - _________ -1Figure 4 Power and ~ TimingPart ofHD68P05VMCU2Table 1 Selection of Clock Input SourceTimer ControlRegister (TCR)Bit 5 Bit 4Clock Input Source0 a===----0 1 CP2 (Internal Clock) (Note 2)1 a----Figure 5 Power Up Reset Delay Circuit• INTERNAL OSCILLATORThe internal oscillator circuit is designed to require a minimumof external components. The use of a crystal (AT cut,4 MHz max) is sufficient to drive the internal oscillator withvarious stability. The different connection methods are shownin Figure 6. Crystal specifications are given in Figure 7.1 1 TIMER Input Pin(NOTE) 1. 0.0 and 1.0 are not usable In mask option of 68052. The TIMER input pin must be tied to Vee. foruncontrolled ¢. clock.Table 2 Selection of Prescaler Dividing RatioTimer ControlRegister (TCR)Bit 2 Bit 1 Bit 0Prescaler Dividing Ratio0 a a Prescaler + 10 a 1 Prescaler .;- 20 1 a Prescaler .;- 40 1 1 Prescaler .;- 81 a a Prescaler .;- 161 a 1 Prescaler .;- 321 1 a Prescaler .;- 641 1 1 Prescaler .;- 128584 ~HITACHI4~a~Z c::J22PF!20%TExternalClockInputFigure 66 XTAL5 EXTAL HD68POSVMCU6 XTALCrystal5 EXTAL HD68POSVMCUExternal ClockInternal Oscillator

--------------------------------------------------------------HD68P05V07C,XTAL~~EXTAL6 ~~ 5AT - Cut Parallel Resonance CrystalCo ; 7 pF max.f; 4 MHzRs = 60n max.Figure 7 Crystal Parameters• INTERRUPTSThe MCU can be interrupted three different ways: throughthe external interrupt (lNT) input pin, the internal timer interruptrequest, and a software interrupt instruction (SWI). Whenany interrupt occurs, processing is suspended, the present CPUstate is pushed onto the stack in the order shown in Fig. 8, theinterrupt bit (I) in the Condition Code Register is set, the addressof the interrupt routine is obtained from the appropriateinterrupt vector address, and the interrupt routine is executed.Since the stack pointer decrements during pushes, the low orderbyte (PCL) of the program counter is stacked first; then thehigh order five bits (pCH) are stacked. This ensures that the programcounter is loaded correctly as the stack pointer incrementswhen it pulls data from the stack. A subroutine call will canseonly the pr9gram counter (pCH, PCL) contents to be pushedonto the stack. This interrupt bit (I) in the condition code registeris set, the address of the interrupt routine is obtained fromthe appropriate interrupt vector addrdss, and the interrupt routineis executed. The interrupt service routines normally endwith a return from interrupt (RTI) instruction which allows theMCU to resume processing of the program prior to the interrupt.Table 3 provides a listing of the interrupts, their -priority, andthe vector address that contain the starting address of theappropriate interrupt routine.A flowchart of the interrupt processing sequence is givenin Fig. 9.6 5 4 3 2 0 PullPushn-4 1 111ConditionCode Registern+1n-3 Accumulator n+2n-2 Index Register n+3n-1 1 1 111PCW n+4PCL' n+5• For subroutine calls. only PCH and PCL are stacked.Figure 8 Interrupt Stacking OrderTable 3 Interrupt PrioritiesInterrupt Priority Vector AddressRES 1 $OFFE and $OFFFSWI 2 $OFFC and $OFFDINT 3 $OFFA and $OFFBTIMER 4 $OFF8 and $OFF91-17F -sPO ... OOR·sCLR tNT LogicFF ... Timer7F ... Prescater7F ... TCRFigure 9 Interrupt Processing Flowchart* HITACHI585

HD68P05V07--------------------------------------------------------------• INPUT/OUTPUTThere are 24 input/output pins. All pins are programmableas either inputs or outputs under software control of the correspondingData Direction Register (DDR). When programmedas outputs, the latched output data is readable as input data,regardless of the logic levels at the output pin due to outputloading (see Fig. 10). When Port B is programmed for outputs,it is capable of sinking lOrnA on each pin (VOL = IV max).All input/output lines are TTL compatible as both inputs andoutputs. Port A is CMOS compatible as outputs, and Port BandC are CMOS compatible as inputs. Figure 11 provides someexamples of port connections.DataDirection Output Output Input toRegister Data Bit State MCUBit1 0 0 01 1 1 10 ,. 3·State PinFigure 10 Typical Port 1/0 CircuitryPort AA. B.· ';fT~L ImA LoadA, ·Port BB,Port A Programmed as output!s), driving CMOS and TTL Load directly.la)+VPort B Programmed as output!s), driving Darlington base directly.Ib)+VPort B.B,R10 -mA maxPort Cc.· c,RCMOS InverterPort B Programmed as output!s), driving LED!s) directly'.Port C Programmed as output Is), driving CMOS loads, using externalIc) pull·up resistors. Id)Figure 11 Typical Port Connections• INPUTthe example when Vm is set to 3.5V .Port D can be used as either 8 TTL compatible inputs or 1 • BIT MANIPULATIONthreshold input and 7 analog inputs pins. Fig. 12 (a) shows the The MCU has the ability to set or clear any single randomconstruction of port D. The Port D register at location $003 access memory or input/output bit (except the data directionstores TTL compatible inputs, and those in location $007 store registers) with a single instruction (BSET, BCLR). Any bit inthe result of comparisol} Do to D6 inputs with D7 threshold the page zero read only memory can be tested, using the BRSETinput. Port D has not only the conventional function as inputs and BRCLR instructions, and the program branches as a resultbut also voltage-comparison function. Applying the latter, can of its state. This capability to work with any bit in RAM, ROMeasily check that 7 analog input electriC potential max. exceeds or I/O allows the user to have individual flags in RAM or tothe limit with the construction shown in Fig. 12 (b). Also, using handle single I/O bits as control lines. The example in Figure 13one output pin of MCU, after external capacity is discharged illustrates the usefulness of the bit manipulation and testat the preset state, charge the CR circuit of long enough time instructions. Assume that bit 0 of port A is connecte"d to a zeroconstant, apply the charging curve to the D7 pin. The construc- crossing detector circuit and that bit 1 of port A is connected totion described above is shown in Fig. 12 (c). The compared the trigger of a TRIAC which power the controlled hardware.result of Do to D6 is regularly monitored, which gives the This program, which uses only seven ROM locations, .p.roanaloginput electric potential applied to Do to D6 pins from vides turn-on of the TRIAC within 14 microseconds of the zeroinverted time. This method enables 7 inputs to be converted orossing. The timer could also be incorporated to provide turnfromanalog to digital. Furthermore, combination of two func- on at some later time which would permit pulse-width modUlationsgives 3 level voltages from Do to D6. Fig. 12 (d) provides tion of the controlled power.586 $ HITACHI

_____ 00--------------------------------------------------------------HD68P05V07Internal BusIBitO - BitS)$003 ReadInternal BusIBit 7)$003 Readla) The logic configuration of Port 0Input Port (07)r---PortCCo0 7Reference LevelD.Analog Input S0, _________ o __________ ---lPort0)PortoD.~-=---Analoq Input 6DoAnalog Input 0Do1---=--- Analog Input 0Ib) Seven analog inputs and a reference level input of Port 0Ic) Application to A/D·convertor0 7VTH I; 3.5V)Port0D.~3 Levels Input SInput 1$003) 1$007)VoltageOV - O.8V 0 02.0V - 3.3V 1 0- - ---------~ --"-- ----~----3.7V - Vee 1 1Do3 Levels Input 0Id) Application to 3 levels inputFigure 12 Configuration and Appl ication of Port 0~HITACHI 587

HD68P05V07--------------------------------------------------------------SELF 1 BRCLR 0, · PORT A, SELF 1BSET 1, PORT ABCLR 1, PORT AFigure 13 Bit Manipulation · Example• ADDRESSING MODESThe MCV has ten addressing modes available for use by theprogrammer. They are explained and illustrated briefly in thefollowing paragraphs.• ImmediateRefer to Figure 14. The'immediate addressing mode acce§sesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 15. In direct addressing. the address of theoperand is contained in the second byte of the instruction,Direct addressing allows the user to directly address the lowest256 bytes in memory. All RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage of thisefficient memory addressing mode.• ExtendedRefer to Figure 16. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instruc·tions are three bytes long.• RelativeRefer to Figure 17. The relative addressing mode applies onlyto the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA=(pC)+2+Rel. ReI is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken Rel=O, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 of the present instruction, Theseinstructions are two bytes long.• Indexed (No Offset)Refer to Figure 18. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and'their EA is the contents of the index register.• Indexed (8-bit Offset)Refer to Figure 19. The EA is calculated by adding thecontents of the byte f'Ollowing the opcode to the contents ofthe index register. In this mode, 5 II low memory locations areaccessable. These instructions occupy two bytes.'• Indexed (16-bit Offset)Refer to Figure 20. This addressing mode calculates the EAby adding the contents of the two bytes following the opcodeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode are threebytes long.• Bit Set/ClearRefer to Figure 21. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 22. This mode of addressing applies toinstructions which can test any bit in the first 256 locations($OO-$FF) and branch to any location relative to the PC. Thebyte to be tested is addressed by the byte following the opcode.The individual bit within that byte to be tested is addressed bythe lower three bits of the opcode. The third byte is the relativeaddress to be added to the program counter if the branch conditionis met. These instructions are three bytes long. The value ofthe bit tested is written to the carry bit in the condition coderegister.• ImpliedRefer to Figure 23. The implied mode of addressing has noEA. All the information necessary io execute an instruction iscontained in the opcode. Direct operations on the accumulatorand the index register are included in this mode of addressing.In addition, control instructions such as SWI, RTI belong to thisgroup. All implied addressing instructions are one byte long.• INSTRUCTION SETThe MCU has a set of S9 basic instructions. They can bedivided into five different types: register/memory, read/modify/write, branch, bit manipulation, and control. The followingparagraphs briefly explain each type. All the instructions withina given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operand iseither the accumulator or the index register. The other operandis obtained from memory using one of the addressing modes.The jump unconditional (JMP) and jump to subroutine (JSR)instructions have no register operand. Refer to Table 4.• Read/ModifylWrite InstructionsThese instructions read a memory location or a register,modify or test its contents, and write the modified value backto memory or to the register. The test for negative or zero(TST) instruction is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to TableS.'. Branch InstructionsThe branch instructions cause a branch from the programwhen a certain condition is met. Refer to Table 6.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 256 bytesof the memory. One group either sets or clears. The other groupperforms the bit test and branch operations. Refer to Table 7.• Control InstructionsThe control instructions control the MCU operations duringprogram execution. Refer to Table 8.• Alphabetical ListingThe complete instruction set is given in alphabetical order inTable 9,• Opcode MapTable \0 is an opcode map for the instructions used on theMCU.588 ~HITACHI

______________________________________________________________ HD68P05V07MemoryI~IPROG LOA #$F8 05BE A6I------....f05BF F8IIStack PointProg Count05COCC§IIIIIFigure 14Immediate Addressing ExampleCATFCB32OO4B,II,IItMemory20iII,,I/1 EA004B1Adder'"oiIA20IPROG LOA CAT 0520 B6052E4BIIIndex RegI IIStack PointI IIProg Count052FICC~•IIIFigure 15 Direct Addressing Example~HITACHI589

HD68P05V07------------------------------------------------------------~lEAMemory0000PROG LOA CATA40Index RegStack PointCAT FeB 64Prog Count040CCCFigure 16 Extended Addressing ExampleI,MemoryI~IIPROG BEQ PROG2 04A 7 271-------104A8 18I0000AStack PointIndex Reg§I , I,Figure 17 Relative Addressing Example590 $ HITACHI

----------------------------------------------------------HD68P05V07Memory•II..IIATABLFCC I Lli OOB84C494CIndex RegB8Stack PointPROG LOA XProg Count05F5CCFigure 18 Indexed (No Offset) Addressing Example~MemoryTABL FCB .. BF 0089 BFPROGFCB #86 008A 86t------~FCB '" DB 008B DBFCB .. CF 008C t----C-F--~~~--~----~--~LOATAB LX:;:: I : I--I---.JI~I,IACFIndex Reg03Stack POintProg Count0750CCFigure 19 Indexed (8-Bit Offset) Addressing Example~HITACHI591

HD68P05V07-------------------------------------------------------------PROG§IMemoryILOATA'LX_2~0693 070694 7EIiIIIADBIndex Reg02Stack PointProg Count0695CCTABl FCB #BF 077E BFFCB #86 077F 86FCB #DB 0780 DBFCB #CF 0781 CFFigure 20 Indexed (16-Bit Offset) Addressing ExampleMemoryPORTB EQU 0001 BFI0000A..... ------40590 01PROG BelR 6. PORT B 058F 10I~IIIIfIndex RegStack PointProg Count0591CCFigure 21Bit Set/Clear Addressing Example592~HITACHI

-------------------------------------------------------------HD68P05V07PORT C eau 2 0002 FO AIndex RegStack PointPROG BRCLR 2. PORT C. PROG 2 0574 05 Prog Countt-------40575 02 000005940576 10 CCIII~I L-_________________________ ~,Figure 22 Bit Test and Branch Addressing ExampleI,IIMemorvI~AE5Index RegPROGTAXIIO~A~IIProg CountE5IIII0588cc§II•Figure 23 Implied Addressing Example~HITACHI593

HD68P05V07-----------------------------------------------------------Table 4 Register/Memory Instructions~--Function Mnemonic Immediate Direct ExtendedAddressing ModesIndexed Inde-xed Indexed(No Offset) (8-Bit Offset) (16-Bit Offset)Op # # Op # # Op # # OP # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesLoad A from Memory LOA A6 2 2 B6 2 4 C6 3_ 5 F6 1 4 E6 2 5 06 3 6Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6Store A in Memory STA - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7!------ -- ----- --- .-.. 1------ --- --I-Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6Add Memory andAOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6Carry to A---Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6---Subtract Memory fromSBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6A with Borrow/--AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6----r--OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6f--1-----Exclusive OR MemoryECR AB 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6with AArithmetic Compare Awith MemoryArithmetic Compare Xwith MemoryBit Test Memory with A(Logical Compare)CMP Al 2 2 Bl 2 4 Cl 3CPX A3 2 2 B3 2 4 C3 3BIT A5 2 2 B5 2 4 C5 35 Fl 1 4 El 2 5 01 3 65 F3 1 4 E3 2 5 03 3 65 F5 1 4 E5 2 5 05 3 6Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5Jumllto Subroutine JSR - - - SO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9Table 5 Read/ModifylWrite InstructionsAddressing Modes1--- -----------·--r- --------.-.--~IndexedIndexedFunction Mnemonic Implied (A) Implied (X) Direct(No Offset) (8·Bit Offset)f----Op # # Op # # Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIncrement INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7Clear ClR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7Negate(2's Complement)NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7Rotate left Thru Carry ROl 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7logical Shift Left lSl 48 1 4 58 1 4 38 2 6 78 1 6 66 2 7logical Shift Right lSR 44 1 4 54 1 4 34 2 6 74 1 6 fM 2 7Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 87 2 7Arithmetic Shift left ASl 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7Test for Negative orZeroTST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7594 ~HITACHI

---------------------------------------------------------------HD68P05V07Table 6 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch I F Higher BHI 22 2 4Branch I F Lower or Same BLS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch IF Lower) (BLO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch I F Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch I F Plus BPL 2A 2 4Branch IF Minus BMI 2B 2 4Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4Branch I F Interrupt Mask Bit is Set BMS 20 2 4Branch I F Interrupt Line is Low BIL 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AD 2 8Table 7 Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set B RSET n (n=O ..... 7) - - - 2·n 3 10Branch I F Bit n is clear BRCLR n (n=O ..... 7) - - - 01+2·n 3 10Set Bit n BSET n (n=O ..... 7) 10+2·n 2 7 - - -Clear bit n BCLR n (n=O ..... 7) 11+2·n 2 7 - - -FunctionTable 8 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 1 2Clear Carry Bit CLC 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2$ HITACHI 595

HD68P05V07-------------------------------------------------------------Table 9 Instruction SetAddressing ModesCondition CodeMnemonicIndexedBit BitImme- Ex- Re-Indexed IndexedImpliedDirect(No~t/ Test & H I N Zdiatetended lative(8 Bits) (16 Bits)COffset) Clear BranchADC x x x x x x 1\ 1\ 1\ 1\ADD x )( x x x x 1\ • 1\ 1\ 1\AND x )( x x x x 1\ 1\ •ASL x x x x 1\ 1\ /\ASR x x x x /\ 1\ /\BCC x BCLR x BCS x BEQ x BHCC x BHCS BHI :i BHS x -.-~BIH x------- ------- r-------- ---- -------- ----- --- f---- --• • • • •Bil x----- --- --- -----r--------- --BIT x x x x x x 1\1/\ • !.J..!- I.BlO x- f------BlS x• • • • •--r--BMC x• • • • •BMI x-- --t---------r----r-iI. • • • •-------------- ----- -.--- --------BMS x-BNE x--t------- • • • • •BPlx--r------I-- BRA x----- -----BRN x •BRClR I x-----t------+----/\x • • • • /\BRSH_B.§_~ ___t--- - --r~-l-=x----- -- x----- ------- -------------r-------1--BSET --- •------ - -~ -- -------t"CLC x • 0CLI x 0 • • CLR x x x x----0 1 •CMP x x x x x x 1\ 1\ /\COM x x x x 1\ 1\ 1CPX x x x x x x 1\ 1\ /\DEC x x x x 1\ 1\ EOR x x x x x x----1\ 1\ INC x x x x 1\ 1\ JMP x x x x x JSR x x x x x • • LOA x x x x x x 1\ 1\ LOX x x x x x x • • 1\ 1\ •---------- ---- . ------- - ----------- - -----f---Condition Code Symbols;H Half Carry (From Bit 31 C Carry BorrowI Interrupt Mask 1\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bitl • Not AffectedZ Zero596 $ HITACHI(to be continued)

--------------------------------------------------------------HD68P05V07MnemonicImpliedAddressing ModesImme- Ex- Re-Directdiatetended lativeTable 9 Instruction SetCondition CodeIndexed Bit Bit(No Indexed Indexed(8 Bits) (16 Bits)Setl Test & H I N Z COffset) Clear BranchLSL x x x x I\. I\. I\.LSR x x x x 0 I\. I\.-NEG x x x x I\. I\. I\.NOP x • • ORA x x x x x x I\. I\. --f----•ROL x x x x I\. I\. I\.~- t--~--1-------f--ROR x x x x I\. I\. I\.RSP x • • • • •RTI x ? ? ? ? ?RTS x • • •SBC x x x x X x I\. I\. I\.SEC x • 1SEI x 1 • • STA x x x x x I\. I\. STX x x x x x I\. I\. •SUB x x x X x x • I\. 1\ I\.SWI x 1 TAX x- • • ~-~-t---.TST x x x x I\. I\. TXA x • • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry IBorrowI Interrupt Mask I\. Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From Stack~HITACHI 597

HD68P05V07------------------------------------------------------------Table 10Opcode MapBit Manipulation Branch Read/Modify/Write Control Register/MemoryTest &BranchSet/ClearRei DIR'I A I X I ,X1 I ,XO IMP IMP IMM I DIR L EXT I X2 I X 10 1 2 3 I 4 I 5 I 6 I 7 8 9 A I B I C I 0 I E0 BRSETO BSETO BRA NEG RTI· - SUB1 BRCLRO BCLRO BRN - RTS· - CMP2 BRSET1 BSET1 BHI - - - SBC3 BRCLR1 BCLR1 BLS COM SWI· - CPX4 BRSET2 BSET2 BCC LSR - - AND5 BRCLR2 BCLR2 BCS - - - BIT6 BRSET3 BSET3 BNE ROA - - LOA7 BRCLR3 BCLA3 BEQ ASR - TAX - I STA(+1)8 BRSET4 BSET4 BHCC LSL/ASL - CLC EOR9 BRCLR4 BCLR4 BHCS ROL - SEC ADCA BRSET5 BSET5 BPL DEC - Cli OAAB BRCLR5 ~CLR5 BMI - - SEI ADDC BRSET6 BSET6, BMC INC - ASP - I JMP(-ll0 BRCLR6 BCLR6 BMS TST - NOP BSR·I JSR(-3)E BRSET7 BSET7 BIL - - - LOXF BRCLR7 BCLR7 BIH CLR - TXA - j STX(+l13/10 2/7 2/4 2/6 I 1/4 I 1/4 I 2/7 I 1/6 1/· 1/2 2/2 I 2/4 I 3/5 I 3/6 I 2/5(NOTE) 1. Undefined opcodes are marked with "-".2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).Mnemonics followed by a ..... require a different number of cycles as follows:RTI 9RTS 6SWI 11BSR 83. ( indicate that the number in parenthesis must be added to the cycle count for that instruction.I,xoI Fl 1/4

--------------------------------------------------------------HD68P05V077000127128255256110 PortsTimerRAM(128 BytesROM(128 Bytes)o$000IS$07FOO$OFF$100765432100123456PortAPort BPort CPort D (digital)Port A DDRPort B DDRPort C DDR$000$001$002$003**$004"$005"$006"Not Used7Port D (analog)$007""20472048ROM(1920 Bytes)$7FF$800891031321:'}Timer Data RegTimer CTR L RegNot Used(22 Bytes)RAM (96 Bytes)St~Ck$008$009$OOA$01F$020$07F39673968408740884095Self-TestInterrupt Vectors* Write Only Registe$F7F* •$F80Read Only Register$FF7$FF8$FFF(a) HD6805U Configuration7000127128110 PortsTimerRAM(128 Bytes)ROM(3840 Bytes)o 76543210$000 01Port APort B$000$001$07F2 Port C $002$080 345678910Port D (digital)Port A DDRPort B DDRPort C DDRPort D (analog)Timer Data RegTimer CTR L RegNot Used$003*"$004"$005"$006"$007""$008$009$OOA313\127(22 Bytes)RAM (96 Bytes)Sta{k$01F$020$07F39673968408740884095Self-TestInterrupt Vectors$F7F$FOO$FF7$FF8$FFF" Write Only Register" " Read Only Register(b) HD6805V ConfigurationFigure 25 MCU Memory Configuration~HITACHI 599

HD68P05V07'------------------------------------------------------------• PRECAUTION TO USE EPROM ON THE PACKAGE a-BITSINGLE-CHIP MICROCOMPUTERAs this microcomputer takes a special packaging type withpin sockets on its surface, pay attention to the followings;(1) Do not apply higher electro-static voltage or serge voltageetc. than maximum rating, or it may cause permanentdamage to the device.(2) There are 28 pin sockets on its surface. When using 32kLet the index·side four pins open.When using 24 pin EPROM. matchits index and insert it into lower24 pin sockets.EPROM (24 pins), let the index-side four pins open.(3) When assembling this LSI into user's system products aswell as the mask ROM type 8-bit single-chip microcomputer,pay attention to the followings to keep the good ohmiccontact between EPROM pins and pin sockets.(a) When soldering on a printed circuit board, etc., keep itscondition under 250°C within 10 seconds. Over-timettemperature may cause the bonding solder of socketpins to meet and the sockets may drop.(b) Keep out detergent or coater from the pin sockets ataft-solder flux removal or board coating. The flux orcoater may make pin socket contactivity worse.(c) Avoid the permanent use of this LSI under the evervibratoryplace and system.(d) Repeating insertion/removal of EPROMs may damagethe contactivity of the pin sockets, so it is recommendedto assemble new ones to your system products.Ask our sales agent about anything unclear.600 $ HITACHI

HD68P05WO------------~MCU (Microcomputer Unit)The HD68POSWO is the 8-bit Microcomputer Unit (MCU)which contains a CPU, on-chip clock, RAM, an A/D converter,I/O and two timers. It is designed for the user who needs aneconomical microcomputer with the proven capabilities of theHD6800-based instruction set. Setting EPROM on the package,this MCU has the same function as the HD6805Wl which hason-chip ROM. It is useful not only for a means of debuggingand evaluating the HD680SWl but also for small-scale-production.The following EPROMs are available.4k byte: HN482732A8k byte: HN482764-PRELIMINARY-• HARDWARE FEATURES• 8-Bit Architecture• PIN ARRANGEMENT• 96 Bytes of RAM• Memory Mapped I/O• Internal 8-Bit Timer with 7-Bit Prescaler A,• Vectored interrupts: External, Timer and Software• 23 I/O Ports + 6 Input Ports(8 Lines Directly.Drive LEDs.)OVee VecO• On-Chip Clock GeneratorOA,2 VecO• On-Chip 8 bits A/D ConverterOA7 VecO• Two Programmable TimersOAe As 0• Master Reset OA5 A9 0• 5 Vdc Single Supply OA4 A" 0OA3 VssO• SOFTWARE FEATURES OA2 A,oO• Similar to HD6800 Family OA, CEO• Byte Efficient Instruction SetOAo 070IC• Easy to Program000 Oe 0OC• Ture Bit Manipulation00, as 0• Bit Test and Branch Instructions002 04 0• Versatile Interrupt HandingOVss 030• Powerful Indexed Addressing for Tables AN, V RH /0,• Full Set of Conditional Branches AN, 21 Vee Standby• Memory Usable as Registers/F lags• Single Instruction Memory Examine/Change(Top View)• 10 Powerful Addressing Modes• All Addressing Modes Apply to ROM, RAM and I/O• Compatible Instructiofl Set with HD6805• TYPE OF PRODUCTSType No. Bus Timing EPROM Type No.HD68P05WO1 MHz(NOTE) EPROM is not attached to the MCU.HN482732A-30HN482764-3$ HITACHI 601

HD68P05WO~-----------------------------------------------------------• BLOCK DIAGRAMTIMER10C)(lC)TIMER-2Prescaler 27Prescaler Control8 Register 2Timer Data8 Register 2Timer8 Status Register 2Output Compare8 RegisterInput Capture8 RegisterTimer Control8 Register 2Port A1/0 LinesAo ~--~--~AlA2A,A.AsA,A7,------- I000,02030405Oe07oQ.Accumulator8 AIndex Register8 XCondition Code5 Register CCStack Point6 SPProgram Counter"High"PCHProgram Counter8 "Low" PClCPUCPU ControlALUIRAME) Vee Standbyc ..0 !!.~·f.~ .. a:~.i10'

-------------------------------------------------------------HD68P05WO• ABSOLUTE MAXIMUM RATINGSItem Symbol ValueSupply Voltage Vee -0.3 - +7.0Input Voltage (EXCEPT TIMER) -0.3 - +7.0VinInput Voltage (TIMER)-0.3 - +12.0Operating Temperature Topr o -+70Storage Temperature Tstg -55 - +150UnitVVV°c°c(NOTE)This device has an input protection circuit for high quiescent voltage and field, however, be careful notto impress a high input voltage than the insulation maximum value to the high input impedance circuit.To insure normal operation, the following are recommended for V in and V out :VSS ~ (Vin or Vout) ~ Vee• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta = O-+70 o C, unless otherwise noted.)Input "liigh" VoltageItem Symbol Test Condition minRES 4.0INT I ,INT 2 3.2All OthersV IH2.2Timer 2.0RES -0.3INTr Input "Low" VoltageI ,INT 2V-0.3ILEXTAL -0.3All Others -0.3Power Dissipation Po -Low Voltage Recover LVR -TIMER -20Input Leak Current INT I ,INT 2 IlL Vin=O.4V-Vee -50EXTAL -1200Nonoperation ModeStandby VoltageVSBB 4.0Operation Mode VSB 4.75Standby Current Nonoperation Mode ISBB VSBB=4.0V -typ max Unit- Vee V- Vee V- Vee V- Vee V- 0.8 V- 0.8 V- 0.6 V- 0.8 V- 750 mW- 4.75 V- 20 p.A- 50 p.A- 0 p.A- VeeV- Vee- 3 mA• AC CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)Item Symbol Test Condition minClock Frequency fel 0.4Cycle Time teye 1.0INT Pulse WidthRES Pulse WidthTIMER Pulse WidthOscillation Start·up Time (Crystal Mode)tlWLtAWLtTwLtoset eye+250t eye+250tcye+250CL =22pF±20%Rs=60n max.-Delay Time Reset tAHL External Cap. = 2.2 p.F 100I XTAL, VRH/Ds -I nput CapacitanceI All Others Cin Vin=OV-typ max Unit- 4.0 MHz- 10 p.s- - ns- - ns- - ns- 100 ms- - ms- 35 pF- 12.5 pF$ HITACHI603

HD68P05WO~--------------------------------------------------------~-• PORT ELECTRICAl CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta = 0 '" +70°C, unless otherwise noted.)Output "High" VoltageItem Symbol Test Condition min typ max UnitPort APort aIOH = -lOJ,tA 3.5 - - VIOH =-lOOJ,tA 2.4 - - VVOH IOH = -200 J,tA 2.4 - - VIOH =-1 mA 1.5 - - VPort C IOH = -100 J,tA 2.4 - - VPorts A and C IOL = 1.6 mA - - 0.5 VOutput "Low" Voltage VOL IOL = 3.2 mA - - 0.5 VPort aIOL = 10 mA - - 1.0 VInput "High" Voltage Ports A, B, C V IH 2.0 - Vee VInput "Low" Voltage and 0* V IL -0.3 - 0.8 VVin= 0.8V -500 - - J,tAPort AI nput Leak Current IlL Vin= 2V -300 - - J,tA* Port 0 as digital InputPorts a, C and 0* Vin =0.4V-Vee -20 - 20 J,tA• AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V, Vss = AVss = GMD, Ta = 0 - +70°C, unlessotherwise noted.)Item SymbOl Test Condition min typ maxAnalog Power SupplyVoltageAVee 4.75 5.25 5.75Analog Input Voltage AVin 0 - V RHReference "High" VoltageVRH4.75V ~ V ee ~ 5.25V 4.0 - Vee5.25V < Vee ~ 5.75V 4.0 - 5.25Analog Multiplexer Input- - 7.5CapacitanceResolution Power - 8 -Conversion Time at 4MHz 76 76 76I nput Channels 4 4 4UnitVVVVpFBitt cvcChannelAbsolute Accuracy Ta = 25°C - - ±1.5LSBOff-channel Leak CurrentOff-channel Leak CurrentAVin=5.0V, AVec =4.75V, Ta= 25°C,On-channel AVin=OVAVin =OV, AVee =4.75V, Ta= 25°C,On-channel AVin =5V- 10 100-100 -10 -nAnATTL Equiv. (Port a) TTL Equiv. (Ports A, C and D)Test POintIj=3.2mATest Pojntli= 1.6mAVi40pF 12 kn 30pF 24 knVi(NOTE)1. load cap~itance includes the floating capacitance of the probe and the jig etc.2. All diodes are lS2074

-----------------------------------------------------------HD68P05WO• SIGNAL DESCRIPTIONThe input and output signals for the MCU, shown in PINARRANGEMENT, are described in the following paragraphs.• Vee and VssVoltage is supplied to the MCU using these two pins. Vee isS.2SV ±O.5V. Vss is the ground connection.• INT,/INT2This pin provides the capability for asynchronously applyingan external interrupt to the MCU. Refer to INTERRUPTS foradditional information.• XTAL and EXTALThese pins provide connections for the on-chip clock circuit.A crystal (AT cut, 4MHz maximum) or an external signal can beconnected to these pins to provide the internal oscillator withvarying degrees of stability. Refer to INTERNAL OSCILLA­TOR for recommendations about these inputs.• TIMERThis pin allows an external input to be used to count for theinternal timer circuitry. Refer to TIMER I and TIMER 2 foradditional information about the timer circuitry.• RESThis pin allows resetting of the MCU. Refer to RESETS foradditional information.• NUMThis pin is not for user application and should be connectedto Vss.• I/O Lines (Ao - A7 , Bo - B7 , Co - C6 )These 23 lines are arranged into three ports (A, B and C). Alllines are programmable as either inputs or outputs under softwarecontrol of the Data Direction Registers. Refer to INPUT IOUTPUT for additional information.• Input Lines (Do - Os)These are TTL compatible input lines, in location $0003.These also allow analog inputs to be used for an AID converter.Refer to INPUT for additional information.• Vee StandbyVee Standby provides power to the standby portion of theRAM and the STBY PWR and RAME bits of the RAM ControlRegister. Voltage requirements depend on whether the MCUis in a powerup or powerdown state. In the powerup state, thepower supply should provide Vee and must reach V SB beforeRES .reaches 4.0V. During powerdown, Vee Standby mustremain above V SBB (min) to sustain the standby RAM andSTBY PWR bit. While in powerdown operation, the standbycurrent will not exceed ISBB.It is typical to power both Vee and Vee Standby from thesame source during nomal operation. A diode must be usedbetween them to prevent supplying power to Vee during powerdownoperation shown Figure 2.To sustain the standby RAM during powerdown, the followingsoftware or hardware are needed.(I) SoftwareWhen clearing the RAM Enable bit (RAME) which is bit 6of the RAM Control Register at location $OOIF, the RAM isdisabled.Vee Standby must remain above V SBB (min).(2) HardwareWhen RAME pin is "Low" before powerdown, the RAM isdisabled. Vee Standby must remain above VSBB (min).T Vee ...""bV Powe, Un.Figure 2Battery Backup for Vee Standby• RAMEThis pin is used for the external control of the RAM. Whenit is "Low" before powerdown, the RAM is disabled. If VeeStandby remains above V SBB (min), the standby RAM issustained.• AVecThis pin is used for the power supply of the AID converter.When high accuracy is required, a different power source fromV cc is impressed asAVec = 5.25 ± O.5VConnect to Vee for all other cases.• ANo - AN3These pins allow analog inputs to be used for an AID converter.These inputs are switched by the internal multiplexerand selected by bit 0 and I of the AID Control Status Register(ADCSR: $OOOE).• VRH and AVssThe input terminal reference voltage for the AID converter is"High" (VRH) or "Low" (AVss). AVss is ftxed at OV.• Input Capture (lC)This pin is used for input of Timer2 control. in this case,Port Cs should be conftgured as input. Refer to TIMER 2 formore details.• Output Compare (OC)This pin is used for output of Timer2 when the OutputCompare Register is matched with the Timer Data Register 2.In this case, Port C 6 should be configured as an output. Refer toTIMER 2 for more details.$ HITACHI 605

HD68P05WOI-------------------------------------------------------------• REGISTERSThe CPU has five registers available to the programmer,as shown in Figure 3 and explained below.I .._____7 °A ____.... I Accumulator....____X ____..Illndex Register12 °.. I ________ pc ______-...II Program Counter12 6 5 °1 ... o .... l ... o ... l_o .... l_o .... l ... o .... l_o .... I ... 1 ..... 1 _____ s_p _---" Stack Pointer°Figure 3 Programming ModelCondition CodeRegisterCarry/BorrowZeroNegativeInterrupt MaskHalf Carry• Accumulator (A)The accumulator is a general purpose 8-bit register used tohold operands and results of arithmetic calculations or datamanipulations.• I ndex Register (X)The index register is an 8-bit register used for the indexedaddressing mode and contains an 8-bit address that may beadded to an offset value to create an effective address. Theindex register can also be used for limited calculations or datamanipulations when using read/modify/write instructions. Whennot required by a code sequence being executed, the indexregister can be used as a temporary storage area.• Program Counter (PC)The program counter is a 13-bit register that contains theaddress of the next instruction to be executed.• Stack Pointer (SP)The stack pointer is a 13-bit register that contains the addressof the next free location on the stack. Initially, the stack pointeris set to location $007F and is decremented as data is beingpushed onto the stack and incremented while data is beingpulled from the stack. The seven most Significant bits of thestack pointer are permanently set to 0000001. During an MCUreset or reset stack pointer (RSP) instruction, the stack pointeris set to location $007F. Subroutines and interrupts may benested down to location $0041 which allows the programmer touse up to 31 levels of subroutine calls.executed. These bits can be individually tested by a programand specific action taken as a result of their state. Each individualcondition code register bit is explained below.Half Carry (H)The half carry bit is used during arithmetic operations (ADDor ADC) to indicate that a carry occurred between bits 3 and 4.Interrupt (I)This bit is set to mask everything. If an interrupt occurswhile this bit is set, it is latched and will be processed as soon asthe interrupt bit is reset.Negative (N)The negative bit is used to indicate that the result of the lastarithmetic, logical or data manipulation was negative (bit 7 ina result equal to a logical one).Zero (Z)Zero is used to indicate that the result of the last arithmetic,logical or data manipulation was zero.Carry/Borrow (C)Carry/borrow is used to indicate that a carry or borrow outof the arithmetic logic unit (ALU) occurred during the lastarithmetic operation. This bit is also affected during bit test andbranch instructions, shifts and rotates.• TIMER 1The MCU timer circuitry is shown in Figure 4. The 8-bitcounter, Timer Data Register 1 (TDRl), is loaded under programcontrol and counts down toward zero as soon as the clockinput is applied. When the TDRI reaches zero, the timer interruptrequest bit (bit 7) in the Timer Control Register 1 (TCRl)is set. The MCU responds to this interrupt by saving the presentCPU state in the stack, fetching the timer 1 interrupt vectorfrom locations $OFF8 and $OFF9 and executing the interruptroutine. The timer 1 interrupt can be masked by setting thetimer interrupt mask bit (bit 6) in the TCR I. The interrupt bit(I bit) in the Condition Code Register also prevents a timer 1interrupt from being processed.The clock input to the timer 1 can be from an externalsourr.e applied to the TIMER input pin or it can be the internal2 signal. When 2 is used as the source, it can be gated by aninput applied to the TIMER input pin allowing the user toeasily perform pulse-width measurements. The timer 1 continuesto count past zero, faIling through to $FF from zero andthen continuing the count. Thus, the counter (TDRI) can beread at any time by reading the TDRI. This allows a programto determine the length of time since a timer interrupt hasoccurred and not disturb the counting process.At power-up or reset, the prescaler and counter are initializedwith all logical ones; the timer 1 interrupt request bit (bit 7) iscleared and the timer 1 interrupt mask bit (bit 6) is set. Inorder to release the timer 1 interrupt, bit 7 of the TCR I mustbe cleared by software.• Condition Code Register (CC)The condition code register is a 5-bit register in which eachbit is used to indicate or flag the results of the instruction just606 eHITACHI

-------------------------------------------------------------HD68P05WO3WriteReadFigure 4 Timer Clock• Timer Control Register 1 (TCR1: $0009)The Timer Control Register 1 (TCRl: $0009) can controlselection of clock input source and prescaler dividing ratio andtimer interrupt.Timer Control Register 1 (TCR1: $0009)765432100011Table 1 Selection of Clock Input SourceTCRlBit 5 Bit 4Clock I nput Source0 Internal Clock 1/>2 *1 1/>2 Controlled by TIMER Input1 Event-------Input From TIMER0--I TIF ITIMIIS1 I ISO l/1MS21 MS11 Msoi * The TIMER input pin must be tied to Vee. for uncontrolled ~clock input.: L" ..~ml" O",d',. "",.Clock Input SourceTimer Interrupt Mask'-----------Timer Interrupt Request FlagAs shown in Table 1, the selection of the clock input sourceis ISO and IS 1 in the TCRI (bit 4 and bit 5) and 3 kinds ofinput are selectable. At reset, internal clock 1/>2 controlled bythe TIMER input (bit 4 = 1, bit 5 = 0) is selected.The prescaler dividing ratio is selected by MSO, MSl, andMS2 in the TCRI (bit 0, bit 1, bit 2) as shown in Table 2. Thedividing ratio is selectable from eight ways (+1, +2, +4, +8, +16,+32, +64, +128). At reset, +1 mode is selected. The prescaleris initialized by writing in the TDRI.Timer 1 interrupt mask bit (TIM) allows the Timer 1 intointerrupt at "0" and masks at "1". Timer 1 interrupt causesTimer· 1 interrupt request bit (TIF) to be set. TIF must becleared by software.(NOTE)If the MCU Timerl and Timer2 are not used, theTIMER input pin must be grounded.Bit 200001111Table 2 Selection of Prescaler Dividing RatioTCRlBit 1 BitOPrescaler Dividing Ratio0 0 +10 1 +21 0 +41 1 +80 0 +160 1 +321 0 +641 1 + 128$ HITACHI607

HD68P05WOI-----------------------------------------------------------• TIMER 2The HD68POSWO includes an 8-bit programmable. timer(Timer 2) which can not only measure the input waveformbut also generate the output waveform. The pulse width forboth input and output waveform can be varied from severalmicroseconds to several seconds.(NOTE) If the MCU Timer! and Timer2 are not used, theTIMER input pin must be grounded.Timer 2 hardware consists of the followings.• 8-bit Control Register 2• 8-bit Status Register 2• 8-bit Timer Data Register 2• 8-bit Output Compare Register• 8-bit Input Capture Register• S-bit Prescaler Control Register• 7-bit Prescaler 2Block Diagram of Timer 2 is shown in Fig. S.Output Compare Register(OCR: $0010)88 bit RegisterL-_____ ...I Read/WriteInput Capture Register IICR: $001 E)8 bit Register 8 ReadTimer Control Register 2(TCR2: $001 B)ICIOCI TOIInternal Interrupts Request SignalFigure 5 Block Diagram of Timer 2• Timer Data Register 2 (TOR2; $001C)The main part of the Timer 2 is the 8-bit Timer Data Register2 (TDR2) as free-running counter, which is driven by internalclock tP2 or the TIMER input and increments the value. Thevalues in the counter is always readable by software.The Timer Data Register 2 is Read/Write register and iscleared at reset.• Output Compare Register (OCR; $0010)The Output Compare Register (OCR) is an 8-bit read/writeregister used to control an output waveform. The contents ofthis register are always compared with those of the TDR2.When these two contents conform to each other, the flag (OCF)in the Timer Status Register 2 (TSR2) is set and the value of theoutput level bit (OLVL) in the TCR2 is transferred to Port C 6(OC).If Port C 6 's Data Direction Register (DDR) is "I" (output),this value will appear at Port C 6 (OC). Then the values of OCFand OLVL can be changed for the next compare. The OCR isset to $FF at reset.• Input Capture Register nCR; $001 E)The Input Capture Register (ICR) is an 8-bit read-onlyregister used to store the value of the TDR2 when Port Cs(IC) input transition occurs as defined by the input edge bit(IEDG) of the TCR2.In order to apply Port Cs (IC) input to the edge detectcircuit, the DDR of Port Cs should be cleared ("0").·608 ~HITACHI

-------------------------------------------------------------HD68P05WOTo ensure an input capture under all condition, Port C 5(IC) input pulse width should be 2 Enable-cycles at least.*The edge detect circuit always senses Port Cs (lC) even if the DDRis set with Port Cs output.• Timer Control Register 2 (TCR2; $001B)The Timer Control Register 2 (TCR2) consists of an 5-bitregister of which all bits can be read and written.Timer Control Register 2 (TCR2: $001 B)654321 0IZVI/1ICIM I OCIM I TOIM IIEDG I OLVL IBit 0 OLVL Output LevelThis bit will appear at Port C 6 when the value in the TDR2equals the value in the OCR, if the DDR of Port C 6 is set. Itis cleared by reset.Bit 1 I EDG Input EdgeThis bit determines which level transition of Port Cs (Ie)input will trigger a data store to ICR from the TDR2. Whenthis function is used, it is necessary to clear DDR of Port Cs .When IEDG = 0, the negative edge triggers ("High" to "Low"transition). When IEDG = 1, the positive edge triggers ("Low"to "High" transition). It is cleared by reset.Bit 2 TOIM Timer Overflow Interrupt MaskWhen this bit is cleared, internal interrupt (TOI) is enabledby TOF interrupt but when set, interrupt is inhibited.Bit 5 TOF Timer Overflow FlagThis read-only bit is set when the TDR2 contains $00. Itis cleared by reading the TSR2 followed by reading of theTDR2 .Bit 6 OCF Output Compare FlagThis read-only bit is set when a match is found between theOCR and the TDR2. It is cleared by reading the TSR2 and thenwriting to the OCR.Bit 7 ICF Input Capture Flag. This read-only bit is set to indicate a proper level transitionand cleared by reading the TSR2 and then reading the TCR2.User can write into port C 6 by software.Accordingly, after port C 6 has output -by hardware and isimmediately write into by software, simultaneous cyclic pulsecontrol with a short width is easy.• Prescaler Control Register 2 (PCR2: $0019)The selections of clock input source and prescaler dividingratio are performed by the Prescaler Control Register 2 (PCR2:$0019).Prescaler Control Register 2 (PCR2: $0019)7 6 5 4 3 2 o1//lZIIS1 ISO IZI MS2 MS1 MSO'----v---------tPrescaler Dividing RatioBit 3 OCIM Output Compare Interrupt MaskWhen this bit is cleared, internal interrupt (OCI) by OCFinterrupt occurs. When set, interrupt is inhibited.Bit 41CIM Input Capture Interrupt MaskWhen this bit is cleared, internal interrupt (lCI) by ICFinterrupt occurs. When set, interrupt is inhibited.• Timer Status Register 2 (TSR2: $001 A)The Timer Status Register 2 (TSR2) is an 8-bit read-onlyregister which indicates that:(1) A proper leveltransition has been detected on the inputpin with a subsequent transfer of the TDR2 value to theICR (ICF).(2) A match has been found between the TDR2 and the OCR(OCF).(3) The TDR2 is zero (TO F).Each of the event can generate 3 kinds of internal interruptrequest and is controlled by an individual inhibit bits in theTCR2. If the I bit in the Condition Code Register is cleared,priority vectors are generated in response to clearing eachinterrupt mask bit. Each bit is described below.Timer Status Register 2 (TSR2: $001A)7 6 5 4 3 2 0ICFOCFTOF L212JZI2JZ1'---------Clock Input SourceThe selection of clock input source is performed in threedifferent ways by bit 4 and bit 5 of the PCR2, as shown inTable 3. At reset, internal clock ~2 controlled by the TIMERinput (bit 4 = I, bit 5 = 0) is selected.The prescaler dividing ratio is selected by three bits in thePCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratiocan be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64,+ 128). At reset, + 1 (bit 0 = bit I = bit 2 = 0) is selected.When writing into the PCR2, or when writing into the TDR2,prescaler is initialized to $FF.Bit 5Table 3 Selection of Clock Input SourcePCR2Bit4Clock Input Source0 0 Internal Clock q,2 *0 1 q,2 Controlled by TIMER Input1 01 1 Event Input from TIMER* The TIMER input pin must be tied to Vee. for uncontrolled t/>2clock.~HITACHI 609

HD68P05WQ--------------------------------------------------------------Table 4 Selection of Prescaler Dividing RatioPCR2Bit 2 Bit 1 BitOPrescaler Dividing Ratio0 0 0 +10 0 1 +20 1 0 +40 1 1 +81 0 0 +161 0 1 +321 1 0 +641 1 1 + 128CAUTION(1) Don't program branch instructions shown in Table 5-(1),(4) at address $117 to $IIC.(2) Don't use the instructions shown in Table 5-(1), (2), (3)for read/write/test operation of the TSR2 flags.When these instructions are executing the TSR2, two flags(TOF and rCF) of the TSR2 will sometimes cleared.Cause:These instructions have some dummy read cycles sothe TSR2 be read when executing the instructions.Table 5 Instruction Inhibited to Operate the TSR2(1 ) Bit Test and Branch InstructionMnemonic Op Code # Bytes # CyclesBRSET n (n=0-7) 2·n 3 10BRCLRn (n=0-7) 01+2· n 3 10(2) Bit Set/Clear InstructionMnemonic Op Code # Bytes # CyclesBSET n (n=0-7) 10+2· n 2 7BCLR n (n=0-7) 11+2· n 2 7(4) Branch InstructionMnemonic Op Code # Bytes # CyclesBRA 20 2 4BRN 21 2 4BHI 22 2 4BLS 23 2 4BCC 24 2 4(BHS) 24 2 4BCS 25 2 4(BLO) 25 2 4BNE 26 2 4BEQ 27 2 4BHCC 28 2 4BHCS 29 2 4BPL 2A 2 4BMI 2B 2 4BMC 2C 2 4BMS 20 2 4BIL 2E 2 4BIH 2F 2 4BSR AD 2 8• RESETSThe MCV can be reset two ways; by initial power-up and bythe external reset input (RES), see Figure 6. All the I/O portsare initialized to input mode (DDRs are cleared) during reset.During power-up, a minimum 100 milliseconds is neededbefore allowing the RES" input to go "High". This time allowsthe internal crystal oscillator to stabilize. Connecting a capacitorto the ~ input, as shown in Figure 7, typically providessufficient delay.(3) Read/Modify/Write InstructionMnemonic Op Code # Bytes # CyclesINC 3C 2 6DEC 3A 2 6CLR 3F 2 6COM 33 2 6NEG 30 2 6ROL 39 2 6ROR 36 2 6LSL 38 2 6LSR 34 2 6ASR 37 2 6ASL 38 2 6TST 3D 2 6R'ES/RAME PinInternalReset-------'i'---------------~Figure 6 Power Up and Reset TimingPart ofHD68P05WOMCU2Figure 7 Power Up Reset Delay Circuit610 ~HITACHI

-------------------------------------------------------------HD68P05WO• INTERNAL OSCILLATORThe internal oscillator circuit is designed to interface with acrystal (AT cut, 4 MHz max.) which is sufficient to drive itwith various stability. As shown in Figure 8, a 22 pF capacitor22PF±20%=ifrisrequired from EXT AL to ground. Crystal specifications aregiven in Figure 9. Alternatively, EXTAL may be driven witha duty cycle of 50% with XTAL connected to ground.6 XTAl4 MHz CJ HD68P05WOmax 5 EXTAl MCUExternalClockInput6 XTAlHD68P05WO5 EXTAl MCUExternal ClockFigure 8 Internal Oscillator OptionsTable 6 Interrupt PrioritiesAT - Cut Parallel Resonance CrystalCo = 7 pF max.f = 4 MHz IC, =22pF±20%)Rs= 60n max,Figure 9 Crystal parameters• INTERRUPTSThe MCU can be interrupted in seven different ways: throughexternal· interrupt input pin ~ and INT 2)' internal timerinterrupt request (Timer I, ICI, OCI and OFI) and a softwareinterrupt instruction (SWI). 1N'r 2 and Timer I are generatedby the same vector address. When interrupt occurs, processingof the program is suspended, the present CPU state is pushedonto the stack. Figure 10 shows interrupt stacking order.Moreover, the interrupt mask bit (I) of the Condition CodeRegister is set and the external routine priority address isachieved from the special external vector address. After that,the external interrupt routine is executed. The interruptservice routines normally end with a return from interrupt(RTI) instruction which allows the CPU to resume processingof the program prior to the interrupt. The priority interruptsare shown in Table 6 with the vector address that containsthe starting address of the appropriate interrupt routine. Theinterrupt sequence is shown as a flowchart in Figure 11.Note that the Vector Address when using the 8k byte typeEPROM is'different from the 4k byte type EPROM.4k bytestype8k bytestypePushn-4Interrupt PriorityRES" 1SWI 2INT, 3Timer/IN'2 4ICI 5OCI 6OFI 7Interrupt PriorityRES 1SWI 2INT, 3Timer/mi 2 4ICI 5OCI 6OFI 76 5 4 3 2 01 111ConditionCode Registern-3 Accumulatorn-2 Index Registern-1 1 1~PCH*PCl*Vector Address$OFFE, $OFFF$OFFC, $OFFD$OFFA, $OFFB$OFF8,$OFF9$OFF6, $OFF7$OFF4, $OFF5$OFF2,$OFF3Vector Address$1FFE,$1FFF$1FFC,$1FFD$1FFA,$1FFB$1FF8,$1FF9$1FF6,$1FF7$1FF4,$1FF5$1FF2,$1FF3n+1n+2n+3n+4n+5Pull* For subroutine calls, only PCH and PCl are stacked.Figure 10 Interrupt Stacking OrdereHITACHI 611

HD68P05WO'-----------------------------------------------------------yINT.yINT,Cleary TIMER 11-+-17F -+-SPo -+-DDR'sCLR INT Logic7F-+-MRFF-+-TDR100-+-TDR27F -+- Prescaler 17 F -+- Prescaler 250-+-TCR11C-+-TCR200-+-TSR210 -+-PCR2Fetch InstructionyyYICIOCIStack PC, X, CC, AExecute InstructionTypeSWIINf";""TIMERINT,ICIOCIOFILoad PC From4k bytes8k bytes$OFFC, $OFFD I $1 FFC, $1 FFD$OFFA, $OFFB I $1 FFA, $1 FFB$OFF8,$OFF9 I $1FFS,$1FF9$OFFS,$OFF9 I $1FF8,$1FF9$OFF6,$OFF7 I $1FF6,$1FF7$OFF4,$OFF5 I $1FF4,$1FF5$OFF2,$OFF3 I $1FF2,$1FF3Figure 11Interrupt Flowchart• Miscellaneous Register (MR: $OOOA)The vector address generated by the external interrupt(1NT 2 ) is the same as that of TIMERI as shown in Table 6.The miscellaneous register (MR) controls the 1NT2 interrupt.7IRFMiscellaneous Register (MR: $OOOA)6 5 4 3 2 01M[21ZVV121ZIL-------INT2 Interrupt MaskL----------INT2 Interrupt Request Flag612 $ HITACHI

------~-------------------------------------------------------HD68P05WOBit 7 (IRF) of the MR is used as an 1NT2 interrupt requestflag. 1NT"2 interrupt occurs at the lliff2 negative edge, andIRF is set. lNT"2 interrupt or not can be proved by checkingIRF by software in the interrupt routine of the vector address($FF8, $FF9). IRF should be reset by software (BCLR instruction).Bit 6 (1M) of the MR is an 1NT2 interrupt mask bit. When1M is set, IN'f; interrupt is disabled. 1NT2 interrupt is alsodisabled by bit (I) of the Condition Code Register (CC) likeother interrupts.IRF is available for both read and write. However, IRF isnot writable by software. Therefore, 1N'F 2 interrupt cannotbe requested by software. At reset, IRF is cleared and 1M isset.• INPUT/OUTPUTThere are 23 input/output pins. All pins are controlled bythe Data Direction Register and both input and output areprogrammable. When programmed as output, the latchedoutput data is readable as input data, regardless of the logiclevels at the output pin due to output loading (See Figure 12.)When Port B is programmed for output, it is capable of sinking10 rnA on each pin (VOL max. = IV). Furthermore, Port A isCMOS compatible as output. Ports Band C are CMOS compatibleas inputs. Some examples of the Port connections areshown in Figure 13.Port Cs and C6 are also used for Timer 2.When Port Cs is used as Timer 2 Input Capture (I C) , PortCs's DDR should be cleared (Port Cs as input) and bit 4 (ICIM)in the Timer Control Register 2 (TCR2) should be cleared too.The Input Capture Register (lCR) stores the TDR2 when aPort Cs input transition occures as defined by bit 1 (IDEG) ofthe TCR2.When Port C6 is used as Timer 2 Output Compare (OC), PortC6 's DDR should be set (port C6 as output). When the OutputCompare Register (OCR) matches the TDR2, bit 0 (OLVL) inthe TCR2 is set and OLVL will appear at Port C6. Port C6 iswritable by software. But the writing by software is unavailablewhen a match between the TDR2 and the OCR is found at thesame time.DataDirection Output Output Input toRegister Data Bit State MCUBit1 0 0 01 1 1 10 x 3-State PinFigure 12 Typical Port I/O Circuitry$ HITACHI 613

HD68P05WO-----------------------------------------------------------Port AAo·•A, ·Port BPort A Programmed as output(s), driving CMOS and TTL Load directly.(a)Port BBo·•B, ·+vR10mA - maxPort B Programmed as output(s), driving LED(s) directly.(elFigure 13 Typical Port ConnectionsPort B Programmed as output(s), driving Darlington base directly.(b)Port CC. ·+vRI----..... ---;~ CMOS InverterPort C Programmed as output(s), driving CMOS load(s), using externalpull-up resistors.(d)• INPUTPort D is usable as either TTL compatible inputs or a 4-channel input for an AID converter. Fig. 14 shows port D logicconfiguration.The Port D register at location $003 stores TTL compatibleinputs. When using as analog inputs for an AID converter,refer to "AID CONVERTER"• AID CONVERTERThe HD68P05WO has an internal 8 bit AID converter. '{heAID converter, shown in Figure 15, includes 4 analog inputs(ANo to AN3), the Result Register (ADRR) and the ControlStatus Register (ADCSR).CAUTIONThe MCU has circuitry to protect the inputs against damagedue to high static voltages or electric field; however, the designof the input circuitry for the AID converter, ANo -- AN3, V RHand A V cc, does not offer the same level of protection. Precautionsshould be taken to avoid applications of any voltagehigher than maximum-rated voltage or handled in any environmentproducing high-static voltages.$0003 ReadInternal Bus 1-...... ____ Port 0(D. to Os)O/A4AVss--------lAnalog InputFigure 14 Port DANoAN,AN,AN3Select MUXAVec 0-0---_SV8 Bit Register (AORR: $OOOF)AID Control Status Register(AOCSR, $CODE)AID Result Register (AORR: SOOOF)Figure 15 AID Converter Block Diagram614eHITACHI

-----------------------------------------------------------HD68P05WO• Analog Input (ANo to AN3 )Analog inputs ANo to AN3 accept analog voltages of OVto 5V. The resolution is 8 bits (256 divisions) with a conversiontime of 76 J.l.S at I MHz. Analog conversion starts selectinganalog inputs by bit 0 and bit I of the ADCSR analog input.Since the CPU is not required during conversion, other userprograms can be executed.Bit 1ADCSRTable 7 Analog Input SelectionBit aAnalog Input Signala d ANoa 1 ANI1 a ANz1 1 AN3• AID Control Status Register (ADCSR: $OOOE)The Control Status Register (ADCSR) is used to selectanalog input pin and confirm A/D conversion termination.An analog input pin is selected by bit 0 and bit I as shown inTable 7.A/D conversion begins when the data is written into bit 0and bit I of the ADCSR. When A/D conversion ends, bit 7(CEND) is set. Bit 7 is reset after the ADRR is read. Even ifbit 7 is set, A/D conversion execution still continues. To endthe A/D conversion, the A/D Result Register (ADRR) stores themost current value. During A/D conversion execution, newdata is written into the ADCSR selecting the input channel andthe A/D conversion execution at that time is suspended. CENDis reset and new A/D conversion begins.• AID Result Register (ADRR: $OOOF)When the AID conversion ends, the result is set in the A/DResult Register ($OOOF). When CEND of the ADCSR is set,converted result is obtained by reading the ADRR. Furthermore,CEND is cleared.• STANDBY RAMThe portion from $020 to $027 of the RAM can be used forthe standby RAM.When using the standby RAM, Vee Standby should remainabove VSBB (min) during powerdown. Consequently, power isprovided only to the standby RAM and STBY PWR bit of theRAM Control Register. 8 byte RAM is sustained with smallpower dissipation. The RAM including the standby RAM iscontrolled by the RAM Control Register (RCR) or RAME pin.~====:::::::;;;;::~~~..L..JRAM CTRLReg. 1$001 F 1• RAM Control Register (RCR: $001 F)This register at location $01 F gives the status informationabout the RAM. When RAM Enable bit (RAME) is "0", theRAM is disabled. When Vee Standby is greater than VSBB,Standby Power bit (STBY PWR) is set and the standby RAM issustained during powerdown.RAM Control Register (RCR: $OalF)7 6543210$001F I ~ri I RAM" 021/1NVlBit 6 RAM EnableRAME bit is set or cleared by either software or hardware.When the MCU is reset, RAME bit is set and the RAM is enabled.If RAME bit is cleared, the user can neither read nor writethe RAM.When the RAM is disabled (logic "0"), the RAM address isinvalid.Bit 7 Standby PowerSTBY PWR bit is cleared whenever Vee standby decreasesbelow VSBB (min). This bit is a read/write status bit that theuser can read. When this bit is set, it indicates that the standbypower is applied and data in the standby RAM is valid.• RAME SignalRAME bit in the RCR can be cleared when RAME pin goes"Low" by hardware (RAM is disabled). To make standby modeby hardware, set RAME pin "Low" during Vee Standby remainsabove VSBB (min) and powerdown sequence should be asshown in Fig. 17.When RAME pin gets "Low" in the powerup state, RAMEbit of the RCR is cleared and the RAM is disabled. Duringpowerdown, RAME bit is sustained by Vee Standby. WhenRAME pin gets "High" in the powerup state, RAME bit of theRCR is set and the RAM is enabled.RAME pin can be used to control the RAM externally withoutsoftware.RAMEVeeRAM Enable\ vee OFF /~------r~ RAMm .....Figure 17 RAM Control Signal (RAME)RAM196BI1--___ ~$OO7FFigure 16 Standby RAM• BIT MANIPULATIONThe MCU has the ability to set or clear any single RAM orinput/output port (except the data direction registers) with asingle instruction (BSET and BCLR). Any bit in the page zeroread only memory can be tested by using the BRSET andeHITACHI 615

HD68P05WQ-------------------------------------------------------------BRCLR instructions, and the program branches as a result ofits state. This capability to work with any bit in RAM, ROM orI/O allows the user to have individual flags in RAM or to handlesingle I/O bits as control lines. The example in Figure 18 showsthe usefulness of the bit manipulation and test instructions.Assume that bit 0 of port A is connected to a zero crossingdetector circuit and that bit 1 of port A is connected to thetrigger of a TRIAC which powers the controlled hardware.This program, which uses only seven bytes of ROM providestum-on of the TRIAC within 14 microseconds of the zerocrossing. The timer is also incorporated to provide tum-on atsome later time which permits pulse-width modulation of thecontrolled power.•to the branch instructions. In this mode the contents of thebyte following the opcode is added to the program counterwhen the branch is taken. EA = (PC) + 2 + ReI. Rei is the contentsof the location following the instruction opcode with bit 7being the sign bit. If the branch is not taken, Rei = 0, when abranch takes place, the program goes to somewhere within therange of + 129 bytes to -127 bytes of the present instruction.These instructions are two bytes long.• Indexed (No Offset)Refer to Figure 23. This mode of addressing accesses thelowest 256 bytes of memory. These instructions are one bytelong and their EA is the contents of the index register.SELF 1BRClRO, · PORTA, SELF 1BSET 1, PORTABClR 1, PORTA• Indexed (a-bit Offset)Refer to Figure 24. The EA is calculated by adding the contentsof the byte following the opcode to the contents of theindex register. In this mode, 511 low memory locations areaccessable. These instructions occupy two bytes.Figure 18 Bit Manipulation Example• ADDRESSING MODESThe MeU has ten addressing modes available for use by theprogrammer. These modes are explained and illustrated brieflyin the following paragraphs.• ImmediateRefer to Figure 19. The immediate addressing mode accessesconstants which do not change during program execution. Suchinstructions are two bytes long. The effective address (EA) isthe PC and the operand is fetched from the byte following theopcode.• DirectRefer to Figure 20. In direct addressing, the address of theoperand is contained in the secondbyte of the instruction.Direct addressing allows the user to directly address the lowest256 bytes in memory. AU RAM space, I/O registers and 128bytes of ROM are located in page zero to take advantage ofthis efficient memory addressing mode.• ExtendedRefer to Figure 21. Extended addressing is used to referenceany location in memory space. The EA is the contents of thetwo bytes following the opcode. Extended addressing instructionsare three bytes long.• RelativeRefer to Figure 22. The relative addressing mode applies only• Indexed U6-bit Offset)Refer to Figure 25. This addressing mode calculates the EAby adding the contents of the two bytes following the ope odeto the index register. Thus, the entire memory space may beaccessed. Instructions which use this addressing mode arethree bytes long.• Bit Set/ClearRefer to Figure 26. This mode of addressing applies toinstructions which can set or clear any bit on page zero. Thelower three bits in the opcode specify the bit to be set orcleared while the byte following the opcode specifies theaddress in page zero.• Bit Test and BranchRefer to Figure 27. This mode of addressing applies toinstructions which can test any bit in the fust 256 locations($0000 through $ooFF) and branch to any location relative tothe PC. The byte to be tested is addressed by the byte followingthe opcode. The individual bit within that byte to be testedis addressed by the lower three bits of the opcode. The thirdbyte is the relative address to be added to the program counterif the branch condition is met. These instructions are threebytes long. The value of the bit to be tested is written to thecarry bit in the condition code register.• ImpliedRefer to Figure 28. The implied mode of addressing hasno EA. All of the information necessary to execute an instructionis contained in the opcode. Direct operations on theaccumulator and the index register are included in this modeof addressing. In addition, control instructions such as SWIand RTI belong to this group. All implied addressing instructionsare one byte long.616 _HITACHI

-------------------------------------------------------------HD68P05WOMemory8IIi IIIPROG LOA #$F8 05BE A61-------405BF F8IIAIndex esIStack PointProg Count05COF8§III ,Figure 19 Immediate Addressing ExampleIIIIIICAT FCB 32 004BIPROG LOA CAT 0520052E+ Memory20864BIIIIIIIlEAI004BJ/'1Adder~O~OOIIAJl20JIndex RegIIStack PointProg Count052FCCIII~IIIIiFigure 20 Direct Addressing Example_HITACHI617

HD68P05WO-------------------------------------------------------------Memory0000PROG LOA CATA40Index RegStack PointCAT FeB 64 06E540Prog Count040CCCFigure 21Extended Addressing ExampleMemoryiII~IPROG SEQ PROG2 04A7 2704A8 180000AStack PointIndex Reg§II, ,Figure 22 Relative Addressing Example618 ~HITACHI

---------------------------------------------------------------HD68P05WOMemoryTABL FCC t Lit 00B8 4C49A4CIndex RegB8PROG LOA XI~F4~§II,Stack PointProg Count05F5CCFigure 23 Indexed (No Offset) Addressing ExampleTABL FCB #BF 0089FCB #86 008AFCB #OB 008BFCB #CF 008CIIPROG LOA TABL. X 075B075ClEAMelory008CI IIJtJIAdderIL'"B6 I' IBFDBCFIIE689§IIIIIIAJCFLIndex RegII 03IStack PointIProg Count0750ICCIII, ,Figure 24 Indexed (8-Bit Offset) Addressing Example_HITACHI619

HD68P05WO-------------------------------------------------------------MemoryiI§ADBIndex RegPROGLOAIITABL. X 0692 ~60693 070694 7E f--------'Stack PointProg Count069502IICCTABl FCB #BF 077E BFFCB #86 077F 86FCB #DB 0780 ~--!:D~B~ _ _t----.:..-------------'FCB #CF 0781 CFFigure 25 Indexed (l6-Bit Offset) Addressing ExampleMemoryPORT B EQU 0001 BF0000AIndex RegPROG BelR 6. PORT B 058F 10t-------I0590 01Stack PointI§IProg Count0591CCIII620Figure 26 Bit Set/Clear Addressing Example$ HITACHI

---------------------------------------------------------------HD68P05WOPORT C EQU 2 0002PROG BRCLR 2. PORT C. PROG 2 057405750576Mem~OrYiI,I,FO,III05I'/Bit202 000010,I" JOR~~~ ~I ,lEA0002tAdderJAdder/I~t0000IIAIIIStack PointIndex RegIIIProg Count0594JCCI C JFigure 27 Bit Test and Branch Addressing ExampleMemoryi,PROGTAX.~ ,I05BA~Prog CountIndex RegE5AE5,§05BBccFigure 28 Implied Addressing Example$ HITACHI621

·HD68P05WO-------------------------------------------------------------• INSTRUCTION SeTThe MeV has a set of 59 basic instructions. These instructionscan be divided into five different types; register/memory,read/modify/write, branch, bit manipulation and control. Eachinstruction is briefly explained below. All of the instructionswithin a given type are presented in individual tables.• Register/Memory InstructionsMost of these instructions use two operands. One operandis either the accumulator or the index register. The otheroperand is obtained from memory by using one of the addressingmodes. The jump unconditional (JMP) and jump to subroutine(JSR) instructions have no register operand. Refer toTable 8.• ReadlModify/Write InstructionsThese instructions read a memory location or a register,modify or test its contents and write the modified value backto the memory or register. The TST instruction for test ofnegative or zero is an exception to the read/modify/writeinstructions since it does not perform the write. Refer to Table9.• Branch InstructionsThe branch instructions cause a branch from a programwhen a certain condition is met. Refer to Table 10.• Bit Manipulation InstructionsThese instructions are used on any bit in the first 256 bytesof the memory. One group either sets or clears. The othergroup performs the bit test and branch operations. Refer toTable 11.• Controllnstructi!>nsThe control ilJstructions control the MeV operations duringprogram execution. Refer to Table 12.• Alphabetical ListingThe complete instruction set is given in alphabetical orderin Table 13.• OpcodeMapTable 14 is an opcode map for the instructions used on theMeV.622 _HITACHI

Table 8 Register/Memory InstructionsAddressing ModesFunctionLoad A from MemoryLoad X from MemoryStore A in MemoryStore X in MemoryAdd Memory to AMnemonicLOALOXSTASTXADDImmediateOp # #Code Bytes CyclesA6 2 2AE 2 2- - -- - -AB 2 2DirectExtendedIndexed(No Offset)Op # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesB6 2 4 C6 3 5 F6 1 4BE 2 4 CE 3 5 FE 1 4B7 2 5 C7 3 6 F7 1 5BF 2 5 CF 3 6 FF 1 5BB 2 4 CB 3 5 FB 1 4Indexed(8-Bit Offset)Op # #Code Bytes CyclesE6 2 5EE 2 5E7 2 6EF 2 6EB 2 5Indexed(16-Bit Offset)Op # #Code Bytes Cycles06 3 6OE 3 607 3 7OF 3 7OB 3 6$%~o!Add Memory andcarry to ASubtract MemorySubtract Memory fromA with BorrowAND Memory to AOR Memory with AADCSUBSBCANDORAA9 2 2AO 2 2A2 2 2A4 2 2AA 2 2B9 2 4 C9 3 5 F9 1 4BO 2 4 CO 3 5 FO 1 4B2 2 4 C2 3 5 F2 1 4B4 2 4 C4 3 5 F4 1 4BA 2 4 CA 3 5 FA 1 4E9 2 5EO 2 5E2 2 5E4 2 5EA 2 509 3 600 3 602 3 604 3 6OA 3 6Exclusive OR Memorywith AEORA8 2 2B8 2 4 C8 3 5 F8 1 4E8 2 508 3 6Arithmetic Compare Awith MemoryCMPAl 2 2Bl 2 4 Cl 3 5 Fl 1 4El 2 501 3 6Arithmetic Compare Xwith MemoryCPXA3 2 2B3 2 4 C3 3 5 F3 1 4E3 2 503 3 6Bit Test Memory with A(Logical Compare)BITA5 2 2B5 2 4 C5 3 5 F5 1 4E5 2 505 3 60)I\)c:.lJump Unconditional.Jump to SubroutineSymbols:Op: Operation Abbreviation# : Instruction StatementJMPJSR- - -- - -BC 2 3 CC 3 4 FC 1 3BD 2 7 CO 3 8 FO 1 7---- -~~EC 2 4EO 2 8DC 3 500 3 9:J:o0)(X)"tJoCJ1~

0)I\)~::I:o0)00"'0o(11~Table 9 Read/Modify/Write InstructionsAddressing ModesFunctionMnemonicImplied (A) Implied (X) DirectOp # # Op # # Op # #Code Bytes Cycles Code Bytes Cycles Code Bytes CyclesIndexed(No Offset)Op # #Code Bytes CyclesIndexed(8-Bit Offset)Op # #Code Bytes CyclesIncrementINC4C 1 4 5C 1 4 3C 2 67C 1 66C 2 7DecrementDEC4A 1 4 5A 1 4 3A 2 67A 1 66A 2 7ClearCLR4F 1 4 5F 1 4 3F 2 67F 1 66F 2 7-%~o~ComplementNegate(2's Complement)Rotate Left Thru CarryRotate Right Thru CarryLogical Shift LeftCOMNEGROLRORLSL43 1 4 53 1 4 33 2 640 1 4 50 1 4 30 2 649 1 4 59 1 4 39 2 646 1 4 56 1 4 36 2 648 1 4 58 1 4 38 2 673 1 670 1 679 1 676 1 678 1 663 2 760 2 769 2 766 2 768 2 7Logical Shift RightLSR44 1 4 54 1 4 34 2 674 1 664 2 7Arithmetic Shift RightASR47 1 4 57 1 4 37 2 677 1 667 2 7Arithmetic Shift LeftASL48 1 4 58 1 4 38 2 678 1 668 2 7Test for Negative orZeroTST4D 1 4 5D 1 4 3D 2 67D 1 66D 2 7Symbols:Op: Operation Abbreviation# : Instruction Statement

-------------------------------------------------------------HD68P05WOTable 10 Branch InstructionsRelative Addressing ModeFunction Mnemonic Op # #Code Bytes CyclesBranch Always BRA 20 2 4Branch Never BRN 21 2 4Branch IF Higher BHI 22 2 4Branch I F lower or Same BlS 23 2 4Branch I F Carry Clear BCC 24 2 4(Branch IF Higher or Same) (BHS) 24 2 4Branch I F Carry Set BCS 25 2 4(Branch I Flower) (BlO) 25 2 4Branch I F Not Equal BNE 26 2 4Branch I F Equal BEQ 27 2 4Branch IF Half Carry Clear BHCC 28 2 4Branch I F Half Carry Set BHCS 29 2 4Branch IF Plus BPl 2A 2 4Branch IF Minus BMI 2B 2 4Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4Branch IF Interrupt Mask Bit is Set BMS 20 2 4Branch IF Interrupt Line is low Bil 2E 2 4Branch IF Interrupt Line is High BIH 2F 2 4Branch to Subroutine BSR AD 2 8Symbols: Op: Operation Abbreviation #: Instruction StatementTable 11Bit Manipulation InstructionsAddressing ModesFunction Mnemonic Bit Set/Clear Bit Test and BranchOp # # Op # #Code Bytes Cycles Code Bytes CyclesBranch IF Bit n is set BRSET n (n=O ..... 7) - - - 2·n 3 10Branch I F Bit n is clear BRClR n (n=O ..... 7) - - - 01+2·n 3 10Set Bit n BSET n (n=O ..... 7) 10+2·n 2 7 - - -Clear bit n BClR n (n=O ..... 7) 11+2·n 2 7 - - -Symbols: Op: Operation Abbreviation #: Instruction StatementFunctionTable 12 Control InstructionsMnemonicImpliedOp # #Code Bytes CyclesTransfer A to X TAX 97 1 2Transfer X to A TXA 9F 1 2Set Carry Bit SEC 99 1 2Clear Carry Bit ClC 98 1 2Set Interrupt Mask Bit SEI 9B 1 2Clear Interrupt Mask Bit CLI 9A 1 2Software Interrupt SWI 83 1 11Return from Subroutine RTS 81 1 6Return from Interrupt RTI 80 1 9Reset Stack Pointer RSP 9C 1 2No-Operation NOP 90 1 2..Symbols: Op: Operation AbbreViation #: Instruction Statement$ HITACHI 625

HD68P05WO--------------------------------~------------------------___MnemonicImpliedImme- Ex- RediateDirecttended lativeTable 13 Instruction SetAddressing ModesIndexed(NoIndexed Indexed(8 Bits) (16 Bits)Condition CodeBit BitSet! Test & H I N Z COffset) Clear BranchADC x x x x x x A A A AADD x x x x x x A A A AAND x x x x x x A A •ASl x x x x A A AASR x x x x A A ABCC x BClR x• • • • •BCS x BEQ x BHCC x BHCS x BHI x• • • • •BHS x• • • • •BIH x• • • • •Bil x• • • • •BIT x x x x x x• • A A •BlO x• • • • •BlS x• • • • •BMC x• • • • •BMI x• • • • •BMS x• • • • •BNE x• • • • •BPl x• • • • •BRA x• • • • •BRN x• • • • •BRCLR x• • • • ABRSET x• • • • ABSET x• • • • •BSR x• • • • •CLC x• • • • 0Cli x• 0 • • •CLR x x x x• • 0 1 •CMP x x x x x x• • A A ACOM x x x x• • A A 1CPX x x x x x x• • A A ADEC x x x x• • A A •EaR x x x x x x• • A A •INC x x x x• • A A •JMP x x x x x• • • • •JSR x x x x x• • • • •LDA x x x x x x• • A A •LOX x x x x x x• • A A •Condition Code Symbols:H Half carry (From Bit 3) C Carry BorrowI Interrupt Mask A Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero (to be continued)626 _HITACHI

---------------------------------------------------------------HD68P05WOMnemonicImpliedAddressing ModesImme- Ex- Re-Directdiatetended lativeTable 13 Instruction SetCondition CodeIndexedBit Bit(NoIndexed Indexed(8 Bits) (16 Bits)Set/ Test & H I N Z COffset) Clear BranchLSL x x x x 1\ 1\ 1\LSR x x x x 0 1\ 1\NEQ x x x x 1\ 1\ 1\NOP x • • ORA x x x x x x 1\ 1\ •ROL x x x x 1\ 1\ 1\ROR x x x x 1\ 1\ 1\RSP x• • • • •RTI x ? ? ? ? ?RTS x • • •SBC x x x x x x 1\ 1\ 1\SEC x • 1SEI x 1 • • STA x x x x x 1\ 1\ STX x x x x x 1\ 1\ •SUB x x x x x x • 1\ 1\ 1\SWI x 1 TAX x • • TST x x x x 1\ 1\ TXA x • • • • •Condition Code Symbols:H Half Carry (From Bit 3) C Carry/BorrowI I nterrupt Mask 1\ Test and Set if True, Cleared OtherwiseN Negative (Sign Bit) • Not AffectedZ Zero ? Load CC Register From StackTable 14 Opcode MapBit Manipulation Brnch Read/Modify/Write Control Register IMemoryTest & SetlBranch ClearRei OIRI A I X IXl I ,XO IMP IMP IMM I OiR I EXT I X2 I Xl I ,XO0 1 2 3 I 4 I 5 I 6 I 7 8 9 J A B I C 1 0 I E 1F ... H IGH0 BRSETO BSETO BRA NEQ RTI' - SUB 01 BRCLRO BCLRO BRN - RTS* - CMP 12 BRSET1 BSET1 BHI - - - SBC 23 BRCLR1 BCLR1 BLS COM SWI' - cpx 34 BRSET2 BSET2 BCC LSR - - AND 45 BRCLR2 BCLA2 BCS - - - BIT 56 BRSET3 BSET3 BNE ROR - - LOA 67 BRCLR3 BCLR3 BEQ ASR - TAX - I STA(+1) 78 BRSET4 BSET4 BHCC LS LIAS L - CLC EOR 89 BRCLR4 BCLR4 BHCS ROL - SEC AOC 9A BRSET5 BSET5 BPL DEC - CLI ORA AB BRCLR5 BCLR5 BMI - - SEI ADD BC BRSET6 BSET6 BMC INC - RSP - I JMPH) Co BRCLR6 BCLR6 BMS TST - NOP BSR*I JSR(-3) 0E BRSET7 BSET7 BIL - - - LOX EF BRCLR7 BCLR7 BIH CLR - TXA - 1 STX(+1) F3/10 2/7 2/4 2/6 I 1/4 I 1/4 I 2/7 I 1/6 1/' 1/2 2/2 I 2/4 I 3/5 I 3/6 I 2/5 I 1/4[NOTE) 1. Undefined opcodes are marked with "-".2. The number at the bottom of each column denotes the number of bytes and the number of cycles required (Bytes/Cycles).Mnemonics followed by a "." require a different number of cycles as follows:RTI 9RTS 6SWI 11eSR 8.3. ( ) indicates that the number in parenthesis must be added to the cycle count for that instruction.$ HITACHILoW627

HD68P05WO-------------------------------------------------------------• HD68P05WO USED FOR HD6805W1The HD680SWI provides mask option of the internal oscillatorand low voltage inhibit, while the HD68POSWO providesonly crystal option and without low voltage inhibit function,The address from $OF7A to $OFFI cannot be used for userprogram because the self test program of the HD680SWI (on--SOOOO$000'$0002, IOO'F....~RAM-.... al121 1OO7F'28- - - - - - - - - - - - - - - SOF7A(Self Ten):;I--------I:~~~InttrruptVectonTim.r Oale Reg. 1$0003"$0004'$0006'$0006'$0007SOOO8Timer CTRL Reg, 1 $0009AID CrRL Stanll Reg$OOOA$0008$OOOC$0000$OOOESOOOF··100101001110012100131001.10015100161001710018Prescaler eTR l Reg. 2 10019TimerSt&lusReg.21OO1A"Timer CTRl Reg. 2 $0018$00ICOutput Complr. RItg $0010$00IE"~~"=AM~C=on="O~I"~~~-__I::~__________________ Standby RAM 18BI'" 10027 ,10028)chip ROM version) is located at these addresses,In order to be pin compatible with the HD680SW1, theaddress of the HD68POSWO's ROM must be located at $0080 -$OFFF, Memory addresses $1000 to $1 FFF should not beusable,-03'032 I---------I=~RAM196al"OM18050 I$007FSOO8O1----== ______1 soooo1----== ______1 $00011----== ______1 $0002I----.-:= ____ ~ $0003"I----.-:== ___ ~ $0004'1----=== _____1 $0005'I----.-:== ___ ~ $0006'.I--______ ~ $0007I-----.:T~'me=_' :::0'::.:""::;"!:..:. '~___I SOOO8I----=:.::::::.=:.=~_~ $00091-----===='------1 $OOOA1--_______ ---1 $0008I--________ ---I$OOOC1--______ __1 $0000I----=A::;:'O..::..CT:.:.:"::..:L S::::,,,:::u'':'::"~'''--_-l $OOOEI---==::::::":~ ____I $OOOF"1--______ __1 $00101--______ ---1 100111--______ __1 $00121--______ ---1 10013I--______ ~ 1001.I--______ ~ $00151--______ __1 10016I--______ .~ $0017I--______ ~ $0018I----=p::::".:::".~=_' ::.:.CT.:::"L:.::"~~:.:. '_~ $0019I-----=T.:::' ... :::.,:::S":::,",:.:."",, ..;..:.'__-I $001A··I--~T.:::"":::.':::.CT.:.:."L:..:.";.:.:"c.:. '__-I $0018I-----=T.:::'"":::.,.:::O,:=,,.:.:.:":::..:..,__-I $00ICI-----=O.:::u,=pu.:...::Oo:..:. ..... =-,._".:..:.. _~ $0010\I--"::=::'=::::':.::!:...---l $00IE"~--=::::":=~'------l =~sr )St*,dby RAM 18 8t··· s6007------------------ $0028'-____ --1.._---1 $007FL-______ ...JSOFFF·Writ.Reg'-ReadReg"'Standby RAM uses fim B byllH of RAM·WrlteAIf.·-ReIldR".• ··StlnCIbV RAM UIIt fir.t B by'" 0' RAMFigure 29 MCU Memory Structure (For 32k bytes)h't~uplVectonL-______ ...J"FFFFigure 30 MCU Memory Structure (For 64k bytes)-CAUTION -This 64k bytes type should not be used debuggingon-chip ROM of the HD6805W1.628 eHITACHI

-------------------------------------------------------------HD68P05WO• PRECAUTION TO USE EPROM ON THE PACKAGE 8-BITSINGLE-CHIP MICROCOMPUTERAs this microcomputer takes a special packaging type withpin sockets on its surface, pay attention to the followings;(1) Do not apply higher electro-static voltage or serge voltageetc. than maximum rating, or it may cause permanentdamage to the device.(2) There are 28 pin sockets on its surface. When using 32kLet the index-side four pins open.When using 24 pin EPROM, matchits index and insert it into lower24 pin sockets.EPROM (24 pins), let the index-side four pins open.(3) When assembling this LSI into user's system products aswell as the mask ROM type 8-bit single-chipmicrocomputer,pay attention to the followings to keep the good ohmiccontact between EPROM pins and pin sockets.(a) When soldering on a printed circuit board, etc., keep itscondition under 250°C within 10 seconds. Over-time/temperature may cause the bonding solder of socketpins to meet and the sockets may drop.(b) Keep out detergent or coater from the pin sockets ataft-solder flux removal or board coating. The flux orcoater may make pin socket contactivity worse_(c) Avoid the permanent use of this LSI under the evervibratoryplace and system.(d) Repeating insertion/removal of EPROMs may damagethe contactivity of the pin sockets, so it is recommendedto assemble new ones to your system products.Ask our sales agent about anything unclear.$ HITACHI 629

HD63P01 M1 ,HD63PA01 M1,­HD63PB01 M1CMOS MCU (Microcomputer Unit)The HD63POIMI is an 8-bit single chip Microcomputer Unit(MeU) which has 4096 bytes or 8192 bytes of EPROM onthe package. It is pin and function (except ROM) compatiblewith the HD6301Vl. The HD63POIMI can be used to emulatethe HD6301Vl for software development or it can be used inproduction to allow for easy firmware changes with minimumdelay.- The specifications for HD63PA01Ml and HD63PB01Ml are preliminary. -HD63P01M1, HD63PA01M1,HD63PB01M1• FEATURES• Pin Compatible with HD6301V1• On Chip Function Compatible with HD6301V1• 128 Bytes of RAM• 29 Parallel I/O• 16 Bit Programmable Timer• Serial Communication Interface• Low Power Consumption ModeSleep Mode, Standby Mode• Minimum Instruction Cycle Timel~s (f = 1 MHz), O.67~s (f = 1.5MHz),0.51ts (f = 2MHz)• Bit Manipulation, Bit Test Instruction• Protection from System UpsetAddress Trap, Op-Code Trap• Up to 65k Words Address Space• Applicable to 4k or 8k Bytes of EPROM4096 Bytes: HN482732A8192 Bytes: HN482764, HN27C64• TYPE OF PRODUCTSType No. Bus Timing EPROM Type No.HD63P01M1 1MHz HN482732A·30, HN482764·3, HN27C64-30HD63PA01M1* 1.5MHz HN482732A-30, HN482764-3, HN27C64-30HD63PB01 M 1· 2MHz HN482732A-25, HN482764, HN27C64-25• Preliminary• PIN ARRANGEMENTHD63P01Ml, HD63PA01M1, HD63PB01MloNMiOVcc Vee 0OAu Vee 0OA7 Vee 0OAe A. 0OAs At 0OA, A" 0OA3 Vss 0OA2 A,o 0OA, CE 0OAo '07 0000 Oe 000, 05 0002 0, 0OVSS 03 0(Top View)(NOTE)EPROM is not included.630 ~HITACHI

------------------------------------------HD63P01M1.HD63PA01M1.HD63PB01M1• BLOCK DIAGRAM..... -~-+-+P20h+-r-~~P2.h++-...--...... P22h+-4--'I'--.-_ P 2314+-1-1-+ ........ P2 •...... ---P.oJ.----Pl\...... ---P.2J.----P\J...... ---P ••J.----PlsJ.----PI6...... ---P17On Package1--------------IIEPROMHN482732Al(HN482764HN27C6400O.0203I O.1 OsI ~I

HD63P01Ml,HD63PA01Ml)HD63PB01Ml------------------------------------------• ABSOLUTE MAXIMUM RATINGSItem Symbol Value UnitSupply Voltage Vee -0.3 - +7.0 VInput Voltage V in -0.3 - Vee+0.3 VOperating Temperature T opr 0- +70 °cStorage Temperature Tstg -55 -+150 °c(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.But be careful not to apply overvoltage more than maximum ratings to these high input impedance protectioncircuits. To assure the normal operation, we recommend Vin, Vout : VSS :;; (Vin or Vout) ;::;;; Vee.• ELECTRICAL CHARACTERISTICS• DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)Item Symbol Test Conditio'n min typRES, STBY Vee-0.5 -!nput "High" Voltage EXTAL V IH VeexO.7 -Other Inputs 2.0 -Input "Low" Voltage All Inputs V IL -0.3 -Input Leakage Current NMI,IRQ1, RES, STBY Il in I Vi~ =0.5-Vec-0.5V - -Three State (off-state) PlO-P17, P 20 -P 24 ,IiTSII Vin =0.5-Vcc-0 .5V - -Leakage Cu rrentP 30 -P 37 , P 40 -P 47 , IS3Output "High" Voltage All Outputs VOHIOH = -200p.A 2.4 -IOH = -10p.A Vee-0.7 -Output "Low" Voltage All Outputs VOL IOL = 1.6mA - -Input Capacitance All Inputs CinVin=OV, f=1.0MHz,Ta = 25°C- -Standby Current Non Operation lee - 2.0pperating (f=1 MHz**) - 6.0Cu rrent Dissipation *leeSleeping (f=1 MHz*~) - 1.0RAM Stand-By Voltage V RAM 2.0 -• VIH,min = vee-1.OV, VIL max = O.8V, lee of EPROM is not included .•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.values about Current Dissipations at f = x MHz operation are. decided according to the following formula;typo value (f = x MHz) = typo value (f = 1 MHz) x xmax. value If = x MHz) = max. value If = 1 MHz) x x(both the sleeping and operating)maxVeeto.30.81.01.0--0.5512.515.010.02.0-UnitVVp.Ap.AVVVpFp.AmAV632 ~HITACHI

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1• AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)BUS TIMINGTest HD63P01Ml HD63PA01Ml HD63PB01MlItem Symbol Condition min typ max min typ max min typ maxCycle Time tcyc 1 - 10 0.666 -. 10 0.5 - 10Address Strobe Pulse WidthPWASH 220 - 150"High" - - - 110 - -Address Strobe Rise Time tASr - - 20 - - 20 - - 20Address Strobe Fall Time tAst - - 20 - - 20 - - 20Address Strobe Delay Time tASD 60 - - 40 - - 20 - -Enable Rise Time tEr - - 20 - - 20 - - 20Enable Fall Time tEt - - 20 - - 20 - - 20Ellable Pulse Width "High" Level PWEH 450 - - 300 - - 220 - -Enable Pulse Width "Low" Level PWEL 450 - - 300 - - 220 - -Address Strobe to Enable Delayt ASED60 - - 40 - - 20 - -TimetAD1 - - 250 - - 190 - - 160Address Delay TimetAD2 Fig. 1 - - 250 - - 190 - - 160Address Delay Time for Latch tADL Fig. 2 - - 250 - - 190 - - 160Write t Dsw 230 - - 150 - - 100 - -Data Set·up TimeRead tDSR 80 - - 60 - - 50 - -Read tHR 0 - - 0 - - 0 - -Data Hold TimeWrite tHW 20 - - 20 - - 20 - -Address Set-up Time for Latch tASL 60 - - 40 - - 20 - -Address Hold Time for Latch tAHL 30 - - 20 - - 20 - -Address Hold Time tAH 20 - - 20 - - 20 - -Ao - A7 Set-up Time Before E tASM 200 - - 110 - - 60 - -I Non-Multiplexed (tACCN) - - 650 - - 395 - - 270Peripheral ReadBusAccess T-ime I MUltiplexed Bus (tACCM) - - 650 - - 395 - - 270Oscillator stabilization Time tRC Fig_ 10 20 - - 20 - - 20 - -'-Processor Control Set-up Time tpcs Fig. 11 200 - - 200 - - 200 - -UnitIlSnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsnsPERIPHERAL PORT TIMINGPeripheral Data.Set-up TimePeripheral DataHold TimeTest HD63P01Ml HD63PA01Ml HD63PB01MlItem Symbol Conditionmin typ max min typ max min typ maxPort 1,2,3,4 tpDSU Fig. 3 200 - - 200 - - 200 - -Port 1,2,3,4 tpDH Fig. 3 200 - - 200 - - 200 - -Delay Time, Enable PositiveTransition to OS3 Negative tOSD1 Fig. 5 - - 300 - - 300 - - 300TransitionDelay Time, Enable PositiveTransition to OS3 Positive tOS02 Fig_ 5 - - 300 - - 300 - - 300TransitionDelay Time. En.ble Nega-[ Port 1tive Transition to Peri- 2* 3 ,; tpwD Fig. 4 - - 300 - - 300 - - 300pheral Data Valid ' ,Input Strobe Pulse Width tpWIS Fig. 6 200 - - 200 - - 200 - -Input Data Hold Time I Port 3 tlH Fig. 6 150 - - 150 - - 150 - -Input Data Setup Time I Port 3 tiS Fig. 6 0 - - 0 - - 0 - -• Except P21~HITACHIUnitnsnsnsnsnsnsnsns633

HD63P01Ml,HD63PA01Ml,HD63PB01Ml------------------------------------------TIMER, SCI TIMINGItemTimer Input Pulse WidthDelay Time, Enable PositiveTransition to Timer OutSCI Input Clock CycleSCI Input Clock Pulse WidthTest HD63P01M1 HD63PA01M1 HD63PB01M1Symbol Con-Unitdition min typ max min typ max min typ maxtPWT 2.0 - - 2.0 - - 2.0 - - t cvctTOD Fig.7 - - 400 - - 400 - - 400 nstScvc 2.0 - - 2.0 - - 2.0 - - tcyctPWSCK 0.4 - 0.6 0.4 - 0.6 0.4 - 0.6 tScvcMODE PROGRAMMINGItemRES "Low" Pulse WidthMode Programming Set-up TimeMode Programming Hold TimeTest HD63P01M1 HD63PA01M1 HD63PB01M1Symbol Con-Unitdition min typ max min typ max min typ maxPW RSTL 3 - - 3 - - 3 - - tcvetMPs Fig. 8 2 - - 2 - - 2 - - !evetMPH 150 - - 150 - - 150 - - nsAddr ... StrobeIASI2.4VR,W.Ar-A.ISCII IPort41MCU WriteO.-O"A.-A,IPort 31MCU Read0.-0,. A.-A,1P0rt 311-----ltACcMI----I~ NotValidFigure 1 Expanded Multiplexed Bus Timing634~HITACHI

------------------------------------------HD63P01Ml,HD63PA01Ml,HD63PB01MlteyeA. -A, {Port 41R/W (SC"ilrn (SC,)MCUWrite0,-0, ---+----+------6(Po,I3)MCU ReadD.-D,(Po'I3)----4---------------------~2.4VO.BVFigure 2 Expanded Non·Multiplexed Bus TimingrMCUReadr MCUW"IePI"PIO -P zo - PI4P4n - p • .,InputsAll DataPO'I OUlputs _______ J2.4V ,0.1. V.lid".;.;O.B;;.:V~__'Port 3 Non·Latched OperationFigure 3 Port Data Set-up and Hold Times(MCU Read)Note) Port 2; Except P,.Figure 4 Port Data Delay Times(MCU Write)r MCU access of Port 3-Addr,,,BUI053-----....:.p,. - P"'"PUIS• Access matches Output Strobe Select (055 ,. 0, • read;OSS ,. 1, a write)Figure 5 Port 3 Output Strobe Timing(Single Chip Mode)Figure 6 Port 3 Latch Timing(Single Chip Mode)~HITACHI635

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------rImerCoun.e, ____ -' ,"_"';';;';;;';;"';;"',.J '_ __ _P"Ou.pu'1~:,:,;,I~;~:: l.------Cl~----~Figure 8 Mode Programming TimingFigure 7 Timer Output TimingC =90pF for P.lu-P:I1, P.u-P", SCI, SC,=30pF for P",-P." P,u-P"=40pF for ER =12kQ for PIU-PI7, P,o-P", P:\O-P:I1, P.u-p", E, SCI, SC,Figure 9 Bus Timing Test Loads (TTL Load)In.errup.Tes.InternalAdd,ess Bus __ J\.-+--.J'\-,....""'_-.J'-"""'~ ........ ..-'r\.., ..... .J\........ ...,.."-...... .,..,.'-' ...... "-..".."""'~ ...... ~--""'_-~,.......pf'---"-In.ernal ---V-~~--V-~~-_V-...... V--""",....-...,.-'"""~-...,.-'""",_-...,.-'"""~-"'-~,_-~Oa.a Bus --.J\.--.J"-_J\_~"-_.J\._--''''-_-'' ..... _'''-_.J'-_'''-....... .,..,'__J\.,......,,..J'''''"...,..~_,.....I'__J\-In.ernalReadInternalWrite______________ J!Figure 10 Interrupt Sequence'---------::".''''''')\\\\\\\\\\\\\\\\\\\\\\\:; ......... ~\\\\\\\\\\\\\\\\\\\\\\\ANi .. ~\\\J\\\\\\.\\\\\\'~~)\\WMWIi\'\\\\.m~., .....-------------~,~~~l-------Figure 11 Reset Timing636$ HITACHI

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1• FUNCTIONAL PIN DESCRIPTION• Vee, VssThese two. pins are used fo.r po.wer supply and GND. Reco.mmendedpo.wer supply vo.ltage is 5V ±1O%. If the o.peratingvo.ltage o.f the EPROM is 5V ±5%, 5V±5% sho.uld be used.• XTAL, EXTALThese two. pins are co.nnected with parallel reso.nant fundamentalcrystal, AT cut. Fo.r instance, in order to. o.btain thesystem clo.ck IMHz, a 4MHz reso.nant fundamental crystal isused because the devide by 4 circuitry is included. EXT ALaccepts an external clo.ck input o.f duty 50% (±IO%) to. drive,then internal clo.ck is a quarter the frequency o.f an externalclo.ck. External driving frequency will be less than 4 times asmaximum intemal clo.ck. Fo.r external driving, XT AL pinsho.uld be o.pen. An example o.f co.nnectio.n circuit is sho.wn inFig. 12.AT Cut Parallel Resonance CrystalCo = 7 pF maxRs = 60 n maxXTAL~--~------'oEXTAL ~-... ---.(a) Crystal InterfaceXTALEXTAL(b)N.C.C L1z C L2z 10-22pF • 20%(32 - 8MHz)External ClockExternal ClockFigure 12 Connection Circuit• Standby (STBV)This pin is used to. place the MCU in the Standby mo.de.If this go.es to. ."Lo.w" level, the o.sci1latio.n sto.ps, the internalclo.ck is tied to. Vss o.r Vee and the MCU is reset. In o.rder to.retain info.rmatio.n in RAM during standby, write "0" into. RAMenable bit (RAME). RAME is bit 6 o.f the RAM Co.ntro.l Registerat address $0014. This disables the RAM, so. the co.ntents o.fRAM is guaranteed. Fo.r details o.f the standby mo.de, see theStandby sectio.n.• Reset (RES)This input is used to. reset the MCU. RES must be held"Lo.w" fo.r at least 20ms when the po.wer starts up. It sho.uld beno.ted that, befo.re clo.ck generator stabilize, the internal stateand I/O po.rts are uncertain, because MCU can no.t be resetwitho.ut clo.ck. To. reset the MCU during system o.peratio.n, itmust beheld "Lo.w" fo.r at least 3 system clo.ck cycles. Fro.mthe third cycle, all· address buses beco.me "High-impedance"and it co.ntinues while RES'is "Lo.w". If RES go.es to. "High",CPU do.es the fo.llo.wing.(I)(2)(3)I/O Po.rt 2 bits, 2,1,0 are latched into. bits PC2, PCI, PCO o.fpro.gram co.ntro.l register.The co.ntents o.f the two. Start Addresses, $FFFE, $FFFFare bro.ught to. the pro.gram co.unter, fro.m which programstarts (see Table I).The interrupt mask bit is set. In o.rder to. have the CPUreco.gnize the maskable interrupts IRQt and IRQ2, clearit befo.re tho.se are used.• Enable (E)This o.utput pin supplies system clo.ck. Output is a singlephase,TTL co.mpatible and 1/4 o.f the crystal o.scillatio.n frequency.It will drive two. LS TTL Io.ad and 40pF.• Non maskable Interrupt (NMI)When the falling edge o.f the inpu t signal o.f this pin is reco.gnized,NMI sequence starts. The current instructio.n is co.ntinuedto. co.mplete, even if NMI signal is detected. Interruptmask bit in Co.nditio.n Co.de Register has no. effect o.n NMIdetectio.n. In respo.nse to. NMI interrupt, the info.rmatio.n o.fPro.gram Co.unter, Index Register, Accumulato.rs, and Co.nditio.nCo.de Register are sto.red o.n the stack. On co.mpletio.n o.f thissequence, vecto.ring address $FFFC and $FFFD are generatedto. lo.ad the co.ntents to. the program co.unter. Then the CPUbranch to. a no.n maskable interrupt service ro.utine.• I nterrupt Request (I Rat)This level sensitive input requests maskable interrupt sequence.When fRQi go.es to. "Lo.w" , the CPU waits until itco.mpletes the current instructio.n that is being executed. Then,if the interrupt mask bit in Co.ndition Co.de Register is no.t set,CPU begins interrupt sequence; o.therwise, interrupt request isneglected.Once the sequence has started, the info.rmatio.n o.f ProgramCo.unter, Index Register, Accumulato.rs, Co.nditio.n Co.de Registerare sto.red o.n the stack. Then the CPU sets the interruptmask bit so. that no. further maskable interrupts may be respo.nded.Table 1 Interrupt Vectoring memory mapHighestPriorityLowestPriorityVectorMSB LSBFFFEFFEEFFFCFFFAFFFBFFF6FFF4FFF2FFFOFFFFFFEFFFFOFFFBFFF9FFF7FFFSFFF3FFFIInterrupt1mTRAPNMISoh ... ,. Inte"upt ISWIIiRQ, lo,1.S31ICF IT" ... , Input C8Ptu,elOCF (Time, Outout Como-'.TOF ITi,.,.,. Ove,flowlSCI IRORF + ORFE + TOREIAt the end o.f the cycle, the CPU generates 16 bit vecto.ringaddresses indicating memo.ry addresses $FFF8 and $FFF9, andlo.ad the co.ntents to. the Pro.gram Co.unter, then branch to. aninterrupt service ro.utine.The Internal Interrupt will generate signal (IRQ2) which isquite the same as IRQl except that it will use the vecto.r address$FFFO to. $FFF7.When IROiand IRQ2 are generated at the same time, thefo.rmer precede the latter. Interrupt Mask Bit in the co.nditio.nco.de register ,if being set, will keep the bo.th interrupts o.ff.JRQI has no. internal latch. Therefo.re, if IRQt is remo.vedduring suspensio.n, that mQ1 is ignored.$ HITACHI 637

HD63P01M1.HD63PA01M1.HD63PB01M1--------------------On occurrence of Address error or Op-code error, TRAPinterrupt is invoked. This interrupt has priority next to RES.Regardless of the Interrupt Mask Bit condition, the CPU willstart an interrupt sequence. The vector for this interrupt will be$FFEE, $FFEF.The follOWing pins are available only in single chip mode.Table 2 Port and Data Direction Register AddressesPorts Port Addr""Data Di ractionRegist"r AddressI/O Port 1 $0002 $00001/0 Port 2 $0003 $0001I/O Port 3 $0006 $0004I/O Port 4 $0007 $0005• Input Strobe (iD) (SCI)This signal controls IS3 interrupt and the latch of Port 3.When the falling edge of this signal is detected, the flag ofPort 3 Control Status Register is set.For detailed explanation of Port 3 Control Status Register,see the I/O PORT 3 CONTROL STATUS REGISTER section.• Output Strobe (053) (SC2 )This signal is used to send a strobe to an external device,indicating effective data is on the I/O pins. The timing chart forOutput Strobe are shown in Figure 5.The follOWing pins are available for Expanded Modes.• Read/Write (R/W) (SC2)This TTL compatible output signal indicates peripheral andmemory devices whether CPU is in Read ("High"), or in Write("Low")_ The normal stand-by state is Read ("High"). Itsoutput will drive one tTL load and 90pF.• I/O Strobe (lOS) (SCI)In expanded non multiplexed mode 5 of operation, IDSgoes to "Low" onl)' when A9 through Ais are "0" and A8 is"I" . This allows external access up to 256 addresses from$0100 to $OIFF in memory. The timing chart is shown inFigure 2.• Address Strobe (AS) (SCI)In the expanded multiplexed mode, address strobe signalappears at this pin. It is used to latch the lower 8 bits addressesmultiplexed with data at Port 3. The 8-bit latch is controlledby address strobe as shown in Figure 18. Thereby, I/O Port 3can become data bus during E pulse. The timing chart of thissignal is shown in Figure I.Address Strobe (AS) is sent out even if the internal addressarea is accessed.• PORTSThere are four I/O Ports on HD63POIMI MCU (three 8-bitports and one 5-bit port). 2 control pins are connected to oneof the 8-bit port. Each port has an independent write-only datadirection register to program individual I/O pins for input oroutput.*When the bit of associated Data Direction Register is "I".I/O pin is programmed for output, if "0", then programmed foran input.There are four ports: Port I, Port 2, Port 3, and Port 4.Addresses of each port and associated Data Direction Registersare shown in Table 2.* Only one exception is bit I of Port 2 which becomes either adata input or a timer output. It cannot be used as an outputport.RES does not affect I/O port Data Register. Therefore, justafter REs, Data Register is uncertain. Data Direction Registersare reset.638 $ HITACHI• I/O Port 1This is an 8-bit port, each bit being defined individually asinput or outputs by associated Data Direction Register. The8-bit output buffers have three-state capability, maintaining inhigh impedance state when they are used for input. In order tobe read accurately, the voltage on the input lines must be morethan 2.0V for logic" I" and less than 0.8 V for logic "0".These are TTL compatible. After the MCU has been reset, allI/O lines of Port I are configured as inputs in all modes exceptmode I. In all modes except expanded non multiplexed mode(Mode I), Port I is always parallel I/O. In mode 1, Port 1 will beoutput line for lower order address lines (Ao to A7).• I/O Port 2This port has five lines, whose I/O direction depends on itsdata direction register. The 5-bit output buffers have three-statecapability, going high impedance state when used as inputs. Inorder to be read accurately, the voltage on the input lines mustbe more than 2.0V for logic "I" and less than 0.8V for logic"0". After the MCU has been reset, I/O lines are configured asinputs. These pins on Port 2 (pins 10,9,8 of the chip) are usedto program the mode of operation during reset. The values ofthese three pins during reset are latched into the upper 3 bits(bit 7, 6 and 5) of Port 2 Data Register, which is explained inthe MODE SELECTION section.In all modes, Port 2 can be configured as I/O lines. This portalso provides access to the Serial I/O and the Timer. However,note that bit I (P21) is the only pin restricted to data input orTimer output.• I/O Port 3This is an 8-bit port which can be configured as I/O lines, adata bus, or an address bus multiplexed with data bus. Itsfunction depends on hardware operation mode programmed bythe user using 3 bits of Port 2 during Reset. Port 3 as a data busis bi-directional. For an input from peripherals, regular TTLlevel must be supplied, that is greater than 2.0V for a logic" I "and less than 0.8V for a logic "0". This TTL compatible threestatebuffer can drive one TTL load and 90pF. In the expandedModes, data direction register will be inhibited after Reset anddata direction will depend on the state of the R/W line. Functionof Port 3 is shown below.Single Chip Mode (Mode 7)Parallel Inputs/Outputs as programmed by its correspondingData Direction Register.There are two control lines associated with this port in thismode, an input strobe (IS3) and an output strobe (00), bothbeing used for handshaking. They are controlled by I/O Port 3Control/Status Register. Function of these two control lines ofPort 3 are summarized as follows:(1) Port 3 input data can be latched using TS3 (SCt) as ainput strobe signal.(2) US3 can be generated by CPU read or write to Port 3'sdata register.(3) IRQI interrupt can be generated by an 183 fallingedge.

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1Port 3 strobe and latch timing is shown in Figs. 5 and 6respectively.I/O Port 3 Control/Status Register is explained as follows:I/O Port 3 Control/Status Registerport becomes inpu ts. In order to use these pins as addresses,they should be programmed as outputs. When all of the eightbits are not required, the remaining lines can be used as I/Olines (input only).Expanded Multiplexed Mode (Mode 0,2,4): In this mode, Port4 becomes output for upper order address lines (As to A15)regardless of the value of data direction register.Bit ° Not used.Bit 1 Not used.Bit 2 Not used.Bit 3 LATCH ENABLE.Bit 3 is used to control the input latch of Port 3. If the bit isset at "I", the input data on Port 3 is latched by the falling edgeof IS3. The latch is released by the MCV read to Port 3; nownew data can be latched again by IS3 falling edge. Bit 3 iscleared by a reset. If this bit is "0", IS3 does not affect I/OPort 3 latch operation.Bit 4 OSS (Output Strobe Select)This bit identifies the cause of output strobe generation: awrite operation or read operation to I/O Port 3. When the bit iscleared, the strobe will be generated by a read operation to Port3. When the bit is not cleared, the strobe will be generated by awrite operation. Bit 4 is cleared by a reset.Bit 5 Not used.Bit 6 iS3 IROl ENABLE.If this bit is set, IRQl interrupt by IS3 Flag is enabled.Otherwise the interrupt is disabled. The bit is cleared by areset.Bit 71S3 FLAG.Bit 7 is a read-only bit which is set by the falling edge of IS3(SCi). It is cleared by a read of the Control/Status Register followedby a read/write of I/O Port 3. The bit is cleared by rese·t.Expanded Non Multiplexed Mode (mode 1,5)In this mode, Port 3 becomes data bus. (Do '" D7 )Expanded Multiplexed Mode (mode 0, 2, 4, 6)Port 3 becomes both the data bus (Do '" D7) and lower bitsof the address bus (Ao -- A 7). An address strobe output is "High"while the address is on the port.• I/O Port 4This is an 8-bit port that becomes either I/O or addressoutputs depending on the selected operation mode. In orderto be read accurately, the voltage at the input lines must begreater than 2.0V for a logic "I ", and less than 0.8V for a logic"0". For outputs, each line is TTL compatible and can drive oneTTL load and 90pF. Function of Port 4 for each mode isexplained below.Single Chip Mode (Mode 7): Parallel Inputs/Outputs as programmedby its associated data direction register.Expanded Non Multiplexed Mode (Mode 5): In this mode,Port 4 becomes the lower address lines (Ao to A 7) by writing"I "s on the data direction register. After reset, this portbecomes inpu ts. In order to use these pins as addresses, theyshould be programmed as outputs.When all of the eight bits are not required as addresses, theremaining lines can be used as I/O lines (Inputs only).Expanded Non Multiplexed Mode (Mode 1): In this mode, Port4 becomes output for upper order address lines (As to Ai 5)regardless of the value of the direction register.Expanded Multiplexed Mode (Mode 6): In this mode, Port 4becomes the upper address lines (As to A15). After reset, thisThe relation between each mode and I/O Port 1 to 4 issummarized in Table 3.• MODE SELECTIONThe operation mode after the reset must be determined bythe user wiring the 10,9, and 8th pins externally. These threepins are lower order bits; I/O 0, I/O I, I/O 2 of Port 2. They arelatched into the control bits PCO,PCI,PC2 ofI/OPort 2 registerwhen reset goes "High". I/O Port 2 Register is shown below.Port 2 DATA REGISTER.. , 0$00031 pc21 PC' I PCO 11/0 ..11/0311/0211/0, 1110 0 IAn example of external hardware used for Mode Selection isshown in Fig. 13. The HDI4053B is used to separate the peripheraldevice from the MCV during reset. It is necessary ifthe data may conflict between peripheral device and Modegeneration circuit.No mode can be changed through software because the bits5, 6, and 7 of Port 2 Data Register are read-only. The modeselection of the HD63POIMI is shown in Table 4.The HD63POIMI operates in three basic modes: (1) SingleChip Mode; (2) Expanded Multiplexed Mode (compatible withthe HMCS6800 peripheral family), (3) Expanded Non MultiplexedMode (compatible with HMCS6800 peripheral family).• Single Chip Mode (Mode 7)In the Single Chip Mode, all ports will become I/O. This isshown in Figure 15. In this mode, SC 1, SC2 pins are configuredfor control lines of Port 3 and can be used as input strobe (183)and output strobe (ITSj) for data handshaking.• Expanded Multiplexed Mode (Mode 0, 2, 4, 6)In this mode, Port 4 is configured for I/O (inputs only) oraddress lines. The data bus and the lower order address bus aremultiplexed in Port 3 and can be separated by the AddressStrobe.Port 2 is configured for 5 parallel I/O or Serial I/O, or Timer,or any combination thereof. Port I is configured for 8 parallelI/O. In this mode, HD63POIMl is expandable up to 65k words(See Fig. 16).• Expanded Non Multiplexed Mode (Mode 1,5)In this mode, the HD63POlMI can directly addressHMCS6800peripherals with no external logic. In mode 5, Port 3 becomes adata bus. Port 4 becomes Ao to A7 address bus or partialaddress bus and I/O (inputs only). Port 2 is configured for aparallel I/O, Serial I/O, Timer or any combination thereof.Port I is configured as a parallel I/O only.In this mode, HD63POIMI is expandable to 256 locations.In mode I, Port 3 becomes a data bus and Port 1 becomesAo to A7 address bus, and Port 4 becomes As to A15 addressbus.~HITACHI 639

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------In this mode, the HD63P01M1 is expandable to 65k wordswith no extemallogic. (See Fig. 17)• Lower Order Address Bus LatchBecause the data bus is multiplexed with the lower orderVeeaddress bus in Port 3 in the expanded multiplexed mode,address bits must be latched. It requires the 74LS373 Transparentoctal D-type to latch the LSB. Latch connection ofthe HD63POIM1 is shown in Figure 18.p ..RR, R, RIIIIAll\;X.~Z.V. XvX, Z-RESHD63POIMlp .. (PCOIP" (PCOPI) (PC21P"V,PI) Z, HD140538InhNote 1) Figure of Mode 7C2) RC"'Reset ConstantMode??? ~ ];n Irol ---I3) R , =10kn~ SwitchFigure 13 Recommended Circuit for Mode SelectionInh0-A0-B 0--CO-XoX,YoY,ZoZ,Truth TableConlrol InpulOn SWllchSeleclInhibItC 8 A HD1405380 0 0 0 Z. V. X.0 0 0 1 Z. V. X,0 0 1 0 Z. V, X.0 0 1 1 Z. V, X,X 0 1 0 0 Z. Yo Xo0 1 0 1 Z, V. X,0 1 1 0 Z. VI XoZ0 1 1 1 Z. VI XI1 X X XFigure 14 HD140538 Multiplexers/De-MultiplexersVeeEnablePorI 18110 LinesPort 381/0 LinesPort 18110 LinesPort 38 LinesMultiplexedO.t./Address640PorI 481/0 LinesVssPorI 25110 LinesSCIT.merFigure 15 HD63P01M1 MCU Single-Chip ModePort 25110 LinesSCITimer~H!TACH!VssPort 48 AddressLine. orSilO Lines(Inputs Onlv)Figure 16 HD63P01M1 MCU ExpandedMultiplexed Mode

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1VeeVeePorI 18 P.rallelllOPort 38 Dala LinesPOri 1To 8 Address LinesPOri 38 Dala LinesPorI 25 Parallel 110SCITimerVssPort 48 AddressLines or8 I/O Lines(lnpuls OnlvlPort 25 Parallel 110SCITimer(a) Mode 5 (b) Mode 1VssPort 48 AddressLinesFigure 17HD63P01 M1 MCU Expanded Non Multiplexed ModeGNDASPorI 3 [Address/Dalal JGOC0, Q,74LS373D. a.1) A"',_ A,-A,) _D,-D,OutputControl(OC)LLLHFunction TableEnableG 0H HH LL XXxOutPUtaHLa.ZFigure 18 Latch Connection• Summary of Mode and MCU SignalThis section gives a description of the MCU signals for thevarious modes. SCI and SC 2 are signals which vary with the mode.Table 3Feature of each mode and linesPORT 1 PORTMODE2 PORT 3 PORT 4Eight Lines Five Lines Eight Lines Eight LinesSINGLE CHIP (Mode 7) I/O I/O I/O I/OADDRESS BUS(Ao-A7) ADDRESS BUS·EXPANDED MUX I/O I/ODATA BUS (As-Als)(Mode 0, 2,4, 6) (00-07)DATA BUS ADDRESS BUS·EXPANDED (Mode 5) I/O I/O(00-07) (Ao-A7)NON·MUX (Mode 1) ADDRESS BUS DATA BUS ADDRESS BUS(Ao-A7)I/O(Do-D7) (Aa-Als)SCIIS3 (I)AS(O)lOS(O)Not UsedSC2OS3(0)R/W(O)R/W(O)R/WiO)"These lines can be substituted for I/O (Input Only) (except Mode 0, 2, 4).I = Input iS3 = Input Strobe SC = Strobe Controlo = Output OS3 = Output Strobe AS" Address StrobeRNi ,. ReadlWrite ~ = I/O Select~HITACHI641

HD63P01M1,HD63PA01M1,HD63PB01M1--------------------Table 4 Mode Selection SummaryModeC~&I7 H6 H5 H4 H3 L2 'L1 L0 LC~llIHHLLHHLLC~'blHLHLHLHLROM RAMInterruptVectorsBusModeI I I II I I MUXC31I I I NMUXC3)EC1) I E MUX- - - -E(1) I E MUXE(1) I E NMUXI I IC2) MUXOperatingModeSingle ChipMultiplexed/Partial DecodeNon·Multiplexed/Pertial DecodeMultiplexed/RAMNot UsedMultiplexed/RAMNon-MultiplexedMultiplexed TestLEGEND:(NOTES)I - Internal1) I nternal ROM is disabled.E - External2) Reset vector is external for 4 cycles afterMUX - Multiplexed rn goes "high".NMUX - Non·Multiplexed 3) Idle lines of Port 4 address outputs canL - Logic "0"be assigned to Input Port.H - Logic "1"• MemoryMapThe MeU can provide up to 65 k byte address spacedepending on the operating mode. Fig. 19 shows a memory mapfor each operating mode. The first 32 locations of each map arefor the MeU's internal register only, as shown in Table 5.Table 5 Internal Register AreaRegisterPort 1 Date Direction Register····Port 2 Data Direction Register····Port 1 Date RegisterPort 2 Data RegisterPort 3 Data Direction Register····Port 4 Data Direction Register····Port 3 Data RegilierPort 4 Data RegisterTimer Control end Status RegisterCounter CHigh Byte)Counter I Low Byte)Output Compere Register IHigh Byte)Output Compere Register I Low By telInput Capture Register IHigh Byte)Input Capture Register I Low By telPort 3 Control end Status RegisterRate end Mode Control RegisterTransmit/Receive Control and Status RegisterReceiw Data RegisterTransmit Date RegisterRAM Control RegisterReserwdAddren00·0102·0304··05···06··07···0809OAOBoc00OEOF··101112131415·1F• External address in Mode 1.. External address in Modes 0, 1,2,4, 6; cannot beaccessed in Mode 5External addren in Modes 0, 1,2,4•••• 1 '" Output, 0 .. Input642~HITACHI

---------------------HD63P01M1,HD63PA01M1;HD63PB01M1HD63P01M10ModeHD63P01M1 1ModeMultiplexed Test modeNon-Multiplexed/Partial Decode$0000(1)SOOlF$0080$OOFF} Internal Registers}IExternal Memory SpaceInternal RAM$0000$OOlF$0080$OOFFInternal RegistersExternal Memory SpaceInternal RAMExternal Memory SpaceExternal Memory Space$EOOOEPROM$FFFF(2)$FFFF .....___ ~J[NOTES)1) Excludes the following addresses which may beused externally: $04, $05, $06, $07 and $OF.2) Addresses $FFFE and $FFFF are consideredexternal if accessed within 4 cycles after a positiveedge of RES and internal at all other times.3) After 4 CPU cycles, there must be no overlappingof internal and external memory spaces to avoiddriving the data bus with more than one device.4) This mode is the only mode which is used fortesting.[NOTE)Excludes the following addresses which may beused externally; $00, $02, $04, $05, $06, $07and $OF.Ito be continued)Figure 19 HD63P01M1 Memory Maps~HITACHI 643

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------HD63P01M12ModeHD63P01M14ModeHD63P01M15ModeMultiplexed/RAM$0000Internal Registers$OOlFExternal Memory Space$0080Internal RAM$ooFFNon-Multiplexed/Partial Decodesoooo\~ I Internal Regi~t .. r~SoolF~JUnusableS0080} Internal RAM$OOFFSOloo} External Memory SpaceSOl FF L..._ ....._ ...External MemoLY Space$EooO$FFFF '-____ )$FFFFEPROMInternal Interrupt Vectors[NOTE)Excludes the following address whichmay be used externally; $04, $05, $06,$07, $OF.[NOTE)Excludes $04, $06, $OF.These address cannot be usedexternally.(to be contin~edlFigure 19 HD63P01M1 Memory Maps644$ HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1HD63P01M16ModeHD63P01M17ModeMultiplexed/Partial DecodeSingle Chip$0000$OOlF$0080SOOFFInternal RegistersExternal Memory SpaceInternal RAM$OOOO~} Internal Registers$OOlF """""~"""~Unusable$0080} Internal RAM$OOFFExternal Memory Space$EOOO$FFFFIEPROMInternal Interrupt Vectors[NOTE]Excludes the following address which may beused externally: $04, $06, $OF.$EOOO$FFFFIEPROMInternal Interrupt VectorsFigure 19 HD63P01M1 Memory Maps~HITACHI645

HD63P01M1,HD63PA01M1,HD63PB01M1---------------------• PROGRAMMABLE TIMERThe HD63POIMI contains 16-bit programmable timer whichmay be used to make measurement of input waveform. Inaddition to that it can generate an output waveform by itself.For both input and output waveform, the pulse width may varyfrom a few microseconds to several seconds.The timer hardware consists of• an 8-bit control and status register• a 16-bit free running counter• a 16-bit output compare register, and• a i6-bit input capture registerA block diagram of the timer is shown in Figure 20.HD63P01Ml Internal BusBit 1Port 2DDR~-- .. -- -_____ ~ Output InputLevelBitlEdgeBitOPort 2 Port 2Figure 20 Programmable Timer Block Diagram• Free Running Counter ($0009: $OOOA)The key element in the programmable timer is a I6-bit freerunning counter, that is driven by an E (Enable) clock toincrement its values. The counter value will be read out by the'CPU software at any time with no effects on the counter.Reset will clear the counter.When the MSB of this counter is read, the LSB is storedin temporary latch. The data is fetched from this latch by thesubsequent read of LSB. Thus consistent double byte data canbe read from the counter.When the CPU writes arbitrary data to the MSB ($09), thevalue of $FFF8 is being pre-set to the counter ($09, $OA)regardless of the write data value. Then the CPU writes arbitrarydata to the LSB ($OA), the data is set to the "Low" byteof the counter, at the same time, the data preceedingly writtenin the MSB ($09) is set to "High" byte of the counter.When the data is written to this counter, a double bytestore instruction (ex. STD) must be used. If only the MSB ofcounter is written, the counter is set to $FFF8.The counter value written to the counter using the doublebyte store instruction is shown in Figure 21.To write to the counter may disturb serial operations, so itshould be inhibited during using the SCI in internal clock mode.(SAF3 written to the countedFigure 21Counter Write Timing• Output Compare Register ($OOOB:$OOOC)This is a 16-bit read/write register which is used to control anoutput waveform. The contents of this register are constantlybeing compared with current value of the free running counter.When the contents match with the value of the free runningcounter, a flag (OCF) in the timer control/status register(TCSR) is set and the current value of an output level Bit(OLVL) in the TCSR is transferred to Port 2 bit 1. When bit Iof the Port 2 data direction register is "1" (output), the OLVLvalue will appear on the bit I of Port 2. Then, the value of OutputCompare Register and Output level bit may be changedfor the next compare.The output compare register is set to $FFFF during reset.The compare function is inhibited at the cycle of writingto the high byte of the output compare register and at thecycle just after that to ensure valid compare. It is also inhibitedin same manner at writing to the free running counter.In order to write a data to Output Compare Register, adouble byte store instruction (ex. STD) must be used.• Input Capture Register ($OOOD:$OOOE)The input capture register is a 16-bit read-only register usedto hold the current value of free running counter when theproper transition of an external input signal occurs.The input transition change required to trigger the countertransfer is controlled by the input edge bit (IEDG).To allow the external input signal to go in the edge detectunit, the bit of the Data Direction Register corresponding to bito of Port 2 must have been cleared (to zero).To insure input capture in all cases, the width of an inputpulse requires at least 2 Enable cycles.• Timer Control/Status Register (TCSR) ($0008)This is an 8-bit register. All 8 bits are readable and the lower5-bit may be written. The upper 3 bits are read-only, indicatingthe timer status information as is shown below.(I) A proper transition has been detected on the input pin(ICF).(2) A match has been found between the value in the freerunning counter and the output compare register (OCF).(3) When counting up to $0000 (TOF).Each flag has an individual enable bit in TCSR whichdetermines whether or not an interrupt request mayoccur (IRQ2). If the I-bit in Condition Code Register hasbeen cleared, a priority vectored address occurs correspondingto each flag. A description of each bit is as follows.Timer Control I Status RegisterBit 0646 ~HITACHI765432' 0IICF I OCF I TOF I E ICI I EOCI I ETOIIIEDG I Ol vll s0008OLVL (Output Level); When a match is found in thevalue between the counter and the output com-

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1pare register, this bit is transferred to the Port 2bit l. If the DDR corresponding to Port 2 bit 1 isset "1", the value will appear on the ou tpu t pin ofPort 2 bit l.Bit 1 IEDG (Input Edge): This bit control which transitionof an input of Port 2 bit 0 will trigger the datatransfer from the counter to the input captureregister. The DDR corresponding to Port 2 bit 0must be cleared in advance of using this function.When IEDG = 0, trigger takes place on a negativeedge ("High" to "Low" transition). When IEDG =I, trigger takes place on a positive edge ("Low" to"High" transition).Bit 2 ETOI (Enable Timer Overflow Interrupt); When. set,this bit enables TOF interrupt to generate theinterrupt request (IRQ2). When cleared, the interruptis inhibited.Bit 3 EOCI (Enable Output Compare Interrupt); When set,this bit enables OCF interrupt to generate theinterrupt request (1I{Q2). When cleared, the interruptis inhibited.Bit 4 EICI (Enable Input Capture Interrupt); When set, thisbit enables ICF interrupt to generate the interruptrequest (TRQ2). When cleared, the interrupt isinhibited.Bit 5 TOF (Timer Over Flow Flag); This read-only bit is setat the transition of $FFFF to $0000 of thecounter. It is cleared by CPU read of TCSR (WithTOF set) followed by an CPU read of the counter($0009).Bit 6 OCF (OutpUt Compare Flag); This read-only bit is setwhen a match is found in the value between theoutput compare register and the counter. It iscleared by a read of TCSR (with OCF set) followedby an CPU write to the output compareregister ($ooOB or $OOOC).Bit 7 ICF (Input Capture Flag); The read-only bit is set by aproper transition on the input, and is cleared bya read of TCSR (with ICF set) followed by anCPU read of Input Capture Register ($OOOD).Reset will clear each bit of Timer Control and StatusRegister.• SERIAL COMMUNICATION INTERFACEThe HD63POIMI contains a full-duplex asynchronous SerialCommunication Interface (SCI). SCI may select the severalkinds of the data rate. It consists of a transmitter and a receiverwhich operate independently but with the same data formatand the same data rate. Both the transmitter and receiver communicatewith the CPU via the data bus and with the outsideworld through Port 2 bit 2, 3 and 4. Description of hardware,software and register is as follows.• Wak.Up FeatureIn typical multiprocessor applications the software protocolwill usually have the deSignated address at the initial byte of themessage. The purpose of Wake-Up feature is to have the nonselectedMCU neglect the remainder of the message. Thusthe non-selected MCU can inhibit the all further interruptprocess until the next message begins.Wake-Up feature is re-enabled by a ten consecutive "I "swhich indicates an idle transmit line. Therefore software protocolmust put an idle period between the messages and mustprevent it within the message.With this hardware feature, the non-selected MCU is reenabledor ("waked-up") by the next message.• Programmable OptionsThe HD63POIMI has the following programmable features.• data format; standard mark/space (NRZ)• clock source; external or internal• baud rate; one of 4 rates per given E clock frequency or1/8 of external clock• wake-up feature; enabled or disabled• interrupt requests; enabled or masked individually fortransmitter and receiver• clock output; internal clock enabled or disabled to Port2 bit 2• Port 2 (bits 3, 4); dedicated or not dedicated to serialI/O individually• Serial Communication HardwareThe serial communications hardware is controlled by 4registers as shown in Figure 22. The registers include:• an 8-bit control/status register• a 4-bit rate/mode control register (write-only)• an 8-bit read-only receive data register• an 8-bit write-only transmit data registerBesides these 4 registers, Serial I/O utilizes Port 2 bit 3(input) and bit 4 (output). Port 2 bit 2 can be used when anoption is selected for the internal-clock-out or the externalclock-in.• Transmit/Receive Control Status Register (TRCSR)TRCS Register consists of 8 bits which all may be read whileonly bits 0 to 4 may be written. The register is initialized to $20on RES. The bits of the TRCS register are explained below.Transmit I Receive Control Status Register7 6 5 4 oTIE TE WU IADDR10011Bit 0 WU (Wake Up); Set by software and cleared by hardwareon receipt of ten consecutive "I "s. While this bitis "I", RDRF and ORFE flags are not set evenif data are received or errors are detected. Thereforereceived data are ignored. It should be notedthat RE flag must have already been set in advanceofWU flag's set.Bit 1 TE (Transmit Enable); This bit enables transmitter. Whenthis bit is set, bit 4 of Port 2 DDR is also forcedto be set. It remains set even if TE is cleared.Preamble of ten consecutive "I"s is transmittedjust after this bit is set, and then transmitterbecomes ready to send data.If this bit is cleared, the transmitter is disabledand serial I/O affects nothing on Port 2 bit 4.Bit 2 TIE (Transmit Interrupt Enable); When this bit is set,TDRE (bit 5) causes an IRQ2 interrupt. Whencleared TDRE interrupt is masked.Bit 3 RE (Receive Enable); When set, Port 2 bit 3 can be usedas an input of receive regardless of DDR value forthis bit. When cleared, the receiver is disabled.Bit 4 RIE (Receive Interrupt Enable); When this bit is set,RDRF (bit 7) or ORFE (bit 6) cause an rRQ2interrupt. When cleared, this interrupt is masked.~HITACHI 647

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------Bit 5 TORE (Transmit Data Register Empty); When the datais transferred from the Transmit Data Registerto Output Shift Register, this bit is set by hardware.The bit is cleared by reading the status registerfollowed by writing the next new data intothe Transmit Data Register. TORE is initializedto 1 by IrnS".Bit 6 ORFE (Over Run Framing Error); When overrun orframing error occurs (receive only), this bit is setby hardware. Over Run Error occurs if the attemptis made to transfer the new byte to the receivedata register while the RDRF is "1". FramingError occurs when the bit counter is not synchronizedwith the boundary of the byte in the receivingbit stream. When Framing Error is detected,RDRF is not set. Therefore Framing Errorcan be distinguished from Overrun Error. That is,if ORFE is "1" and RDRF is "1", Overrun Erroris detected. Otherwise Framing Error occurs.The bit is cleared by reading the status registerfollowed by reading the receive data register, orbyRES.Bit 7 RORF (Receive Data Register Fu!l); This bit is set byhardware when the data is transferred from thereceive shift register to the receive data register.It is cleared by reading the status register followedby reading the receive data register, or by RES.II CCt I CCO I SSI I SSO ,SIOBit 7 Rate and Mode Control Register Bit 0Transmit/Receive Control and StatuI RegisterPo," 7Receive Shift RegisterClock 10Bit 16.-~------aI ... ----E2~------------------Transmit Data RegisterFigure 22 Serial I/O Register65 4 2 0CCl I CCO I 551 I 550 AoOR : $0010Transfer Rate / Mode Control RegisterTable 6 SCI Bit Timesand Transfer RatesSS1 : SSO0 00 11 01 1XTAL 2.4576 MHz 4.0 MHz 4.91S2MHzE 614.4 kHz 1.0MHz 1.2288MHzE+ 16 26 Ils/38,400 Baud 16 Ils/62,SOO Baud 13 I's/76.8008audE+ 128 2081ls/4.800 Baud 128 Ils17812.5 Baud 104.21'$/ 9.6008audE + 1024 1.67ms/600 Baud 1.024ms/976.6 Baud 833.31'5/ 1.2008audE + 4096 6.67ms/150 Baud 4.096msl244.1 Baud 3.333ms/ 3008aud648$ HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1Table 7 SCI Format and Clock Source ControlCC1:CCO Format Clock Source0 0 - -0 1 NRZ .ternal1 0 NRZ Internal1 1 NRZ External- Clock output is available regardless of values for bits RE and TE .•• Bit 3 is used for serial input if RE = "'" in TRCS.Bit 4 is used for serial output if TE = "'" in TRCS ... * This pin can be used as I/O port.Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4- - -Not Used *** -- ..Output- .. ..Input .. ..• Transfer rate/Mode Control Register (RMCR)The register controls the following serial I/O functions:-Bauds rate -data format - clock source-Port 2 bit 2 featureIt is 4-bit write-only register, cleared by RES. The 4 bits areconsidered as a pair of 2-bit fields. The lower 2 bits control thebit rate of internal clock while the upper 2 bits control theformat and the clock select logic.Bit 0 SSO}Bit 1 SS 1 Speed SelectThese bits select the Baud rate for the internal clock. Therates selectable are function of E clock frequency of the CPU.Table 6 lists the available Baud Rates.Bit2 CCO}Bit 3 CCI Clock Control/Format SelectThey control the data format and the clock select logic.Table 7 defines the bit field.• Internally Generated ClockIf the user wishes to use externally an internal clock of theserial I/O, the following requirements should be noted.-CCl, CCO must be set to "10".-The maximum clock rate must be E/16.-The clock rate is equal to the bit rate.-The values of RE and TE have no effect.• Externally Generated ClockIf the user wish to supply an external clock to the SerialI/O, the following requirements should be noted.-The CCl, CCO must be set to "11" (See Table 7).- The external clock must be set to 8 times of the desiredbaud rate.- The maximum external clock frequency is E/2 clock.• Serial OperationsThe serial I/O hardware must be initialized by the softwarebefore operation. The sequence will be normally as follows.- Writing the desired operation control bits of the Rate andMode Control Register.- Writing the desired operation control bits of the TRCSregister.If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may bekept set. When TE, RE bit are cleared during SCI operation,and subsequently set again, it should be noted that TE, REmust be kept "0" for at least one bit time of the current baudrate. If TE, RE are set again within one bit time, there may bethe case where the initializing of internal function for transmitterand receiver does not take place correctly.• Transmit OperationData transmission is enabled by the TE bit in the TRCSregister. When set, the output of the transmit shift registeris connected with Port 2 bit 4 which is unconditionally configuredas an output.After lffiS, the user should initialize both the RMC registerand the TRCS register for desired operation. Setting the TE bitcauses a transmission of ten-bit preamble of" 1 "s. Following thepreamble, internal synchronization is established and the transmitteris ready to operate. Then either of the following statesexists.(1) If the transmit data register is empty (TDRE = 1), theconsecutive "1 "s are transmitted indicating an idlestates.(2) If the data has b.:en loaded into the Transmit DataRegister (TDRE = 0), it is transferred to the outputshift register and data transmission begins.During the data transfer, the start bit ("0") is first transferred.Next the 8-bit data (beginning at bit 0) and finally thestop bit ("1 "). When the contents of the Transmit Data Registeris transferred to the output shift register, the hardware sets theTDRE flag bit: If the CPU fails to respond to the flag withinthe proper time, TDRE is kept set and then a continuous stringof 1 's is sent until the data is supplied to the data register.• Receive OperationThe receive operation is enabled by the RE bit. The serialinput is connected with Port ~ bit 3. The receiver operationis determined by the contents of the TRCS and RMC register.The received bit stream is synchronized by the first "0" (startbit). During lO-bit time, the data is strobed approximately atthe center of each bit. If the tenth bit is not "1" (stop bit),the system assumes a framing error and the ORFE is set.If the tenth bit is "1", the data is transferred to the receivedata register, and the RDRF flag is set. If the tenth bit of thenext data is received and still RDRF is preserved set, thenORFE is set indicating that an overrun error has occurred.After the CPU read of the status register as a response toRDRF flag or OR FE flag, followed by the CPU read of thereceive data register, RDRF or ORFE will be cleared.• RAM CONTROL REGISTERThe register assigned to the address $0014 gives a statusinformation about standby RAM.RAM Control RegisterBit 0 Not used.Bit 1 Not used.Bit 2 Not used.$ HITACHI 649o

HD63P01Ml,HD63PA01Ml,HD63PB01Ml------------------------------------------Bit 3 Not ul8d.Bit 4 Not ul8d.Bit 5 Not ul8d.Bit 6 RAM Enable.Using this control bit, the user can disable the RAM. RAMEnable bit is set on the positive edge of trnS and RAM isenabled. The program can write "1" or "0". If RAME iscleared, the RAM address becomes external address and theCPU may read the data from the outside memory.Bit 7 Standby Bit1lIls bit can be read or written by the user program. It iscleared when the Vee voltage is removed. Normally this bitis set by the program before going into stand-by mode. Whenthe CPU recovers from stand-by mode, this bit !hould bechecked. If it is "1 ", the data of the RAM is retained duringstand-by and it is valid.• GENERAL DESCRIPTION OF INSTRUCTION SETThe HD63POIMI has an upward object code compatible withthe HD6801 to utilize all jnstruction sets of the HMCS6800.The execution time of the key instruction is reduced to increasethe system through-put. In addition, the bit operation instruction,the exchange instruction between the index and theaccumulator, the sleep instruction are added. This sectiondescribes:• CPU programming model (See Fig. 23)- Addressing modes• Accumulator and memory manipulation instructions (SeeTable 8)- New instructions-Index register and stack manipulation instructions (SeeTable 9)-Jump and branch instructions (See Table 10)• Condition code register manipulation instructions (SeeTable II)-Op-code map (See Table 12)• Cycle-by-Cycle Operation (See Table 13)• CPU Programming ModelThe programming model for the HD63POIMI is shown in Figure23. The double accumulator is physically the same as theaccumulator A concatenated with the accumulator B, so thatthe contents of A and B is changed with executing operation ofan accumulator D.t ----"':.. ---iJ~ __ --!!. - - - - ~18'Bit A~cumulator$ A and B15 DOOr 16·B,t Double Accumulator D• CPU Addressing ModesThe HD63POIMI has seven address modes which depend onboth of the instruction type and the code. The address mode forevery instruction is shown along with execution time given interms of machine cycles (Table 8 to 12). When the clockfrequency is 4 MHz, the machine cycles will be microseconds.Accumulator (ACCX) AddressingOnly the accumulator (A or B) is addressed. Either accumulatorA or B is specified by one-byte instructions.I mmediate AddressingIn this mode, the operand is stored in the second byte of theinstruction except that the operand in LOS and LDX, etc arestored in the second and the third byte. These are two orthree-byte instructions.Direct AddressingIn this mod~, the second byte of instruction indicates theaddress where the opelJnd is stored. Direct addressing allowsthe user to directly address the lowest 256 Bytes in the machinelocations zero through 255. Improved execution times areachieved by storing data in these locations. For systemconfiguration, it is recommended that these locations should beRAM and be utilized preferably for user's data realm. These aretwo-byte instructions except the AIM, OIM, ElM and TIMwhich have three- byte.Extended Addre .. ingIn this mode, the second byte indicates the upper 8 bitsaddresses where the operand is stored, while the third byteindicates the lower 8 bits. This is an absolute address inmemory. These are three-byte instructions.I ndexed AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the Index Register. For each of AIM, OIM, ElMand TIM instructions, the contents of the third byte are addedto the lower 8 bits in the Index Register. In addition, theresulting "carry" is added to the upper 8 bits in the IndexRegister. The result is used for addressing memory. Because themodified address is held in the Temporary Address Register,there is no change to the Index Register. These are two-byteinstructions but AIM, OIM, ElM, TIM have three-byte.Implied AddressingIn this mode, the instruction itself gives the address; stackpointer, index register, etc. These are t -byte instructions.Relative AddressingIn this mode, the contents of the second byte is added to thelower 8 bits in the program counter. The resulting carry orborrow is added to the upper 8 bits. This helps the user toaddress the data within a range of -126 to + 129 bytes of thecurrent execution instruction. These are two-byte instructions.1 15X 01 Index Register IX)1 15SPo I Stack Pointer ISP)1 15 PC01 Program Counter IPC)7 0~1 H I N Z V C Condition Code Register ICCR)Carry/Borrow from MSBOverflowZeroNegativeInterruptHalf Carry IF rom Bit 3)Figure 23 CPU Programming Model650 ~HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1Table 8 Accumulator, Memory Manipulation InstructionsCondition CodeAddressing ModesRegisterOperetions Mnemonic BooleanlIMMED DIAECT INDEX EXTEND IMPLIED Arithmetic Operation5 4 3 2 1 0OP - # OP - # OP - # OP - - # OP # H I N Z V CAdd ADDA BB 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-A I I I I IADDB C8 2 2 08 3 2 E8 4 2 F8 4 3 8+M-B I I I I IAdd Doable ADDD C3 3 3 03 4 2 E3 5 2 F3 5 3 A:8+M:M+l-A:8· I I I IAdd Accumulators ABA 18 1 1 A+B- A I I I I IAdd With Carry ADCA 89 2 2 99 3 2 A9 4 2 89 4 3 A+M+C-A I : I I IADCB C9 2 2 09 3 2 E9 4 2 F9 4 3 8+M+C-8 I I I I IAND ANDA 84 2 2 94 3 2 A4 4 2 84 4 3 A'M-A I I AAND8 C4 2 2 04 3 2 E4 4 2 F4 4 3 8·M-8 I I A 8it Test 81TA 85 2 2 95 3 2 A5 4 2 85 4 3 A·M J I A 81T 8 C5 2 2 05 3 2 E5 4 2 F5 4 3 8·M ·t I A Clear CLA 6F 5 2 7F 5 3 oo-M A S A ACLAA 4F 1 1 oo-A A S A ACLA8 5F I 1 00-8 A S A ACompare CMPA 81 2 2 91 3 2 AI 4 2 81 4 3 A-M t I I ICMPB Cl 2 2 01 3 ,2 El 4 2 Fl 4 3 8-M I I I ICompareCIlA 11 1 1 A-8I I I IAccumulators Compliment, l's COM 63 6 2 73 6 3 M-M I I A SCOMA 43 1 1 A-A I I A SCOM8 53 1 1 8 -8 I I A SComplement, 2's NEG 60 6 2 70 6 3 OO-M-M : t CD~I Negate) NEGA 40 1 1 OO-A-A I I (i) (2)NEG8 50 I 1 oo-8-B : : (i) (~Converts binary add of 8CDDecimal Adjust, A DAA 19 2 1characters into 8CD format: : t

HD63P01M1,HD63PA01M1,HD63PB01M1---------------------Table 8 Accumulator, Memory Manipulation InstructionsOperationsMnemonicCondition CodeAddrening ModesRegisterBoolean/IMMED DIRECT INDEX EXTEND IMPLIEDArithmetic Operation5 4 3 2 1 0op - # OP - # OP - # op - # OP- # H I N Z V CShift Left ASL 68 6 2 78 6 3M} _ · · , , @'ArithmeticASLA 48 1 1 A '?1lllllllt--o· · , , (ID'ASLB 58 1 1 • b7 bO· · , • I> •Double Shift1?1 ~~ ~ ~~. 1-0 ,~ASLD 05 1 1 • •=} CCI IITii I r9 , (§ ASRA 47 1 1·· • , ~,• b' bOASRB 57 1 1Left, Arithmetic A7 AO 17 10Shift Right ASR 67 6 2 77 6 3Arithmetic• , 6 Shift Right LSR 64 6 2 74 6 3 M} _ R Cil ,LogicalLSRA 44 1 1 Ao~llllllll""9 R, 61 b7 bO •LSRB 54 1 1R , k6 ,Double Shift- LSRD 04 1 1 0-17 ACCA:'.~CC' IO~ R ,~,Right LogicalStore STAA 97 3 2 A7 4 2 B7 4 3 A ... M , RAccumulatorSTA8 07 3 2 E7 4 2 F7 4 3 B ... M • RStore DoubleA ... MSTD 00.4 2 ED 5 2 FO 5 3· , Accumulator B ... M+ 1• ·R Subtract SUBA 80 2 2 90 3 2 AO 4 2 BO 4 3 A-M ... A·• , • ,SUBB CO 2 2 00 3 2 EO 4 2 FO 4 3 B -M ... B Double Subtract SUBD 83 3 3 93 4 2 A3 5 2 B3 5 3 A:B-M:M+1"'A:B • •SubtractSBA 10 1 1 A-B"'AAccumulators Subtract S8CA 82 2 2 92 3 2 A2 4 2 82 4 3 A-M-C"'A · , With CarryS8C8 C2 2 2 02 3 2 E2 4 2 F2 4 3 8-M-C"'8 •, ,Transfer TAB 16 1 1 A ... 8• • , RAccumulatorsT8A 17 1 1 8 ... A S R Test Zero or TST 60 4 2 70 4 3 M-OO R · RMinusTSTA 40 1 1 A -00 , R RTSTB 50 1 1 8 - 00·· , S. R RAnd Immediate AIM 71 6 3 61 7 3 M·IMM .... M t t R OR Immediate OIM 72 6 3 62 7 3 M+IMM .... M t t R EOR Immediate ElM 75 6 3 65 7 3 MEf)IMM .... M t 1 RTlStlmmediate TIM 78 4 3 68 5 3 M·IMM•• • t t R •Note) Condition Code Register will be explained in Note of Table 11.• New InstructionsIn addition to the HD6801 Instruction Set, the HD63POIMIhas the following new instructions:AIM----(M)· (lMM)-+(M)Evaluates the AND of the immediate data and thememory, places the result in the memory.OIM---- (M) + (lMM) -+ (M)Evaluates the OR of the immediate data and thememory, places the result in the memory.EIM- - --(M) (!) (IMM) -+ (M)Evaluates the EOR of the immediate data and thecontents of memory, places the result in memory.TIM----(M)· (lMM)Evaluates the AND of the immediate data and thememory, changes the flag of associated condition coderegisterEach instruction has three bytes; the fust is op-code, thesecond is immediate data, the third is address modifier.XGDX--(ACCD) ~ (IX)Exchanges the contents of accumulator and the indexregister.SLP----The MPU is brought to the sleep mode. For sleepmode, see the "sleep mode" section.652 ~HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1Table 9 Index Register, Stack Manipulation InstructionsPointer OperationsMnemonicAcldressing ModesCondition CodeBooleanlAegisterIMMED. DIRECT INDEX EXTEND IMPLIED Arithmetic Operation 5 4 3 2 1 0OP - - - - - # OP # OP # OP # OP # H I N Z V C• ~· ·· Compare Index Reg CPX 8C 3 3 9C 4 2 AC 5 2 BC 5 3 'X-M:M+lDecrement Index Reg DEX 09 1 1 X-l-XDecrement Stack Pntr DES 34 1 1 SP-l-SP·Increment Index Reg INX OB 1 1 X + 1- X·Increment Stack Pntr INS 31 1 1 sP+l-SP·load Index Reg lOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M-XH.IM+1I-XL·load Stack Pntr lOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M- sPH, IM+1I-SP LStore Index Reg STX OF 4 2 EF 5 2 FF 5 3 XH - M, XL - 1M + 11 ·Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH - M. SPL - IM+ 11Index Reg - Stack Pntr TXS 35 1 1 X-l-sP ·Stack Pntr - Index Reg TSX 30 1 1 SP+1-X·Add ABX 3A 1 1 B+X~ X·Push Data PSHX 3C 5 1 XL - Mil>' SP - 1 - SP.·XH - Mil>' SP - 1 - SPPull Data PUlX 38 4 1 SP+l-SP,MII>-XHSP + 1 - SP, Mil> - XL ·· t ~ t ~~ ···

HD63P01M1,HD63PA01M1,HD63PB01M1---------------------Table 11Condition Code Register Manipulation Instructions"ddreaingModetCondition Code RegisterOperMionl Mnemonic IMPLIED Boolean ()peration 5 4 3 2 1 0OP H-I N Z V CC .... Carry ClC OC 1 " 1 O-C RClear Interrupt Mask CLI OE 1 1 0-1 R CleerOwrflow ClV OA 1 1 O-V • R Set Carry SEC 00 1 1 l-C SSet Interrupt Mask SEI OF 1 1 1-1 S · Set Owrflow SEV OB 1 1 1-V S · · · ·Accumulator A - CCR TAP 06 1 1 A- CCR --@---CCR - Accumulator A TPA 07 1 1 CCR-A·· · · · ·[NOTE 11 Condition Code Register Notes: (Bit set if test is true and cleared otherwise)CD (Bit V) Test: Result = 10000000?@ (Bit C) Test: Result" OOOOOOOO?@ (Bit C) Test: BCD Character of high-order byte greater than 9? (Not cleared if previously set)@ (Bit V) Test: Operand = 10000000 prior to execution?@ (Bit V) Test: Operand = 01111111 prior to execution?@ (Bit V) Test: Set equal to NIBC=1 after the execution of instructions

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1• Instruction Execution CyclesIn the HMCS6800 series, the execution cycle of each instructionis the number of cycles between the start of the currentinstruction fetch and just before the start of the subsequentinstruction fetch.The HD63POIMI uses a mechanism of the pipeline controlfor the instruction fetch and the subsequent instructionfetch is performed during the current instruction beingexe-cuted.Therefore, the method to count instruction cycles used inthe HMCS6800 series cannot be applied to the instruction cyclessuch as MULT, PULL, DAA and XGDX in the HD63POIMl.Table 13 provides the information about the rellillonshipamong each data on the Address Bus, Data Bus, and R/W statusin cycle-by-cyc1e basis dUring the execution of each instruction.Address Mode &InstructionsTable 13 Cycle-by-Cycle OperationAddress BusData BusIMMEDIATEADC ADDAND BITCMP EORLOA ORASBC SUBADDD CPXLDD LOSLOX SUBD21213 23Op Code Address+ 1 1 Operand DataOp Code Address+2 1 Next Op CodeOp Code Address + 1 1 Operand Data (MSB)Op Code Address+2 1 Operand Data (LSB)Op Code Address+3 1 Next Op CodeDIRECTADCANDCMPLOASSCSTAADDDLDDLOXSTDSTXJSRTIMAIMOIMADDBITEORORASUBCPXLOSSUBDSTSElM123 313 231243412434125 345124341236456Op Code Address+ 1 1 Address of Operand (LSB)Address of Operand 1 Operand DataOp Code Address+2 1 Next Op CodeOp Code Address + 1 1 Destination AddressDestination Address 0 Accumulator DataOp Code Address+2 1 Next Op CodeOp Code Address+ 1 1 Address of Operand (LSB)Address of Operand 1 Operand Data (MSB)Address of Operand + 1 1 Operand Data (LSB)Op Code Address+2 1 Next Op CodeOp Code Address+ 1 1 Destination Address (LSB)Destination Address 0 Register Data (MSB)Destination Address + 1 0 Register Data (LSB)Op Code Address+2 1 Next Op CodeOp Code Address + 1 1 Jump Address (LSB)FFFF 1 Restart Address (LSB)Stack Pointer 0 Return Address (LSB)Stack Pointer-1 0 Return Address (MSB)Jump Address 1 First Subroutine Op CodeOp Code Address+ 1 1 Immediate DataOp Code Address + 2 1 Address of Operand (LSB)Address of Operand 1 Operand DataOp Code Address+3 1 Next Op CodeOp Code Address+ 1 1 Immediate DataOp Code Address + 2 1 Address of Operand (LSB)Address of Operand 1 Operand DataFFFF 1 Restart Address (LSB)Address of Operand 0 New Operand DataOp Code Address+3 1 Next Op Code- Continued -~HITACHI 655

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------Table 13 Cycle-by-Cycle Operation (Continued)Address Mode &InstructionsAddress BusData BusINDEXEDJMPADCANDCMPLOASBCTSTSTAADDDCPXLOSSUBDSTDSTXJSRASLCOMINCNEGRORTIMCLRAIMOIMADDBITEORORASUBLDDLOXSTSASRDECLSRROLElM34455565571 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 Jump Address 1 First Op Code of Jump Routine1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data4 Op Code Address+2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 0 Accumulator Data4 Op Code Address + 2 1 Next Op Code1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data (MSB)4 IX + Offset+ 1 1 Operand Data (LSB)5 Op Code Address+2 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 0 Register Data (MSB)4 IX + Offset+ 1 0 Register Data (LSB)5 Op Code Address + 2 1 Next Op Code1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer-1 0 Return Address (MSB)5 IX + Offset 1 First Subroutine Op Code1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data4 FFFF 1 Restart Address (LSB)5 IX + Offset 0 New Operand Data6 Op Code Address + 1 1 Next Op Code1 Op Code Address+ 1 1 Immediate Data2 Op Code Address + 2 1 Offset3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 Op Code Address + 3 1 Next Op Code1 Op Code Address + 1 1 Offset2 FFFF 1 Restart Address (LSB)3 IX + Offset 1 Operand Data4 IX + Offset 0 005 Op Code Address + 2 1 Next Op Code1 Op Code Address + 1 1 Immediate Data2 Op Code Address + 2 1 Offset3 FFFF 1 Restart Address (LSB)4 IX + Offset 1 Operand Data5 FFFF 1 Restart Address (LSB)6 IX + Offset 0 New Operand Data7 Op Code Address + 3 1 Next Op Code- Continued -656~HITACHI

•------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusEXTENDJMPADC ADD TSTAND BITCMP EORLOA ORASBC SUBSTAADDDCPXLOSSUBDSTDSTXJSRASLCOMINCNEGRORCLRLDDLOXSTSASRDECLSRROLI3445i 566I 5I1 Op Code Address+ 1 1 Jump Address (MSB)2 Op Code Address+2 1 Jump Address (LSB)3 Jump Address 1 Next Op Code1 Op Code Address+ 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 Op Code Address+3 1 Next Op Code1 Op Code Address + 1 1 Destination Address (MSB)2 Op Code Address+2 1 Destination Address (LSB)3 Destination Address 0 Accumulator Data4 Op Code Address+3 1 Next Op Code1 Op Code Address+ 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data (MSB)4 Address of Operand + 1 1 Operand Data (LSB)5 Op Code Address+3 1 Next Op Code1 Op Code Address + 1 1 Destination Address (MSB)2 Op Code Address+2 1 Destination Address (LSB)3 Destination Address 0 Register Data (MSB)4 Destination Address+ 1 0 Register Data (LSB)5 Op Code Address + 3 1 Next Op Code1 Op Code Address+ 1 1 Jump Address (MSB)2 Op Code Address+2 1 Jump Address (LSB)3 FFFF 1 Restart Address (LSB)4 Stack Pointer 0 Return Address (LSB)5 Stack Pointer-l 0 Return Address (MSB)6 Jump Address 1 First Subroutine Op Code1 Op Code Address + 1 1 Address of Operand (MSB)2 Op Code Address+2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 FFFF 1 Restart Address (LSB)5 Address of Operand 0 New Operand Data6 Op Code Address+3 1 Next Op Code1 Op Code Address + 1 1 Address of Operand (MSB)2 Op Code Address + 2 1 Address of Operand (LSB)3 Address of Operand 1 Operand Data4 Address of Operand 0 005 Op Code Address+3 1 Next Op Code- Continued -~HITACHI 657

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------Address Mode &.InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusIMPLIEDABA ABX 1 Op Code Address + 1 1 Next Op CodeASL ASLDASR CBACLC CLICLR CLVCOM DECDES DEXINC INSINX LSR 1LSRD ROLROR NOPSBA SECSEI SEVTAB TAPTBA TPATST TSXTXSDAA XGDX1 Op Code Address + 1 1 Next Op Code22 FFFF 1 Restart Address (LSB)PULA PULB 1 Op Code Address + 1 1 Next Op Code3 2 FFFF 1 Restart Address (LSB)3 Stack Pointer + 1 1 Data from StackPSHA PSHB 1 Op Code Address + 1 1 Next Op Code42 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Accumulator Data4 Op Code Address+ 1 1 Next Op CodePULX 1 Op Code Address+ 1 1 Next Op Code42 FFFF 1 Restart Address (LSB)3 Stack Pointer + 1 1 Data from Stack (MSB)4 Stack Pointer + 2 1 Data from Stack (LSB)PSHX 1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)5 3 Stack Pointer 0 Index Register (LSB)4 Stack Pointer-1 0 Index Register (MSB)5 Op Code Address + 1 1 Next Op CodeRTS 1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)5 3 Stack Pointer + 1 1 Return Address (MSB)4 Stack Pointer+2 1 Return Address (LSB)5 Return Address 1 First Op Code of Return RoutineMUL 1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 FFFF 1 Restart Address (LSB)7 4 FFFF 1 Restart Address (LSB)5 FFFF 1 Restart Address (LSB)6 FFFF 1 Restart Address (LSB)7 FFFF 1 Restart Address (LSB)- Continued -658 ~HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation I (Continued)Address BusData BusIMPLIEDWAIRTISWISLP9101241 Op Code Address+ 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (lSB)4 Stack Pointer-1 0 Return Address (MSB)5 Stack Pointer - 2 0 Index Register (LSB)6 Stack Pointer-3 0 Index Register (MSB)7 Stack Pointer-4 0 Accumulator. A8 Stack Pointer-5 0 Accumulator B9 Stack Pointer-6 0 Conditional Code Register1 Op Code Address+ 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer + 1 1 Conditional Code Register4 Stack Pointer + 2 1 Accumulator B5 Stack Pointer + 3 1 Accumulator A6 Stack Pointer + 4 1 Index Register (MSB)7 Stack Pointer + 5 1 Index Register (LSB)8 Stack Pointer + 6 1 Return Address (MSB)9 Stack Pointer + 7 1 Return Address (LSB)10 Return Address 1 First Op Code of Return Routine1 Op Code Address + 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer - 1 0 Return Address (MSB)5 Stack Pointer - 2 0 Index Register (lSB)6 Stack Pointer - 3 0 Index Register (MSB)7 Stack Pointer - 4 0 Accumulator A8 Stack Pointer - 5 0 Accumulator B9 Stack Pointer - 6 0 Conditional Code Register10 Vector Address FFFA 1 Address of SWI Routine (MSB)11 I Vector Address FFFB 1 Address of SWI Routine (LSB)12 Address of SWI Routine 1 First Op Code of SWI Routine1 Op Code Address+ 1 1 Next Op Code2 FFFF 1 Restart Address (LSB)FFF~High Impedance-Non MPX Mod erAddress Bus -MPX ModeSleep13 FFFF Restart Address (LSB)4 Op Code Address + 1 Next Op Code1- Continued -~HITACHI 659

HD63P01Ml,HD63PA01Ml,HD63PB01Ml------------------------------------------Address Mode &InstructionsTable 13 Cycle-by-Cycle Operation (Continued)Address BusData BusRELATIVEBCC BCS 1 Op Code Address + 1, Branch OffsetBEQ BGE 3 2 FFFF 1 Restart Address (LSB)BGT BHI{BranCh Address·· .... Test=·' ..First Op Code of Branch Routine31BLE BLS Op Code Address+ '···Test=·O" Next Op CodeBLT BMTBNE BPLBRA BRNBVC BVSBSR 1 Op Code Address+ 1 1 Offset2 FFFF 1 Restart Address (LSB)5 3 Stack Pointer 0 Return Address (LSB)4 Stack Pointer-1 0 Return Address (MSB)5 Branch Address 1 First Op Code of Subroutine• LOW POWER CONSUMPTION MODEThe HD63POIMI has two low power consumption modes;sleep and standby mode.• SleepModeOn execution of SLP instruction, the MeU is brought to thesleep mode. In the sleep mode, the CPU sleeps (the CPU clockbecomes inactive), but the contents of the registers in the CPUare retained. In this mode, the peripherals of CPU will remainactive. So the operations such as transmit and receive of theSCI data and counter may keep in operation. In this mode,the power consumption is reduced to about 1/6 the value ofa normal operation.The esca~rom this mode can be done by interrupt, RES,STBY. The RES resets the MCU and the STBY brings it into thestandby mode (This will be mentioned later). When interrupt isrequested to the CPU and accepted, the sleep mode is released,then the CPU is brought in the operation mode and jumps tothe interrupt routine. When the CPU has masked the interruptafter recovering from the sleep mode, the next instruction ofSLP starts to execute. However, in such a case that the timerinterrupt is inhibited on the timer side, the sleep mode cannotbe released due to the absence of the interrupt request to theCPU.This sleep mode is available to reduce an average powerconsumption in the applications of the HD63PO 1M 1 which maynot be always running .• Standby ModeBringing "STBY "Low", the CPU becomes reset and allclocks of the HD63POIM I become inactive. It goes into thestandby mode. This mode remarkably reduces the power consumptionsof the HD63POIMI.In the standby mode, if the HD63POIMI is continuouslysupplied with power, the contents of RAM is retained. Thestandby mode should escape by the reset start. The followingis the typical application of this mode.First, NMl routine stacks the MCU's internal information andthe contents of SP in RAM, disables RAME bit of RAM controlregister, sets the Standby bit, and then goes into the standbymode. If the Standby bit keeps set on reset start, it meansthat the power has been kept during standby mode and thecontents of RAM is normally guaranteed. The system recoverymay be possible by returning SP and bringing into the conditionbefore the standby mode has started. The timing relation foreach line in this application is shown in Figure 24.Vee

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1• ERROR PROCESSINGWhen the HD63POIMl fetches an undefined instruction orfetches an instruction from unusable memory area, it generatesthe highest priority internal interrupt, that may protect fromsystem upset due to noise or a program error.• Op-Code ErrorFetching an undefined op-code,the HD63POIMI will stack theCPU register as in the case of a normal interrupt and vector tothe TRAP (SFFEE, SFFEF), that has a second highest priority(RES is the highest).• Addr ... ErrorWhen an instruction is fetched from other than a residentROM, RAM, or an external memory area, the CPU starts thesame interrupt as op.code error. In the case which the instruc·tion is fetched from external memory area and that area is notusable, the address error cannot be detected.The addresses which cause address error in particular modeare shown in Table 14.This feature is applicable only to the instruction fetch, not tonormal read/write of data accessing.Table 14 Address ErrorMode 0 1 2,4 5 6 7$0000 $0000 $0000 $0000 $0000 $0000\ \ \ \ \ \Address $GOIF $GOIF $GOIF $G07F $GOIF $G07F$0200 $0100\ \$EFFFSEFFFSystem Flow chart ofHD63POIMI is shown in Fig. 25.Transitions among the active mode, sleep mode, standbymode and reset are shown in Fig. 26.Figures 27, 28, 29 and 30 shows a system configuration.~HITACHI 661

HD63P01M1,HD63PA01M1,HD63PB01M1--------------------STACKPCl~MSPPCH ~MSP-lIXl~MSP-2IXH ~MSP-3ACCA -< MSP-4ACCB ·MSP-5CCR ~ MSP-6Figure 25 HD63P01Ml System Flow Chart662 ~HITACHI

----------------------HD63P01 M 1 ,HD63PA01 M 1 ,HD63PB01 M 1Figure 26 Transitions among Active Mode, Standby Mode,Sleep Mode, and ResetVeeveeEnableEnablec::lNMINMIIRQ,IRQ,RESPort 38 TransferLinesPort 18110LinesPort 181/0 LinesPOrt 481/0 LinesVSSPort 2 Port 25110 Lines 5110 LinesSCI16 Bit TimerSCIvssPort 48110 LinesFigure 27 HD63P01Ml MCU Single-Chip Dual Processor Configuration~HITACHI663

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------HD63P01M1MCU8AddressBusDataBus Address Bus Data BusFigure 28 HD63P01 Ml MCU Expanded Non-Multiplexed Mode(Mode 5)Figure 29 HD63P01M1 MCU Expanded Multiplexed Mode(Modes 2, 4 and 6)HD63P01M1 MCU16 8Address BusData BusFigure 30 HD63P01Ml MCU Expanded Non-Multiplexed Mode (Mode 1)664 ~HITACHI

------------------------------------------HD63P01M1,HD63PA01M1,HD63PB01M1• PRECAUTION TO THE BOARD DESIGN OF OSCILLA­TION CIRCUITAs shown in Fig. 31, there is a case that the cross talk disturbsthe nonnal oscillation if signal lines are put near theoscillation circuit. When designing a board, pay attention tothis. Crystal and C L must be put as near the HD63POIMIas possible.~ ~OJOJc: c:CII CII~ enCL :p .......-t__-i-i12 (XTAL)r-I ~I--+---""-II 3 (EXT AUmeLHD63P01M1• PIN CONDITIONS AT SLEEP AND STANDBY STATE• Sleep StateThe conditions of power supply pins (pins 1 and 21), clockpins (pins 2 and 3), input pins (pins 4,5, 6 and 7) and E clockpin (pin 40) are the same as those of operation. Refer to Table15 for the other pin conditions. Both address (Ao '" A 12 ) andchip enable (CE) for the EPROM are in "1" state.• Standby State__Only power supply pins (pins 1 and 21) and STBY pin (pin 7)are active. As for the clock pin EXTAL(pin3), its input is fIXedinternally so the MCU is not influenced by the pin conditions.XTAL (pin 2) is in "1" output. All the other pins are in highimpedance. Both address (Ao '" A 12 -) and chip enable (CE) forthe EPROM are in "1" output.Do not use this kind of print board design.Figure 31Precaution to the boad design ofoscillation circuitTable 15 Pin Condition in Sleep ModePin ~Port'P 1O -P 17Port 2P 2O -P 240 1 2,4 5 6 7Function I/O Port Lower Address Bus I/O Port ..... +- +-ConditionKeep the conditionjust before sleepOutput "'"Keep the conditionjust before sleep+- +- +-Function I/O Port +- +- +- +- +-ConditionKeep the conditionjust before sleep+- +- +- +- +-E: Lower Address E: Lower Address E: Lower AddressFunction Bus Data Bus Bus Data Bus Bus I/O PortPort 3 E: Data Bus E: Data Bus E: Data BusP 3o -P 31E: Output "'" E: Output "'" E: Output "'" Keep the conditionConditionHigh ImpedanceHigh ImpedanceE: High ImpedanceE: High ImpedanceE: High Impedance just before sleepFunction Upper Address +- +-Lower Address Busor Input PortUpper Address Busor Input PortI/O PortPort 4Address Bus: Out·P 40 -P 41 put "'" Keep the conditionCondition Output "'" +- +- Port: Keep the con· +-just before sleepdition just beforesleepSClSCIOutput "1"(Read Condition)Output AddressStrobe+-+- +- +- Output "1"+- +- Output "1"Output AddressStrobeInput Pin$ HITACHI 665

HD63P01M1,HD63PA01M1,HD63PB01M1------------------------------------------Table 16 Pin Condition during RESET~e0,2,4,6 1Pin5 7Port 1high impedance (input) .. .. ..Plo -- PI7Port 2high impedance (input) .. .. ..PlO -- P24Port 3E: "1" Q.utputP30 -- P37E: high impedancePort 4P40 -- P47high impedance (input) ..SCl"1" output (Read)(R/W)..SCIE: "1" output(AS) E: "0" output..high impedance .. .... .... "1" output"1" output high impedance (input)• PRECAUTION TO EMULATE THE HD6301V1 BYHD63P01M1The internal EPROM of the HD63POlMl provides 8k bytesaddress space located from $EOOO through $FFFF. The followingsshould be noted to emulate the HD630lVl (4k bytesinternal ROM) with the HD63POlMl.1. Mode 5 (Expanded Non-multiplexed Mode) and Mode 7(Single Chip Mode)Use 4k bytes of EPROM address space located from $FOOOthrough $FFFF.2. Mode 6 (Expanded Multiplexed Mode)Use 4k bytes of EPROM address space located from $FOOOthrough $FFFF. But do not use 4k bytes from $EOOOthrough $EFFF because these addresses are internal for theHD63POlMl, while these are external for the 1ID6301Vl.3. Mode 1,2,4No need to be careful, since ROM address is external inthese cases.HD63P01M1HD6301V1$EOOO) Address'"~m"'(EPROM)$EOOOI E.,,,M' Add"nInternal Address$FFFFFigure 32 Address Map of Mode 6666 ~HITACHI

------------------------------------------HD63P01Ml,HD63PA01Ml,HD63PB01Ml• PRECAUTION TO USE THE EPROM ON-PACKAGE8 BIT SINGLE CHIP MICROCOMPUTERPlease pay attention to the followings, since this MCU hasspecial structure with pin socket on the package.(1) Don't apply high static voltage or surge voltage over MAX­IMUM RATINGS to the socket pins as well as the LSI pins.If not, that may cause permanent damage to the device.(2) When using 32k EPROM (24 pin), insert it on the mark sideand let the four above pins open.(b) Note that the detergent or coating will not get in thesocket during flux washing or board coating aftersoldering, because that may cause bad effect on socketcontact.(c) Avoid permanent application of this under the conditionof vibratory place and system.(d) The socket, inserted and pulled repeatedly loses itscontactability. It is recommended to use new onewhen applied in production.4 Pins (On index side) open.24 Pin EPROM should be insertedon the mark side with 4 above open.(3) When using this in production like mask ROM type singlechip microcomputer, pay attention to the followings tokeep the good contact between the EPROM pins and socketpins.(a) When soldering the LSI on a print circuit board, therecommended condition isTemperature: lower than 250°CTime : within 10 sec.$ HITACHI 667

HD63P05YO,HD63PA05YO,-­HD63PB05YOCMOS MCU (Microcomputer Unit)-ADVANCE INFORMATION-HD63POSYO is an 8-bit CMOS single-chip microcomputerunit which has 4k bytes or 8k bytes of EPROM on the package.It is compatible with the HD630SYO except for ROM. TheHD63POSYO can be used to emulate the HD630SXO orHD630SYO for software. developmentor, or it can be used insmall-scale production.• FEATURES• Pin compatible with HD6305XO and HD6305YO• 256·byte of RAM• A total of 55 terminals, including 32 110's, 7 inputs and 16outputs.• Two timers8-bit timer with a 7-bit prescaler (programmable prescaler;event counter)15·bit timer (commonly used with the SCI clock divider)• On-chip serial interface circuit (synchronized with clock)• Six interrupts (two external, two timer, one serial and onesoftware)• Low power dissipation modes - Wait, Stop and StandbyMode• Minimum instruction cycle timeHD63P05YO ...... 1 IJ-S (f = 1 MHz)HD63PA05YO .... 0.67 IJ-S (f = 1.5 MHz)H D63PB05YO ..... 0.51J.S (f = 2 MHz)• Similar to HD6800 instruction set• Bit manipulation• Bit test and branch• Versatile interrupt handling• Full set of conditional branches• New instructions - STOP, WAIT, DAA• Applicaple to 4k or 8k bytes of EPROM4k bytes; HN482732A8k bytes; HN482764, HN27C64• TYPE OF PRODUCTSType No. Bus Timing EPROM Type No.HD63P05YO 1 MHz HN482732A·30, HN482764·3, HN27C64-30HD63PA05YO 1.5 MHz HN482732A-30, HN482764·3, HN27C64·30HD63PB05YO 2 MHz HN482732A·25, HN482764, HN27C64-25(Note) EPROM is not attached to the MCU.HD63P05YO, HD63PA05YO,HD63PB05YO ~~~')• PIN ARRANGEMENT(DC·64SP)Vss r"iOm ~IN'f iiST8Y 4,XTAL ~EXTAL~NUM~TIMER 'ii o Vee Vee 0A7 'iOA12 Vee 0As ~As n OA7 Vee 0A4 12OAs As 0A31A21 OAs A9 0AllOA4 A11 0Ao 187 1 oA3 VssO8s 1 OA2 Al00Bs 1B4 ~OAI CEOB3 21 OAo 070B2 ~ 000 Os bBl ~80 ~ 001 Os 0C7/Tx ~ 002 04 0Cs/Rx 26cs/a 7OVss 030C4 8C32C2Cl ~Co(Top View)GoGlG21 G3G4GsGs7 G7F7FsFs• F42 F351 F2FlFoE77 EsEsE4E3~ E2~ El~ Eo~ 07~ os/TNT2~os37 04033 0201Vee668 $ HITACHI

-------------------------------------------HD63P05YO,HD63PA05YO,HD63PB05YO• BLOCK DIAGRAMTIMERPort AI/OTerminalsPort 8I/OTerminalsAccumulator8 AIndexRegisterxCondition CodeRegister ccStackPointer SP. ProgramCounter"High" PCHProgramCounter"Low" PClCPUCPUControlAlU0,D./iiii'r,~= Port 00, Input0, Terminals0,EoE,E,E,E.E,E.E,Port EOutputTerminalsPort CI/OTerminalsCJEK +--..--.,jC./Rx +-""';'...--.,jC,/T. --t-t-:~L_..L_...JFoF,F,F,F.F.F.I 0--_ F,Port FOutputTerminalsOn PackageSerialDataRegisterr----------,EPROMHN482732AjHN482764[ HN27C64IAolAllA21A3A.IAsl1\&1!;IAgiAlolAliiAI21"0"£1IISerialStatusRegisterGoG,G,G,GoGoGoG,Port GI/OTerminalsIIIL I _____ _~HITACHI669

HD63701XO-------------­CMOS MCU (Microcomputer Unit)TheHD63701XO is an 8-bit CMOS sing!e-chip microcomputerwhich contains a CPU compatible with the HD6301XO, 4k byteEPROM, 192 byte RAM, 53 Input/Output lines, a Serial CommunicationInterface and 2 Timers. Besides powerful peripheralfunctions, Halt function and Memory Ready function are availablefor Bus interface in expanded mode.HD63701XO-ADVANCE INFORMATION-• FEATURES• Object Code Compatible with the HD6301 XO/HD6301V1.. Abundant On-Chip Functions;4k Byte EPROM, 192 Byte RAM, 53 I/O Lines, 16-bit Timer,8-bit Timer, Serial Communication Interface• Interrupt - 3 External Lines and 7 Internal Lines• MR Input for Use with Slow Memory• Halt Function for Direct Memory Access• Operation ModeMode 1 - Expanded Mode (On-Chip ROM disable)Mode 2 - Expanded Mode (On-Chip ROM enable)Mode 3 - Single Chip Mode• EPROM ProgramlVerify ModeThe same programming specification as standard 2732;V pp = 21V±0.5V, tpw = 50 msec.• Low Power Consumption Mode; Sleep Mode, Standby Mode• Minimum Instruction Cycle Time; 0.5#lS (f = 2.0MHz)• PIN ARRANGEMENT(DC-64S)HD63701XOP 10P"lP,.P,.p,.p ..P.,PHP,.p ..5 P"P,.51 P"P,.P"P"PISPIS 2p ..P"p ..p .. 2p .. 7p .. 8p ..p ..p .. 31P., 2(Top View)670 ~HITACHI

--------------------------------------------------------------HD63701XO• BLOCK DIAGRAMCEIP1o(Tin)P~I (Tout 1 )P,,(SCLK)P,,(Rx)Pu(Tx)Pu ITout2)Pu ITout3)P.,(TCLK)p,.P" (iA'Q,)P" (mf)P" (RArf)Vcc_Vss_(mo.)P ..P"P"P"p ..-P,,-P,,--P ... 4-_p ..-p ..-P,,-p",.-.r--Lt. ~A~i= .L...-r01 IIIInl1 lJ..J• a:" ~ ~I~ I~ 1~1~;ar--CPU

INTRODUCTION OFRELATEDDEVICES• 8/16-bit Multi-chip Microcomputers• 4-bit Single-chip MicrocomputerHMCS400 Series• 4-bit Single-chip MicrocomputerHMCS40 Series• LCD Driver Series• IC Memories• Gate Array• LSI for Speech Synthesizer System• CODEC/Filter Combo LSI

Preliminary data sheets herein contain information on new products. Specificationsand information are subject to change without notice.Advance Information data sheets herein contain information on productsunder development. Hitachi reserves the right to change or discontinue theseproducts without notice.674

~8_/1_6_-B_I_T_M_U_L_T_I-_C_H_I_P_M_IC __ RO __ C_O_M_P_U_T_E_R_S ________ ~• 8-BIT MULTI-CHIP MICROCOMPUTERSDivisionType No.LSI CharacteristicsClock Supply Operating···Process Frequency Voltage T emperatu fe PackagetOld Type No. (MHz) (V) (oC)H06803NMOS ~ 5.0 0-+70 DP-40H06803·1 1.25H06303RDP-40~-H063A03R CMOS 5.0 0-+70 FP-54~H063B03R 2.0 CG-40HD6303X·~ DP-64SH063A03X· CMOS ~ 5.0 0- +70FP-80H063803X· 2.0H06303Y·· ~ DP-64SH063A03Y-CMOS~ 5.0 0- +70 FP-64H063803Y·· 2.0H06305X2·~ DP-64SH063A05X2· CMOS.J4-- 5.0 0- +70 FP-64H063B05X2· 2.0H06305Y2·~ DP-64SMPU H063A05Y2· CMOS~ 5.0 0- +70 FP-64H063B05Y2· 2.0H06800 HD46800D~H068AOO HD468AOO NMOS 5.0~H068800 HD468800 2.0-20 - +75 DP-40HD6802 HD46802 NMOS 1.0 5.0 -20- +75 DP-40H06802W NMOS 1.0 5.0 -20 - +75 DP-40H06809~H068A09 NMOS 5.0 -20 - +75 DP-40~H068B09 2.0~H06309·· CMOS 5.0 -20 - +75 DP-40~3.0HD6809E~H068A09E NMOS 5.0 -20 - +75 DP-40~H068B09E2.0~H06309E·· ,:'IIIIOS 5.0 -20 - +75 DP-40~3.0H06821 HD46821~H068A21 HD468A21 NMOS ~ 5.0 -20 - +75 DP-40PIA H068B21 HD468B21 2.0H06321·~ DP-40H063A21· CMOS.J4-- 5.0 -20 - +75 FP-54H063B21· 2.0H06840~H068A40 NMOS 5.0 -20 - +75 OP-28~PTMH068B40 2.0H06340·~H063A40· CMOS 5.0 -20 - +75 DP-28~H063840· 2.0H06843 HD46503SFOCNMOS ~ 5.0 0- +75 DP-40H068A43 HD46503S-1 1.5HD6844 HD46504~DMAC H068A44 HD46504-1 NMOS 5.0 -20 - +75 DP-40HD68B44~HD46504-2 2.0HD6845 HD46505RHD68A45 HD46505R-l NMOS~5.0 -20 - +75 DP-40HD68B45 HD46505R-2 ~ 2.0CRTCHD68455 HD46505S~ ~HD68A45S HD46505S-1 NMOS 5.0 -20 - +75 DP-40'! ~HD68B45S HD46505S-22.0:i COMBO HD6846 HD46846 NMOS 1.0 5.0 -20 - +75 DP·40:: HD6850 HD46850NMOS ~ 5.0 -20 - +75 DP-24H068A50 HD468A50 1_5ACIA H06350r--L9--H063A50 CMOS 5.0 -20 - +75 DP-24~H063B50 2.0HD6852 HD46852SSOANMOS ~ 5.0 -20 - +75 DP-24H068A52 HD468A52 1.5HD48508~HD48508-1AOUNMOS rM--- 5.0 -20 - +75 DP-40HD48508A~HD48508A-l 1.5DP-24HOl48818 CMOS 1.0 5.0 0-+70 FP-24RTCH06318··CMOS ...!:.2....-HD63A18··1.55.0 -20 - +75 DP-24• Preliminary·· Undar daYelopment ••• Wide Tempe·ature Range (-40 - +85°C) version is evailable.tOP; Plestic DIP, FP;Plestic Flat Package, CG: GIIIs-sealed Ceramic Leadless Chip CerrierFunctionMicroprocessor +128 8ytes of RAMMicroprocessor +128 8ytes of RAMMicroprocessor +192 8ytes of RAMMicroprocessor +256 Bytes of RAMMicroprocessor +128 Bytes of RAMMicroprocessor +256 Bytes of RAMCompetibilityMC6803MC6803·1~.---MC6800MicroprocessorMC68AOOMC68800Microprocessor+Clock+128 Bytes of RAM MC6802Microjlroceaor+Clock+256 Bvtes of RAMMC6809High-End 8-Bit MicroprocessorMC68A09MC68B09High-End 8-Bit Micropr'oceaorHigh-End 8-Bit Microprocessor(External Clock Type)High-End 8-8it Microprocessor(External Clock Type)Peripheral I nterface AdapterPeripheral I nterface AdapterProgrammable Timer ModuleProgrammable Timer ModuleMC6809EMC68A09EMC68B09EMC6821MC68A21MC68B21MC6840MC68A40MC68B40Flopp'y Disk ControllerMC6843MC6844Direct Memory Access Controller MC68A44MC68B44CRT ControllerMC6845(3.0MHz High-speed Display)MC68A45MC68845CRT Controller(3.7MHz High-speed Display) -_.._-Combination ROM I/O TimerMC6846Asynchronous CommunicationsMC6850I nterface AdapterMC68A50Asynchronous Communications ;-------Interface Adap!erSynchronous Serial Data AdapterMC6852MC68A52Analog Data Acquisition UnitReal Time Clock Plus RAMReal Time Clock Plus RAMMCl46818$ HITACHI675

• 16-BIT MULTI-CHIP MICROCOMPUTERSDivisionType No.LSI CharacteristicsClock Supply Operating t Function CompatibilityProcess Frequency Voltage Tem~erature Package(MHz) (V) (oC)H068000-4 4 MC68000L4FiD68000-6 6 MC68000L6H068000-8 S DC-64 MC68000L8H06S000-10 10 MC68000L101--------H068000-12 12.5MC68000L12H068000Y4 4 MC68000R4HD68000Y6 6 MC68000R6MPU HD68000Y8 NMOS S 5.0 0- +70 PGA-68 Microprocessor MC68000R8H068000Y10 10 MC68000R10HD68000Y12 12.5 MC68000R12-HD6S000Z4* 4 MC68000Z4HD68000ZS* 6 MC68000Z6HDS8000ZS* S CG-68* MC68000Z8HDSSOOOZ10* 10 MC68000Z10HDSSOOOZ12* 12.5 MC68000Z12HD68450-4 4 MC68450L4HD68450-6 6 MC68450L6I H068450-S S DC-64 MC6S450LSHD68450-10* 10 MC68450L10H 068450-12 ** 12.5Direct MemoryDMAC NMOS 5.0 0-+70 --HD68450Y4 4 Access Controller iii-'HD68450Y6 6 -e HD68450YS S PGA-6S* -CII.r:.gHD68450Y10* 10 -CIIc..H D68450Y 12** 12.5-H 063463-4 ** 4 HOC H 063463-6 * * CMOS 6 5.0 -20 - +75 DC-4S Hard Disk Controller -H 063463-8 * * S -H 063484-4 * * 4 -ACRTC H 063484-6 * * CMOS 6 5.0 -20-+75 DC-64 Advanced CRT Controller -H 063484-8* * 8 --* Preliminary ** Under development DC; Ceramic DIP, PGA; Pin Grid Array,CG; Glass-sealed Ceramic Leadless Chip Carrier676 $ HITACHI

14-BIT SINGLE-CHIP MICROCOMPUTER HMCS400 SERIESThe new CMOS 4-bit HMCS400 microcomputer series isdesigned to satisfy the growing need for microcomputersystems with large program capacity and for advanced applications.The HMCS400 series strengthens the proven capabilitiesof the HMCS40 series, offering advanced software productivearchitecture, enhanced peripheral functions, and high speedinstruction execution.• FEATURES• Architecturally Compatible with the HMCS40 Series for ConvenientReplacement• 16 Subroutine Stack levels• 98 Instructions Including Logic Arithmetic and BCD ArithmeticOperating Instructions. and Pattern GeneratingInstruction• Five Interrupt Levels (External: 2. Time/Counter: 2. SerialInterface: 1)• 8-bit Serial Interface (Clock Synchronous Type)• Two Timer/Counters: 8-bit Free Running Timer and 8-bitReload Timer/Event Counter• 58 I/O Lines (26 High Voltage 40V I/O Lines)• One Cycle per Instruction Execution Utilizing 10-bit per • High Speed Instruction Execution: 21ls at Vee 5V, High SpeedVersion (1.3 #,5) AvailableInstruction .• Powerful ROM and RAM Addressing Capability • EPROM-on-Package Type Available for System Emulation-HMCS400 SERIES PRODUCT CHARACTERISTICS:1Family Name HMCS404CL* HMCS404C* HMCS404AC*Process Technology CMOS CMOS CMOSSupply Voltage (V) 2.5 - 6.0 4'::'6 4.5-5.5l!l Power Dissipation (n.ax.) (mW) 9 18 27t! Max. I/O Terminal Voltage (V) VCC-40-- f---. VCC -40coVCC -40~() Operating Temperature Range (oC) -20 - +75 -20 - +75 -20 - +75in..J Package FP·64, DP-64S FP-64, DP·64S FP·64, DP-64SMemoryROM (bits) 4096 x 10 4096 x 10 4096 x 10RAM (bits) 256 x4 256 x4 256 x 4'" c.gcRegisters 7 7 7Subroutine Stack Levels 16 16 164·Bit Input4x1 4 x 1 4x12 x 1 2 x 1 2 x 14·Bit Output 4x4 4x4 4x4I/O Ports4·Bit Input/Output58584x54x5584x5u 1-Bit Input/Output 1 x 16 1 x 16 1 x 16::lII.External 2 2 2Interrupts Timer/Counter 2 2 2Serial Interface_._-------_1 1-------f---------1~Instruction..- Number of Instructions 99 99 99Cycle Time (~s) 4 2 1.33Clock Pulse GeneratorOthersEPROM on the Package Type·PrellmlnaryBuilt-in (External drive is possible)Power Saving Mode (Stop mode, Stand-by mode)HD614P080S*eHITACHI 677

4-BIT SINGLE-CHIP MICROCOMPUTER HMCS40 SERIESThe HMCS40 Series are high performance, low cost 4-BitSingle-Chip Microcomputers designed for dedicated applications.The HMCS40 Series Instruction Set provides convenient chipFEATURES• Full Line-Up: CMOS2 - 4k Words ROM160 - 256 Words RAM32 - 44 I/O Lines• All Instructions (except Pattern Generation Instruction)are Single cycle.• Pattern Generation Instruction (Table Reference Capability).• Powerful Interrupt Function .selection and system expansion.LCD-III/IV are LCD driver on chip microcomputers designedfor applications which need an LCD display device.• 3 Interrupt Sources -r2 External Interrupt Linel-1 Timer/Counter• Low Power Dissipation (2mW): CMOS.• Low Operating Voltage Version (3V): CMOS.• Built-in Clock Pulse Generator (Resistor or Ceramic Filter).• Built-in Power-on Reset Circuitry.• I/O Options (User Selectable at Each Pin).CMOS: Pull up Resistor/Open Drain/CMOS Output• Built-in LCD drive circuit: LCD-III/IV.• HMCS40 SERIES PRODUCT CHARACTERISTICSHMCS44CLFamily Name(HD44808)HMCS44C(Type Name)(HD44800)..u Process Technology CMOS.;: Supply Voltage (VCC) (V) 3/5! Power Dissipation (Typ.l (mW) 0.32/2~Max. I/O Terminal Voltage (V) VCC + 0.3J: '"(,)Operating Temperature Range .1 (oC) -20 - +75CiioJ PackageDP-42, DP-42S..MemoryROM(bits)2,048 x 10128 X 10. 2RAM (bits) 160x4Registers 8Stack Registers 44-Bit Data Input -Discrete Input -4-Bit Data Output-I/O Ports 32c: Discrete Output -0"fi 4-Bit Data Input/Output 4x4c::J Discrete Input/Output 1 x 16\L.InterruptsExternal 2Timer/Counter 1Number of InstructionsInstruc-71tions Cycle Time (~s) 20/10Built-in Clock Pulse GeneratorPower on ResetBattery Back-upNo/YesHaltHMCS45CL(HD44828)HMCS45C(HD44820)CMOS3/50.32/2VCC +0.3-20 - +75FP-54, DP-64S2,048 x 10128 X 10*2160 x 46444217120/10--No/YesHalt4 x 1-4x61 x 16HMCS46CL HMCS47CL LCD-III *3(HD44848) (HD44868)(HD44795,HMCS46CHMCS47C(HD44840) (HD44860)HD44790)LCD-IV *3(HD613900)CMOS CMOS CMOS CMOS3/5 3/5 3/5 3/50.32/4 0.32/4 0.36/2.4 0.9/5.0VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3-20 - +75 -20 - +75 -20 - +75 -20 - +75DP-42, DP-42S FP-54,DP-64S FP-80 FP-804,096 x 10 4,096 x 102,048 x 10128 X 10. 24,096 x 10256 x4 256 x4 160 x 4 256 x 48 6 6 64 4 4 432- - 4 x 1 4 x 1f---- - -f----4 x 14 x 14 x 1443232 f---- - -r----4x4 4x6 4x2 4x2i--1 x 16 1 x 16 1 x 16 1 x 162 2 2 21 1 1 171 71 71 7120/5 20/5 20/10 20/5No/Yes No/Yes Yes NoHalt Halt Halt HaltEvaluation ChipHD44850EHD44857EHD44850EHD44857EHD44857E HD44857E HD44797E HD44797E*1 Wide Temperature Range (-40 - +85°C) version is available.*2 Pattern Memory*3 LCD DRIVE FUNCTIONCommon 4LCD Segment 32DriveDuty Static, 1/2, 1/3, 1/4Display CapabilityBias 1/2,1/34x32 Matrix (1/4 Duty)Expandable using the LCD Driver HD44100H.678 $ HITACHI

LCD DRIVER SERIES• LCD DRIVER SERIES CHARACTERISTICSTypeGeneralII Type Number HD44100H HD61100.~"i Procell-.~.-.. - CMOS CMOSSupply Voltage (V) 5*' 5*'IoS: Operating Temperature (oC) -20 - +75 -20 - +750PackageiiiFP-60 FP·l00..J Po_r Dissipation (mW) 5.0 5.0MemoryROM (bits) - -RAM (bits) - -Interface (CPU) B 8Interface (Driver IC) 2 2110~cInterface"z (External ROM, RAM) - -c:;, Number of Instruction"-- -Common40 80LCD Driver Segment.---Duty FrH(N) Free (N)N x40N x80Display Capability Matrix Matrix(lIN Duty) (lIN Duty)Comment SR type SR typeSegment DisplayHD61602-------HD61603HD44780(LCO·II)CMOS----~O~CMOS3 - 5*' 3 - 5*1 5"-20 - +75 -20 - +75 -2Q - +75*2FP-80 FP·BO Fp·800.5 (5V) 0.5 (5V) 1.75- -7200(CG)"'51 x4 64 xl14 10 11- - 4- - -4 4 114 1 1680 x 8/64X 8(CG)"J51-64 40Static, 1/2,1/3,1/4Static l/B, 1/1 "1/1S204 16 DigitsSegment 64 Segment (5 x7 Dots(1/4 Duty) 1/1S Duty)Expandableto 80 DigitsusingHD44100H'1: Except Power Supply for LCD.*2: -40 - +8S o C (Special Request). Please contact Hitachi Agents.'3: CG;Character Generator.680 ~HITACHI

-----------------------------ILCD DRIVER SERIESCharacter DisplayGraphic DisplayHD44101H HD43160AH HD44102CH HD44103CH HD44105H HD61B30 HD61102 HD61103~~OS CMOS CMOS CMOS CMOS CMOS CMOS CMOS5" 5" 5" 5*' 5,1 5*' 5*1 5*'-20 - +751---- ---20 - +75 -20 - +75 -20 - +75 -20- +75 -20 - +75 -20 - +75 -20 - +75FP-80 FP-54 FP-BO FP-60 FP-60 FP-60 FP-100 FP-1001.75 10.0 2.5 4.0 4.0 30.0 3.0 5.06720 6240 7360(CGI'> (CGI*' - - - - -(CGI*'32 x8 80 x 8 200 x 8 -(external- 65536 x 81512 x 8 -12 21 21 6 6 13 21 64 5 - 5 5 9 - 5- 18 - - - 33 - -B 6 6 - - 12 7 -15 - - 20 32 - - 6440 - 50 - - - 64 -1/8,1/12, 1/8,1/12,1/16, 1/8,1/12,1/16, 1/8,1/12,1/16,1/24,117,1/14Static,1/48,1/64- 1/641~16 1/24,1/32 1/24,1/32 1/32,1/48,1/64 1/1 - 1/12B 1196,1/12816 Digits 32 x 50 64 x64(5 x 7 Dots - Dots - - - Dots-1/14 Dutyl (1/32 Dutvl (1/64 dutylExpandable Display to Display toto 32 Digits 80 Digits Segment Common Common 524288 Segment Commonusing using Driver Driver Driver Dots using Driver DriverHD44100H HD44100H HD44100H~HITACHI 681

[fc MEMORIES• MOSRAMModeStaticTotalBit16k-bit64k-bitOrganiza- Access Cycle Supply Power Package tType No_ Process tion Time Time Voltage Dissipation(word x bitl (ns) max (ns) min (V) (W) Pin No. CG G P FP SPHM6116-2 120 120 0.1m/O.2 r-HM6116-3 150 1500.1m/0.1BHM6116-4 200 200• HM6116L-2 120 120 20~MO.18 HM6116L-3 150 15020~MO.16HM6116L-4 200 200• •HM6116A-12 120 120 HM6116A-15 150 150 0.1m/15m HM6116A-20 2048 x 8 200 200 24 HM6116AL-12 120 120 HM6116AL-15 150 150 5~/10m HM6116AL-20 200 200•HM6117-3 - 150 1500.1m/0.2• HM6117-4 200 200 HM6117L-3 150 15010~/0.18 HM6117L-4 200 200•HM6168H-45 45 45 HM6168H-55 55 550.1m/0.25CMOS+5HM6168H-7070 704096 x 420 •HM6168HL-4545 45HM6168HL-55 55 555~/0.25HM6168HL·70 70 70 5~/0.25HM6167 70 70 HM6167-6 85 85 0.1m/0.15 HM6167-8 100 100•HM6167L 70 70HM6167L-6 85 85 5~/0.15HM6167L-8 100 10045 45 • •HM6167H-4516384 x 1HM6167H-55 55 550.1m/0.2 20HM6167HL-45 45 45HM6167HL-55 55 555~/0.2HM6267-35 35 35HM6267-45 45 450.1m/0.25HM6264-10 100 100HM6264-12 120 120 0.1m/0.2 HM6264-15 150 1508192 x 828 •HM6264L-10100 100HM6264L-12 120 120 1O~/0.2 HM6264L-15 150 150•(Continued)682 $ HITACHI

-------------------------------------------------------------IC MEMORIESModeTotalBit64k-bitOrganiza- Access Cycle Supply Power Package tType No. Process tion Time Time Voltage Dissipation(word x bit) (ns) max (ns) min (V) (W) Pin No. CG G P FP SPHM48416A-12 120 230HM48416A-15 16384 x 4 150 260 20m/0.3 18HM48416A-20 200 330HM4864-2 150 270HM4864-3 200 33520m/0.33•HM4864A-12 65536 x 1 120 220 HM4864A-15 150 260 +5 20m/0.25 Dynamic HM4864A-20 NMOS 200 330 16• •HM50256-12 120 220 HM50256-15 150 260 20m/0.35 HM50256-20200 330256k-bit262144 x 1HM50257-12 120 220 HM50257-15 150 260 20m/0.36 HM50257-20 200 330•Do HM6116LP/LFP Series: 10 p.Wt The package codes of CG, G, P, FP and SP are applied to the package materials as follows.CG: Glass-sealed Ceramic Leadless Chip Carrier, G: Cerdip, P: Plastic DIP, FP: Plastic Flat Package (SOP), SP: Skinny Type Plastic DIP• MOS ROMModeAccessTotalOrganizationType No. Process TimeBit(word x bit)(ns) maxHN61364 25064k-bit HN61365 8192 x 8 250HN61366 250Mask 128k-bit HN613128 CMOS 16384 x 8 25032768x8 orHN61256256k-bit65536 x 43500HN613256 32768 x 8 2501M-bit HN62301 * 131072 x 8 350HN482732A-20 20032k-bit HN482732A-25 4096 x 8 250HN482732A-30 300NMOSHN482764250HN482764-2 200HN482764-3 300U.V. Erasable64k-bit HN27C64-15 8192 x 8 150& ElectricallyHN27C64-20 200CMOSHN27C64-25250HN27C64-30 300HN4827128-25 250128k-bit HN4827128-30 16384 x 8 300HN482712845450NMOSHN27256-20 200256k-bit HN27256-25 32768 x 8 250HN27256-30 300On Time 64k-bit HN482764-38192 x 8 300NMOSElectrically128k-bit HN4827128-30* 16348 x 8 300HN58064-25 250Electrically64k-bit HN58064-30 NMOS 8192 x 8 300Erasable &ProgrammableHN58064-45 450* Preliminaryt The package codes of C, G, P and FP are applied to the package material as follows.C: Side-brazed Ceramic DIP, G: Cerdip, P: Plastic DIP, FP: Plastic Flat PackageSupply Power Package tVoltage Dissipation(V) (W) Pin No. C G285p./50m24+5 5p./50m5p./7.5m5p./50m2m/75m280.18/0.8 24 0.18/0.55 •••+5 •0.55m/0.1 28•0.18/0.53 •+5·0.22/0.55 •0.18/0.550.18/0.5328+5 0.22/0.55 28.p FP•• •••~HITACHI683

Ie MEMORIES---------------------------------------------------------------• BIPOLAR RAMAccess Supply Power Package tTotalOrganizationlevel Type No. Output Time Voltage DissipationBit(word x bit)(ns) max (V) !.mW/bit) Pin No. F G P CCHM1041410256256 x 12.8 HM10414-1 8 HM2110 350.5 16 HM2110-1 251024 x 11k HM2112100.8HM2112-1 8HM10422 10 0.8256 x 424 HM10422-77 1.0 • HM10470 25 HM10470-1 15 0.2 18ECl4096 x 1HM10470-252510k-5.2HM2142 100.3 204k•HM10474 25 0.2 ..HM10474-8*81024 x 40.3 24 HM10474-10* 10- -~-HM10480 Open 25 0.05• H M 10480-15 * 16384 x 1 Emitter 15200.0616k HM10480-20* 20 HM10484-15*154096 x 40.06 28 HM10484-20* 20•HM100415 i024 x 1 10 0.6 16• ..1kHM100422 256 x 4 10 0.8 24• •HM100470 4096 x 1 25 0.2 18 ECl 4k HM100474 1024 x 4 25 -4.5 0.2 24 100k HM100480 25 0.05• HM100480-15* 16384 x 1 15 200.0616k HM100480-20* 20•H M 100484-15 *154096 x 40.06 28 H M 100484-20 * 20•• Under developmentt The package codes of F, G, P and CC are applied to the package materials as follows.F: Flat Package, G: Cerdip, P: Plastic DIP, CC: Ceramic Leadless Chip Carrier.684 ~HITACHI

GATE ARRAYCMOS Gate Array HD61J/HD61K/HD61L/HD61MM Series• FEATURES• Fast operationInternal gate (2-input NAND, FO=3, Al=3mm) .. 3.5ns typInput buffer (FO=3, Al =.3mm) ............. 9ns typOutput buffer (Cl =50pF). . . . . . . . . . . . . . . .. 20ns typMemory access time (HD61MM) ............... 60ns typ• low power dissipationAt 10MHz operation (Internal gate) ...... 1301.tW/gate typ• Abundant input and output configurationAllocation of all pins except power supply pins to input/output/input-outputOutput can be CMOS/open drain/3-state• Memory on-chip (HD61MM)Flexibility of memory capacity and word organizationSelection of single port/dual port memory• Wide operation temperature range-20 to +75°C• Wide package selectionEspecially plastic packages with high pincount ....••.... DllP64/FPP100• Powerful design supportUser-Defined-MacroTest pattern evaluation with fault simulatorDesign support at local Design Center• Quick turn around time and reasonable development cost• LINE UPHD61JGate count 504I/O pin count 50~Monchip -DP28 0DP42 0DP64 -FP54 0PackagePower supply pinFP80 -FP100 -DC28 0DC40 0PGA72 -PGA120 -HD61K HD61l HD61MM*1080 1584 249668 68 104- - available0 0 -0 0 -0 0 0- - -0 0 -- - 0*0 0 00 0 0- 0 -- - 0*4 4 8** PreliminaryBi-CMOS Gate Array HD27K/HD27L/HD27P/HD27Q Series• FEATURES• High speed with super low power dissipation• Internal gate: 4.0ns (Fan out=3)@0.05mW• Input buffer: 5.0ns (Fan out=3)@2.6mW• Output buffer: 8.0ns (Cl =15pF)@2.6mW• lS TTL compatible input/output .................. .• Selectable totem-pole/3-state/open collector output• IOl =8mA: Capable of driving 20 lS TTL's• Output buffer can construct logic functions.• Saves gate stages.• A variety of macrocelilibrary• Internal gate: 44• Output buffer: 9• A variety of reliable package• Plastic DIP 16 to 64 pins• Plastic FP 60 to 100 pins (under development)• A variety of DA 'system support• Only logic diagrams and test patterns needed as an interfacewith the user.• Short development time$ HITACHI 685

GATEARRAY--------------------------------------------------------------Number of gates Number PackageI nternal gate Input Outputof VeeDIPand GND(2-input NAND) buffer buffer(Plastic)pinsHD27K 200 18 18 2HD27L 528 30 30 4HD27P 966 40 40 4HD27Q 1530 50 50 4·Under development16,20,28,42 pins28,42,64.pinsFP*(Plastic)-60,80 pins28,42,64 60,80,100pinspins28,42,64 60,80,100pinspins686 ~HITACHI

LSI FOR SPEECH SYNTHESIZER SYSTEMPMOS 3-chip System• OUTLINE OF BASIC DEVICEType name Function Explanation of function OutlineHD38880BHD38884PHD38882PHMCS40*SeriesSpeech Synthesizes speech by reading out a prescribed c~aracteristic parameter DC-28synthesizer from the ROM chip according to the command from the microcomputer. DP-28128k-bitROMEPROMinterfaceControllerAnalyzes the speech which should be synthesized in advance and stores theextracted characteristic parameter.Capable of 1M-bit connection when using EPROM.Performs overall control to synthesize special speech under suitableconditions.DP-28DP-42**See 4-bit microcomputer item.• System Features• High speech quality • Long-period voice capacitySince a PARCOR system is employed and the bit rate can betaken up to 2400-9600 bits/sec, excellent tone quality ismade possible.A maximum of 16 ROMs can be connected without an interfaceCircuit. Vocal sound of 50"'100 seconds (2400 bit/sec)can be synthesized with 1 ROM.• Synthesizing woman's voiceIn addition to a man's voice, synthesizing woman's voice ispossible with the adoption of the vocal tract loss effect.• Variation of speaking speedSpeech can be spoken slowly or rapidly by microcomputercontrol.• Vocalization with accurate scaleBy producing voice pitch through external synchronization,accurately scaled singing is possible.• Speaker direct driveThe speaker is directly driven by the built-in 0/ A converter andspeaker driving circuit. Excellent tone quality and power ispossible by providing an external Of A converter and speakerdriving circuit utilizing the digital output.• BASIC SYSTEM COMPOSITION EXAMPLES• Case of using mask ROM• Case of using EPROMCeramicOsCillatorCeramicOSCillatorHMCS40 Serie.(Controller)Analog Output \r====::::{11 )i)HMCS40Seriel(Controller)H038884(128k bit ROM)x 16rnaxAMPI'HN482764x 16 maxeHITACHI 687

LSI FOR SPEECH SYNTHESIZER SYSTEM---------------------• SYSTEM SPECIFICATIONSItemSystemVoice channel modelVoice source modelSampling frequencyContentPARCOR system8th stage/10th stage digital filter . . . . . . . . . . . . • . . . . . . . . . . • . . . . .• SelectableVocal tract loss effect (existence/non-existence) .......•.......... SelectableVoice sound ...... Rectangular wave/triangle wave ............. SelectableVoiceless sound ... White noise8 kHzBit rate (b/s) 2400 4800 9600Frame period (ms) 20 10/20 10Variable speaking speedPitchSpeaking timeVariation of frame period is possible from -30% to +600~ by 1 OO~ steps.I ntegral times of 125 #Is/External synchronization " ........•.. . .. Selectable50-100 sec/ROM (2400 b/s)CMOS 1-chip System• OUTLINE OF BASIC DEVICEType No. Function Explanation of function OutlineH06t885 Speech Synthesizes speech by reading out a prescribed characteristic parame- OP-28ter from the internal or external ROM according to the commandH061887 Synthesizer from the microcomputer or key switch. FP-54(Expanding ROM)(H044881) 128k-bit ROM Performs overall control to synthesize special speech under suitable OP-28conditions.• SYSTEM FEATURES• 1-chip system • Long-period voice capacityIncluding synthesizer, 32k-bit ROM and interface circuit.A maximum 16 ROMs can be connected without an interface• High speech qualitySince a PARCOR system is employed and the bit rate can becircuit. Vocal sound of 50-100 seconds can be synthesizedwith 1 ROM.taken to 1250-9900 bit/sec, excellent tone quality is possible. • Low power dissipation (Standby mode)• SYSTEM SPECIFICATIONSItemContentSystemPARCOR systemVoice channel model10th stage digital filterSampling frequency10 kHzBit rate (b/s) 1,250 - 9,900Frame period (ms) 10/20Variable speaking speed -25%, 0, +25%Speaking time 10 - 20 sec (internal ROM)Supply Voltage 5V single (3.6 - 5.5V operation)688 $ HITACHI

---------------------LSI FOR SPEECH SYNTHESIZER SYSTEM• BASIC SYSTEM COMPOSITION EXAMPLESe Key InputeCode InputCeramicOscillatorFilter Ampr-- --- ---,I ,IIII, 'I'I, I, HD44881 :I {128k-blt ROM • 16m •• 1 :, II L __________________ J Ir-- -- - --,IIIIIIIIIIIIIII HD44881 IIIII, II~-----------------~Ie Microcomputer ControlVeeHMCS40 Serl ••(Controller,Filter Amp.r--- -- -IIII: ~ :III :: HD44881 :IIIIIIIIL I _____________________ J IIICf)HITACHI689

I CODEC/F I L TER COM.BO LSI• LINE UPSeriesType No.CompoLawPowerDissipation(mW)CRFilterVoltageReferenceClockInternal Sync.! PCM BitClock Async. Clock RequiredSignalingPackageHD44211A AHD44210 150HD44212A IIHD44220 HD44222 II 40HD44230HD44231BHD44232BHD44233BHD44234BHD44235HD44236HD44237HD44238HD44231CHD44232CHD44233CAIIAIIAIIAIIAHD44234C IIHD44230C 60HD44235C AHD44236C IIHD44237CHD44238C IIHD44240C HD44240C II 60IIAA6050--aaaa-External128 kHz req.Both 64 - 2048kHzExternal PLL Both 64 - 2048kHzSync.a Divider - 1536/1544/2048kHzBothSync.a PLL - 64 - 2048kHzaBothSync.Divider - 1536/1544/2048kHzBothSync.PLL - 64 - 2048kHzBotha PLL Both 64 - 2048kHz- DC·24Decoder Shift--Decoder Shift-Decoder Shift--Decoder Shift-Decoder ShiftA/B Data I/ODC-16DG-16DG-20A-law; Europe & International Telephone.IJ-Iaw ; U.S.A., Canada & Japan690$ HITACHI

HITACHI AMERICA, L TO.SEMICONDUCTOR AND IC SALES & SERVICE DIVISIONHEADQUARTERSHitachi, Ltd.Nippon Bldg., 6-2, 2-chomeOhtemachi, Chiyoda-ku, Tokyo, 100, JapanTel: 212-1111Telex: J22395, J22432U.S. SALES OFFICEHitachi America, Ltd.Semiconductor and IC Sales & Service Division1800 Bering DriveSan Jose, CA 95112Tel: 408/292-6404Telex: 17-1581Twx: 910-338-2103Fax: 408-2922133Fax: 408-2949618REGIONAL OFFICESNORTHEAST REGIONHitachi America, Ltd.5 Burlington Woods Dr.Burlington, MA 01803617/229-2150SOUTHERN REGIONHitachi America, Ltd.Two Lincoln Centre, Suite 8655420 LBJ FreewayDallas, TX 75240214/991-4510NORTH CENTRAL REGIONHitachi America, Ltd.500 Park Blvd., Suite 415Itasca, I L 601433121773-4864NORTHWEST REGIONHitachi America, Ltd.2099 Gateway Place, Suite 550San Jose, CA 95110408/277-0712SOUTHWEST REGIONHitachi America, Ltd.Warner Center Plaza One21600 Oxnard St., Suite 600Woodland Hills, CA 913678181704-6500DISTRICT OFFICES• Hitachi America, Ltd.1700 Galloping Hill Rd.Kenilworth, NJ 07033201/245-6400• Hitachi America, Ltd.3500 W. 80th Street, Suite 175Bloomington, MN 55431612/831-0408• Hitachi America, Ltd.80 Washington St., Suite 101Poughkeepsie, NY 12601914/485-3400• Hitachi America, Ltd.1 Parkland Blvd., #1222EDearborn, MI 48126313/271-4410• Hitachi America, Ltd.6200 Savoy Dr., Suite 850Houston, TX 77036713/974-0534• Hitachi America, Ltd.5775 Peachtree Dunwoody Rd.Suite 270-CAtlanta, GA 30342404/843-3445• Hitachi America, Ltd.4901 N.W. 17th WayFort Lauderdale, FL 33309305/491-6154• Hitachi America, Ltd.18004 Skypark Circle, Suite 200Irvine, CA 92714714/261-9034692

@HITACHIHitachi America, LtdSernlcoriductor and IC Soles and Service Divlslori1800 Bering Drive, Son Jose, CA 951121408-292 -6404t'lll l • j II, ,J'; !\