Microcomputer Unit - Index of

-----------------------------------------------------HD6801S0,HD6801S5• SIGNAL' DESCRIPTIONS• Vee.nd VssThese two pins are used to supply power and ground to thechip. The voltage supplied will be +5 volts ±5%.• XTAL.mt EXTALThese connections are for a parallel resoll .• ( fundamentalcrystal. AT cut. Divide by 4 circuitry is included with theinternal clock. so a 4 MHz crystal may be used to run thesystem at 1 MHz. The divide by 4 circuitry allows for use of theinexpensive 3.58 MHz Color TV crystal for non·time criticalapplications. Two 22pF capacitors are needed from the twocrystal pins to ground to insure reliable operation. EXT AL maybe driven by an external clock source at a 4 MHz rate to run at1 MHz with a 40/60% duty cycle. It is not restricted to 4 MHz,IS it wnI divide by 4 any frequency less than or equal to 4 MHz.XTAL must be grounded if an external clock is used. Thefollowing are the recommended crystal parameters:~ItemNominal Crystal Parameter4MHz 5MHzCo 7 pF max. 4.7 pF max.Rs 6Onmax. 3OnWp.XTAL~--~-----'CJE)(TAL~-"'...,tL2 Jr CL1Figure 12 Crystal InterfaceCL 1 ., CL2 = 22pF :t 20%(3.2 - 5MHz)[Note] These are representativeAT cut parallel resonancecrystal parameters.• Reset (RES)This input is used to reset and start the MCU from a powerdown condition, resulting from a power failure or an initialstartup of the processor. On power up, the reset must be held"Low" for at least 100 ms. During operation, REs, whenbrought "Low", must be held "Low" at least 3 clock cycles.When a "High" level is detected, the MCV does the following:I) All the higher order address lines will be forced "High".2) I/O Port 2 bits 2, I, and 0 are latched into programmedcontrol bits PC2, PC 1 and PCO.3) The last two ($FFFE, $FFFF) locations in memory willbe used to load the program addressed by the programcounter_4) The interrupt mask bit is set, must be cleared before theCPU can recognize maskable interrupts.• Enable (E)This supplies the external clock for the rest of the systemwhen the internal oscillator is used. It is a single phase, TTLcompatible clock, and will be the divide by 4 result of the'crystal frequency. It will drive one TTL load and 90 pF.• Non·Maskable Interrupt (NMI)A low·going edge on this input requests that a non·maskable·interrupt sequence be generated within the processor. As withinterrupt Request signal, the processor will complete the currentinstruction that is being executed before it recognizes the NMIsignal. The interrupt mask bit in the Condition Code Registerhas no effect on NMI.In response to an NMI interrupt, the Index Register, ProgramCounter, Accumulators, and Condition Code Register are storedon the stack. At the end of the sequence, a 16·bit address willbe loaded that points to a vectoring address located in memorylocations $FFFC and $FFFD. An address loaded at these loca·tions causes the CPU to branch to a non·maskable interruptservice routine in memory.A 3.3 kn external resistor to Vee should be used forwire·OR and optimum control of interrupts.Inputs IRQl and NMI are hardware interrupt lines that aresampled during E and will start the interrupt routine on theE following the completion of an instruction.• Vee StMldbyThis pin wnI supply +5 volts ±5% to the standby RAM on thechip. The first 64 bytes of RAM wnI be maintained in the powerdown mode with 8 mA current max. The circuit of figure 13can be utilized to assure that Vee Standby does not go belowV SBB during power down.To retain information in the RAM during power down thefollowing procedure is necessary:I) Write "0·· into the RAM enable bit, RAM E. RAM E is bit6 of the RAM Control Register at location $0014. Thisdisables the standby RAM, thereby protecting it at powerdown.2) Keep Vee Standby greater than VSBB.Vee Standbyi'_,LI'"J,Figure 13 Battery Backup for Vee Standby• Interrupt Request (lRQl)This level sensitiv~ input requests that an interrupt sequencebe generated within the machine. The processor will wait until itcompletes the current instruction that it being executed beforeit recognizes the request. At that time, if the interrupt mask bitin the Condition Code Register is not set, the'ml\chine will beginan interrupt sequence. The Index Register, Progr;un Counter,Accumulators, and Condition Code Register are stored on thestack. Next the CPU will respond to the interrupt request bysetting the interrupt mask bit "High" so that no further mask·able interrupts m~y occur. At the end of the cycle, a 16-bitaddress will be loaded that points to a vectoring address which islocated in memory locations $FFF8 and $FFF9. An addressloaded at these locations causes the CPU to branch to an inter·rupt routine in memory.The IRQl requires a 3.3 kSl external resister to Vee whichshould be used for wire·OR and optimum control of inte'!!!!pts.Internal Interrupts will use an internal interrupt line (IRQ,).This interrupt will operate the same as IRQl except that it willuse the vector address of $FFFO through $FFF7. ~ willhave priority over IRQ 2 if both occur at the same time. TheInterrupt Mask Bit in the condition code register masks bothinterrupts (See Table 1)._HITACHI 47