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14.1.3 SMBus.................................................................................................18514.1.4 Hot-Plug Serial Buses ............................................................................ 18514.1.5 RMII Bus .............................................................................................18514.1.6 CLINK Bus ...........................................................................................18614.1.7 <strong>Intel</strong> ME Clock ......................................................................................18614.1.8 Clock Pin Descriptions ........................................................................... 18614.1.9 High Frequency Clocking Support............................................................ 18714.1.9.1 Spread Spectrum Support ........................................................18714.1.9.2 Stop Clock.............................................................................. 18714.1.9.3 Forwarded Clocks ....................................................................18714.1.9.4 External Reference ..................................................................18714.1.9.5 PLL Lock Time......................................................................... 18814.1.9.6 Analog Power Supply Pins.........................................................18814.2 Miscellaneous Requirements and Limitations........................................................ 18815 Reliability, Availability, Serviceability (RAS) .......................................................... 18915.1 RAS Overview .................................................................................................18915.2 System Level RAS............................................................................................ 19015.2.1 Boot Processor .....................................................................................19015.2.2 Inband System Management .................................................................. 19015.2.3 Outband System Management ................................................................ 19015.3 IOH RAS Support.............................................................................................19115.4 IOH Error Reporting ......................................................................................... 19115.4.1 Error Severity Classification.................................................................... 19215.4.1.1 General Error Severity Classification .......................................... 19215.4.1.2 Thermal Error Severity Classification.......................................... 19415.4.2 Inband Error Reporting..........................................................................19415.4.2.1 Synchronous Error Reporting .................................................... 19515.4.2.2 IOH Asynchronous Error Reporting ............................................ 19615.4.3 IOH Error Registers Overview .................................................................19815.4.3.1 Local Error Registers................................................................ 19915.4.3.2 Global Error Registers .............................................................. 20015.4.3.3 First and Next Error Log Registers ............................................. 20315.4.4 Error Logging Summary......................................................................... 20415.4.4.1 Error Registers Flow ................................................................20515.4.4.2 Error Counters ........................................................................20715.4.4.3 Stop on Error.......................................................................... 20815.5 <strong>Intel</strong> QuickPath Interconnect Interface RAS ......................................................... 20815.5.1 Link Level CRC and Retry.......................................................................20815.5.2 <strong>Intel</strong> QuickPath Interconnect Error Detection, Logging, and Reporting .......... 20915.6 PCI Express RAS..............................................................................................20915.6.1 PCI Express Link CRC and Retry..............................................................20915.6.2 Link Retraining and Recovery ................................................................. 21015.6.3 PCI Express Error Reporting Mechanism................................................... 21015.6.3.1 PCI Express Error Severity Mapping in IOH .................................21015.6.3.2 Unsupported Transactions and Unexpected Completions ............... 21015.6.3.3 Error Forwarding ..................................................................... 21015.6.3.4 Unconnected Ports...................................................................21115.6.3.5 PCI Express Error Reporting Specifics.........................................21115.7 IOH Error Handling Summary ............................................................................21215.8 IOH PCIe Hot Add/Remove Support....................................................................22415.8.1 PCI Express Hot-Plug ............................................................................ 22415.8.1.1 PCI Express Hot-Plug Interface..................................................22515.8.1.2 PCI Express Hot-Plug Interrupts ................................................22715.9 Virtual Pin Ports (VPP) ...................................................................................... 22915.10 Operation ....................................................................................................... 22916 <strong>Intel</strong> ® Virtualization Technology ............................................................................ 23316.1 Introduction .................................................................................................... 23310 <strong>Intel</strong> ® 5520 Chipset and <strong>Intel</strong> ® 5500 Chipset Datasheet

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