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3.3.1 Gen1/Gen2 SupportThe IOH supports both the PCI Express First Generation (Gen1) and the PCI ExpressSecond Generation (Gen2) specifications. The Gen2 ports can be configured to run atGen1 speeds; however, Gen1 ports cannot be configured to run at Gen2 speeds.All PCI Express ports are capable of operating at both Gen1 and Gen2 speeds.3.3.2 PCI Express Link Characteristics - Link Training,Bifurcation, and Lane Reversal Support3.3.2.1 Port BifurcationThe IOH supports port bifurcation using PEWIDTH[5:0] hardware straps. The IOHsupports the following configuration modes:3.3.2.2 Link TrainingThe width of all links are exactly specified by the strapsThe width of all links are programmed by the BIOS using the PCIE_PRTx_BIF_CTRLregister (wait on BIOS mode)The IOH PCI Express devices support the following link widths: x16, x8, x4, x2, x1, upto the maximum allowed for the device based on the bifurcation settings. Each devicewill first attempt to train at the highest possible width configured. If there is a failure totrain at the maximum width, the IOH will attempt to link at progressively smallerwidths until training is successful.For full-width link configurations, lane reversal is supported. Most degraded link widthsalso support lane reversal, see Table 3-3, Supported Degraded Modes.48 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet
Figure 3-2.Intel 5520 Chipset PCI Express Interface PartitioningTransactionIOU0TransactionIOU1TransactionIOU2LinkLinkLinkPhysicalPhysicalPhysicalx4 x4 x4 x4x4 x4 x4 x4x2x2x8x8x8x8x4x16x16Note:The Intel 5500 Chipset has only one X4 in the IOU0.3.3.3 Degraded ModeDegraded mode is supported for x16, x8, x4 and x2 link widths. The IOH supportsdegraded mode operation at half the original width and quarter of the original width orat x1. This mode allows one half or one quarter of the link to be mapped out if one ormore lanes should fail during normal operation. This allows for continued systemoperation in the event of a lane failure. Without support for degraded mode, a failureon a critical lane such as lane 0 could bring the entire link down in a fatal manner. Thiscan be avoided with support for degraded mode operation. For example, if lane 0 failson a x8 link, then the lower half of the link will be disabled and the traffic will continueat half the performance on lanes 4-7. Similarly, a x4 link would degrade to a x2 link.This remapping will occur in the physical layer, and the link and transaction layers areunaware of the link width change. The degraded mode widths are automaticallyIntel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet 49
Page 2: INFORMATION IN THIS DOCUMENT IS PRO
Page 6 and 7: 5.2 PCI Express Link Characteristic
Page 8 and 9: 7.2.1 VGA I/O Addresses ...........
Page 10 and 11: 14.1.3 SMBus.......................
Page 12 and 13: 19.3.3.23SLTCON2: PCI Express Slot
Page 14 and 15: 19.5.9.4 MIERRSV: Miscellaneous Err
Page 16 and 17: 19.8.2 On-Die Throttling Registers
Page 18 and 19: 19.11.2.17INTPIN: Interrupt Pin Reg
Page 20 and 21: 19.13.1.24INV_COMP_EVT_ADDR: Invali
Page 22 and 23: 4-3 Slave to Master Conflict Handli
Page 24 and 25: 19-16 IOH Local Error Map #2 (Dev 2
Page 26 and 27: Revision HistoryRevisionNumberDescr
Page 28 and 29: 28 Intel ® 5520 Chipset and Intel
Page 30 and 31: Figure 1-1.Intel® 5520 Chipset Exa
Page 32 and 33: 1.1.1 Features By Segment based on
Page 34 and 35: Intel ME network accessSystem Defen
Page 36 and 37: Table 1-2. Terminology (Sheet 3 of
Page 40 and 41: Figure 2-1.Example: Intel Xeon 5500
Page 44 and 45: Figure 3-1.Intel QuickPath Intercon
Page 46 and 47: Source Broadcast mode of operation,
Page 50 and 51: attempted every time the PCI Expres
Page 52 and 53: As a performance optimization, the
Page 54 and 55: 3.4.5.1 PHOLD SupportThe IOH suppor
Page 56 and 57: Table 3-5. Internal SMBus Protocol
Page 58 and 59: Table 3-8.Status Field Encoding for
Page 60 and 61: 3.7.7.2 SMBus Configuration and Mem
Page 62 and 63: 3.7.7.4 Configuration and Memory Wr
Page 64 and 65: Figure 3-14.SMBus Memory (Byte Writ
Page 66 and 67: Table 3-10. JTAG Configuration Regi
Page 68 and 69: 4.2.1 Supported FrequenciesThe freq
Page 70 and 71: A CSR configuration write to the re
Page 72 and 73: It is up to the Protocol Layer to e
Page 74 and 75: The Slave IOH will issue requests f
Page 76 and 77: IOH will never set or use the upper
Page 78 and 79: the appropriate bits. The bits that
Page 80 and 81: Table 4-8.Non-Coherent Inbound Tran
Page 82 and 83: Table 4-10. Protocol Transactions S
Page 84 and 85: 4.5.8.2 Peer-to-Peer Across Intel Q
Page 86 and 87: 4.9.1 Tag AllocationTags are used i
Page 88 and 89: Table 4-13. Local-Local Conflict Ac
Page 90 and 91: 4.11.1.2 Inbound Response versus In
Page 92 and 93: If (, != ,) {Strap to ltssm = strap
Page 94 and 95: 5.2.6 PCI Express Gen1/Gen2 Speed S
Page 96 and 97: 5.3.8 Configuration Retry Completio
Page 98 and 99:
Table 5-5.Incoming PCI Express Mess
Page 100 and 101:
Table 5-7.Outgoing PCI Express Mess
Page 102 and 103:
5.7.2 AttributesPCI Express support
Page 104 and 105:
5.10.3 Data PoisoningThe IOH suppor
Page 106 and 107:
5.11.4 Flow ControlThe PCI Express
Page 108 and 109:
5.13.2.1 Outbound Memory, I/O and C
Page 110 and 111:
5.13.2.4.3 Intel ® QuickPath Inter
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5.13.5 Completer IDThe CompleterID
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6.2 Inbound Ordering RulesInbound t
Page 116 and 117:
Note:On the Intel QuickPath Interco
Page 118 and 119:
For PCI configuration space, the or
Page 120 and 121:
Figure 7-1.System Address MapTOCM2^
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7.1.2.1 VGA/SMM Memory SpaceAddress
Page 124 and 125:
egisters (LMMIOL and GMMIOL) to sup
Page 126 and 127:
7.1.4.9 FirmwareThe CPUs may also u
Page 128 and 129:
downstream port in the IOH contains
Page 130 and 131:
7.5 IOH Address DecodingIn general,
Page 132 and 133:
7.5.1.5 Summary of Outbound Target
Page 134 and 135:
Figure 7-3.Peer-to-Peer Illustratio
Page 136 and 137:
Table 7-5.Inbound I/O Address Decod
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138 Intel ® 5520 Chipset and Intel
Page 140 and 141:
to the integrated I/OxAPIC in the l
Page 142 and 143:
Table 8-1.Interrupt Sources in I/Ox
Page 144 and 145:
The EOI message is broadcast to all
Page 146 and 147:
Table 8-6.MSI Address Format when R
Page 148 and 149:
Table 8-9.IA-32 Physical APICID to
Page 150 and 151:
IOH adds a value of 1 to the origin
Page 152 and 153:
Table 8-10. IA-32 Interrupt Deliver
Page 154 and 155:
The same rules that govern the coll
Page 156 and 157:
8.5.2.2 Global Intel SMI8.5.3 CPEIN
Page 158 and 159:
Table 9-1.Status Register Location
Page 160 and 161:
Figure 10-1. Throttled Load LineThr
Page 162 and 163:
Note:By limiting transaction proces
Page 164 and 165:
Page 166 and 167:
Figure 11-2. Example of typical Pla
Page 168 and 169:
Any of the standard PCI Express por
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Figure 11-3. ICH Timing Diagram for
Page 172 and 173:
11.6.2.3 L1 on Intel QuickPath Inte
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Figure 12-1. Example of Intel ME Co
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under special circumstances defined
Page 178 and 179:
(synchronized CORERST_N assertion o
Page 180 and 181:
13.2 Platform RESET Signal Routing
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Figure 13-6. Hard ResetCORERST_Nich
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Page 186 and 187:
14.1.6 CLINK BusThe CLINK reference
Page 188 and 189:
14.1.9.5 PLL Lock TimeThe assertion
Page 190 and 191:
4. PCI Express RASa. Standard PCI E
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Figure 15-2. Error Signal Converted
Page 194 and 195:
Requires immediate logging and repo
Page 196 and 197:
15.4.2.1.4 Time-OutTime-out error i
Page 198 and 199:
15.4.3 IOH Error Registers Overview
Page 200 and 201:
Figure 15-4. Local Error Signaling
Page 202 and 203:
Figure 15-5. Global Error Logging a
Page 204 and 205:
The hardware rules for updating the
Page 206 and 207:
according to the PCI Express Base S
Page 208 and 209:
15.4.4.2.1 Feature RequirementsA re
Page 210 and 211:
15.6.2 Link Retraining and Recovery
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Figure 15-10.PCI Express Error Stan
Page 214 and 215:
Table 15-3.IOH Error Summary (Sheet
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
15.8 IOH PCIe Hot Add/Remove Suppor
Page 226 and 227:
Table 15-4. Hot-Plug Interface (She
Page 228 and 229:
Figure 15-12.PCI Express Hot-Plug I
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one port of the external device has
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Some signals or groups of signals h
Page 238 and 239:
Table 17-6. PCI Express Signals (Sh
Page 240 and 241:
Table 17-9. MISC Signals (Sheet 2 o
Page 242 and 243:
Table 17-11. RMII Signals (Sheet 2
Page 244 and 245:
17.4 Suggested Strap Settings for D
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17.5 PCI Express Width StrappingTab
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Pin Name Location ConnectionTESTLO1
Page 250 and 251:
Table 18-1. Clock DC Characteristic
Page 252 and 253:
Table 18-4.CMOS, JTAG, SMBUS, GPIO3
Page 254 and 255:
Page 256 and 257:
19.2 Nonexistent Devices/Functions
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19.3 Standard PCI Configuration Spa
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Device: 16, 17Function: 0, 1Device:
Page 262 and 263:
Device:19Function: 0Device: 16, 17F
Page 264 and 265:
Device:19, 21Function: 0Device: 16,
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19.3.2.10 SID: Subsystem Device IDS
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19.3.3.2 NXTPTR: PCI Express Next C
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Device: 20Function: 0-2Offset:48hBi
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Device: 20Function: 0-2Offset:4AhBi
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Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Device: 20Function: 0-2Offset:5AhBi
Page 284 and 285:
Device: 20Function: 0-2Offset:5ChBi
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19.4 IOxAPIC ControllerTable 19-4.I
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Device: 19Function: 0Offset:04hBit
Page 292 and 293:
Register: PCISTSDevice: 19Function:
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Register:PMCAPDevice:19Function:0Of
Page 296 and 297:
19.4.8 RDWINDOW: Alternate Window t
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19.4.11 ABAR: I/OxAPIC Alternate BA
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Register:PMCSRDevice:19Function:0Of
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Register:IOAPICTETPCDevice:19Functi
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19.4.20 PAR RegisterRegister: PARBA
Page 306 and 307:
19.4.25 BCFGRegister: BCFGBAR: MBAR
Page 308 and 309:
19.5 Intel ® VT, Address Mapping,
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19.5.1 GENPROTRANGE0.BASE: Generic
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19.5.4 IOHMISCSS: IOH MISC StatusRe
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19.5.6 DUALIOAPIC.ABAR.LIMIT: Dual
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19.5.7.4 GENPROTRANGE2.BASE: Generi
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Register:NCMEM.LIMITDevice:20Functi
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Register: DEVHIDE1Device:20Function
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Page 324 and 325:
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.Register: LIO.BASEDevice:20Functio
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19.5.7.18 LMMIOH.LIMIT: Local MMIOH
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19.5.7.23 GIO.BASE: Global I/O Base
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19.5.7.28 GMMIOH.LIMIT: Global MMIO
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19.5.7.32 GCFGBUS.LIMIT: Global Con
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19.5.7.36 DUAL.NL.MMIOL.LIMIT: Dual
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19.5.7.40 DUAL.NL.IO.LIMIT: Dual No
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19.5.7.43 DUAL.VGA.CTRL: DP Dual IO
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Register: VTGENCTRLDevice:20Functio
Page 344 and 345:
Register: VTUNCERRMSKDevice:20Funct
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RESERVED PCIe Header space 100h IR[
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19.5.8.6 CWR[0:3]: Conditional Writ
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19.5.8.12 IR[0:3]: Increment Regist
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19.5.9 IOH System/Control Status Re
Page 354 and 355:
Table 19-12. IOH Local Error Map #1
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Register:QPIERRSVDevice:20Function:
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Register:IOHERRSVDevice:20Function:
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Register: THRERRSVDevice:20Function
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Register:VIRALDevice:20Function:2Of
Page 364 and 365:
19.5.9.12 VPPCTL: VPP ControlThis r
Page 366 and 367:
19.5.9.17 SYRE: System ResetThis re
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19.6 Global Error RegistersTable 19
Page 370 and 371:
Register: GNERRSTDevice:20Function:
Page 372 and 373:
Register:GERRCTLDevice:20Function:2
Page 374 and 375:
Register:GSYSSTDevice:20Function:2O
Page 376 and 377:
19.6.1.10 GFNERRST: Global Fatal NE
Page 378 and 379:
19.7 IOH Local Error RegistersTable
Page 380 and 381:
Table 19-17. IOH Local Error Map #2
Page 382 and 383:
Register:QPI[1:0]ERRCTLDevice:20Fun
Page 384 and 385:
Register:QPI[1:0]FNERRSTDevice:20Fu
Page 386 and 387:
Register:QPI[1:0]ERRCNTDevice:20Fun
Page 388 and 389:
Register:QPIP[1:0]ERRCTLDevice:20Fu
Page 390 and 391:
19.7.1.16 QPIP[1:0]NFERRST: Intel Q
Page 392 and 393:
Register:QPIP[1:0]ERRCNTSELDevice:2
Page 394 and 395:
19.7.2.4 IOHFNERRST: IOH Core Fatal
Page 396 and 397:
19.7.2.8 IOHERRCNTSEL: IOH Error Co
Page 398 and 399:
Register:THRFFERRSTDevice:20Functio
Page 400 and 401:
19.7.3.7 THRERRCNT: Thermal Error C
Page 402 and 403:
19.7.4.4 MIFNERRST: Miscellaneous F
Page 404 and 405:
19.7.4.9 MIERRCNT: Miscellaneous Er
Page 406 and 407:
19.8 On-Die Throttling Register Map
Page 408 and 409:
19.8.1.4 CGCTRL4L: Clock Gating Con
Page 410 and 411:
19.8.1.10 CGSTAGGER: Clock Gating S
Page 412 and 413:
19.8.2.4 TSTHRLO: On-Die Thermal Se
Page 414 and 415:
19.8.2.10 CTCTRL: On-Die Throttling
Page 416 and 417:
19.10.1 Intel QuickPath Interconnec
Page 418 and 419:
Register:QPI[1:0]LCLDevice:17, 16Fu
Page 420 and 421:
Register:QPI[1:0]LSDevice:17, 16Fun
Page 422 and 423:
Register:QPI[1:0]LP2Device:17, 16Fu
Page 424 and 425:
Register:QPI[1:0]LCL_LATEDevice:17,
Page 426 and 427:
Register:QPI[1:0]LCRDC_LATEDevice:1
Page 428 and 429:
Table 19-21. CSR Intel QPI Routing
Page 430 and 431:
Register:QPIPCTRLDevice:16Function:
Page 432 and 433:
Register:QPIPCTRLDevice:16Function:
Page 434 and 435:
Register:QPIPSTSDevice:16Function:1
Page 436 and 437:
Register:QPIPPOWCTRLDevice:16Functi
Page 438 and 439:
Register:QPIPMADDATADevice:16Functi
Page 440 and 441:
Register:QPIPDCASADDevice:16Functio
Page 442 and 443:
19.10.2.16 QPI[1:0]PORB: QPI[1:0] P
Page 444 and 445:
Register:QPIPLKMCDevice:16Function:
Page 446 and 447:
Register:QPIPQBIOHDevice:16Function
Page 448 and 449:
19.10.2.26 QPIPINITC: Intel® Quick
Page 450 and 451:
Register:QPIPINTRCDevice:17Function
Page 452 and 453:
19.10.3.1 QPI[1:0]PH_CPR: Intel Qui
Page 454 and 455:
19.10.3.3 QPI[1:0]PH_PIS: Intel Qui
Page 456 and 457:
19.10.3.5 QPI[1:0]PH_PRT: Intel Qui
Page 458 and 459:
Figure 19-1. PCI Express Root Port
Page 460 and 461:
Table 19-25. IOH Device 0 (ESI mode
Page 462 and 463:
Table 19-27. IOH Devices 0(PCIe Mod
Page 464 and 465:
Table 19-29. IOH Devices 0-10 Exten
Page 466 and 467:
Register: PCICMDDevice:0-10Function
Page 468 and 469:
Register: PCISTSDevice:0-10Function
Page 470 and 471:
19.11.2.9 PLAT: Primary Latency Tim
Page 472 and 473:
19.11.2.16 INTL: Interrupt Line Reg
Page 474 and 475:
The bottom of the defined I/O addre
Page 476 and 477:
Setting the memory limit less than
Page 478 and 479:
19.11.3.13 BCR: Bridge Control Regi
Page 480 and 481:
19.11.4.3 SVID: Subsystem Vendor ID
Page 482 and 483:
Register: MSIARDevice:1-10Function:
Page 484 and 485:
Register: PXPCAPDevice:0-10Function
Page 486 and 487:
Register: DEVCTRLDevice:0-10Functio
Page 488 and 489:
Register: LNKCAPDevice:0-10Function
Page 490 and 491:
Register: LNKSTSDevice:0-10Function
Page 492 and 493:
Register: SLTCAPDevice:0-10Function
Page 494 and 495:
Register: SLTCONDevice:1-10Function
Page 496 and 497:
Register: SLTSTSDevice:1-10Function
Page 498 and 499:
19.11.4.23 ROOTCAP: PCI Express Roo
Page 500 and 501:
Register: LNKCON2Device:1-10Functio
Page 502 and 503:
Register: PMCSRDevice:1-10Function:
Page 504 and 505:
19.11.5.3 UNCERRMSK: Uncorrectable
Page 506 and 507:
Register: CORERRMSKDevice:0-10Funct
Page 508 and 509:
Register: RPERRSTSDevice:0-10Functi
Page 510 and 511:
19.11.5.14 APICLIMIT: APIC Limit Re
Page 512 and 513:
19.11.5.18 PERFCTRLSTS: Performance
Page 514 and 515:
Register: MISCCTRLSTSDevice: 0Funct
Page 516 and 517:
Register: MISCCTRLSTSDevice: 1-10Fu
Page 518 and 519:
Register:PCIE_IOU0_BIF_CTRLDevice:3
Page 520 and 521:
Register:PCIE_IOU2_BIF_CTRLDevice:1
Page 522 and 523:
Register: XPUNCERRMSKDevice:0-10Fun
Page 524 and 525:
19.12.5.4 RPEDMASK - Root Port Erro
Page 526 and 527:
19.12.8 CTOCTRL: Completion Time-Ou
Page 528 and 529:
19.12.11 XP[10:0]ERRCNT: Error Coun
Page 530 and 531:
IOTLBINV 200h 280h204h284hINVADDRRE
Page 532 and 533:
Register: EXT_VTD_CAPAddr: MMIOBAR:
Page 534 and 535:
Register: GLBSTSAddr: MMIOBAR: VTBA
Page 536 and 537:
Register: FLTSTSAddr: MMIOBAR: VTBA
Page 538 and 539:
19.13.1.11 FLTEVTADDR: Fault Event
Page 540 and 541:
19.13.1.18 INV_QUEUE_HEAD: Invalida
Page 542 and 543:
19.13.1.24 INV_COMP_EVT_ADDR: Inval
Page 544 and 545:
Register:IOTLBINVAddr: MMIOBAR: VTB
Page 546 and 547:
Page 548 and 549:
20.2 Intel® 5520 Chipset Pin List
Page 550 and 551:
Figure 20-4. IOH Ballout Right Side
Page 552 and 553:
Table 20-2. IOH Signals (By Ball Nu
Page 554 and 555:
Table 20-4. IOH Signals (by Ball Nu
Page 556 and 557:
Page 558 and 559:
Page 560 and 561:
Table 20-10. IOH Signals (by Ball N
Page 562 and 563:
Page 564 and 565:
Page 566 and 567:
Page 568 and 569:
Page 570 and 571:
Table 20-20. IOH Signals (by Signal
Page 572 and 573:
Page 574 and 575:
Page 576 and 577:
Page 578 and 579:
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Page 582 and 583:
Page 584 and 585:
Page 586 and 587:
Page 588 and 589:
20.4 Intel® 5500 Chipset IOH Ballo
Page 590 and 591:
Figure 20-7. IOH 24D Ballout Left S
Page 592 and 593:
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Page 598 and 599:
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