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Table 1-2. Terminology (Sheet 3 of 3)TermDescriptionMSIOplinORBOutboundTransactionsPAPCI Express Gen1PCI Express Gen2PCMPLCPMEPortProcessorPXHRASRemote Peer-to-PeerRIDRTARTCSATASCMDSECSMBusSocketSPDS/PDIFSPISPSSSPSTDTCOUHCIURUSBIntel VT-dMessage Signaled InterruptDual 10 Gb Ethernet ControllerOutgoing Request BufferTransactions initiated on an Intel ® QuickPath Interconnect port destined for a PCIExpress or ESI portPhysical AddressCommon reference for 1st generation PCI Express (Base Spec revision 1.x) and up to2.5 GT/s speedCommon reference for 2nd generation PCI Express (Base Spec revision 2.x) and up to5.0 GT/s speedPulse Code ModulationPlatform LAN ConnectPower Management EventIn physical terms, a group of transmitters and receivers physically located on the IOHthat define one side of a linkCommon reference term for processor socket, used throughout this documentIntels PCI Express to dual PCI-X* bridge componentReliability, Availability, ServiceabilityA transaction initiated by an I/O agent destined for an I/O target on a different rootcomplexRevision ID of the IOHRouter Table ArrayReal Time ClockSerial ATASub CommandSingle Error CorrectionSystem Management Bus. A two-wire interface through which various systemcomponents can communicate.Processor (cores + uncore)Serial Presence DetectSony/Phillips Digital InterfaceSerial Peripheral Interface. The interface for serial flash components.Server Platform ServicesSystem Service ProcessorSuspend To DiskTotal Cost of OwnershipUniversal Host Controller InterfaceUnsupported RequestUniversal Serial BusIntel ® Virtualization Technology (Intel ® VT) for Directed I/O (Intel ® VT-d)1.3 Related DocumentsThe reader of this document should also be familiar with the components, material andconcepts presented in the documents listed in Table 1-3.36 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet