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19.13.1.24INV_COMP_EVT_ADDR: Invalidation CompletionEvent Address Register ............................................................ 54219.13.1.25INTR_REMAP_TABLE_BASE: Interrupt RemappingTable Base Address Register ..................................................... 54219.13.1.26FLTREC: Fault Record Register ................................................ 54219.13.1.27IOTLBINV: IOTLB Invalidate Register .......................................54319.13.1.28INVADDRREG: Invalidate Address Register ............................... 54420 Package and Ballout Information ........................................................................... 54720.1 Intel 5520 Chipset IOH Ballout .......................................................................... 54720.2 Intel® 5520 Chipset Pin List and Ballout ............................................................. 54820.3 Intel® 5500 Chipset IOH Ballout........................................................................ 58720.4 Intel® 5500 Chipset IOH Ballout and Pin List.......................................................58820.5 Package Information ........................................................................................ 627Figures1-1 Intel® 5520 Chipset Example System Block Diagram .............................................301-2 Intel® 5520 Chipset and Intel® 5500 Chipset IOH High-Level Block Diagram ............312-1 Example: Intel Xeon 5500 Platform Topology with Intel 5520 Chipset(for reference only)............................................................................................402-2 Example: Intel Xeon 5500 Platform Topology with Intel 5500 Chipset(for reference only)............................................................................................402-3 Example: Intel Xeon 5500 Dual IOH Topology (for reference only) ...........................413-1 Intel QuickPath Interconnect Packet Visibility By The Physical Layer (Phit) .................443-2 Intel 5520 Chipset PCI Express Interface Partitioning..............................................493-3 SMBus Block-Size Configuration Register Read.......................................................593-4 SMBus Block-Size Memory Register Read ..............................................................593-5 SMBus Word-Size Configuration Register Read.......................................................603-6 SMBus Word-Size Memory Register Read ..............................................................603-7 SMBus Byte-Size Configuration Register Read........................................................613-8 SMBus Byte-Size Memory Register Read ...............................................................613-9 SMBus Block-Size Configuration Register Write ......................................................623-10 SMBus Block-Size Memory Register Write..............................................................623-11 SMBus Word-Size Configuration Register Write ......................................................633-12 SMBus Word-Size Memory Register Write..............................................................633-13 SMBus Configuration (Byte Write, PEC Enabled).....................................................633-14 SMBus Memory (Byte Write, PEC Enabled) ............................................................644-1 Intel QuickPath Interconnect Packet Visibility By The Physical Layer (Phit).................674-2 Intel QuickPath Interconnect Packet Visibility By Link Layer (Flit) .............................687-1 System Address Map ........................................................................................1207-2 VGA/SMM and Legacy C/D/E/F Regions............................................................... 1217-3 Peer-to-Peer Illustration ...................................................................................1348-1 Legacy Interrupt Routing Illustration (INTA Example) ........................................... 1418-2 Interrupt Transformation Table Entry (IRTE)........................................................ 1478-3 Assert/Deassert_(HP, PME) GPE Messages .......................................................... 1548-4 Intel QuickPath Interconnect GPE Messages from Processor andDO_SCI Messages from IOH.............................................................................. 15510-1 Throttled Load Line ..........................................................................................16010-2 Load Line Distribution....................................................................................... 16110-3 Example of Die Temperature versus Time Under Throttled Conditions ..................... 16210-4 Thermal Management Control............................................................................ 16311-1 ACPI Power States in G0 and G1 States for the IOH and ICH .................................16511-2 Example of typical Platform Showing Power Saving Signals to BMC......................... 16611-3 ICH Timing Diagram for S3,S4,S5 Transition ....................................................... 17020 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet