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Figure 1-1.Intel® 5520 Chipset Example System Block DiagramCH0CH0SystemMemory(DDR3)CH1ProcessorProcessorCH1SystemMemory(DDR3)CH2CH2Intel® QuickPathInterconnect (Intel® QPI)Intel® QuickPathInterconnect (Intel® QPI)PCIeGen2 X16PCIeGen2 X16Intel® IOHJTAGPCIeGen2 X4ESIInterfaceControlLink6 Serial ATA PortPower ManagmentGPIOUSB 2.012 portSPI Flash BIOSSST and PECI SensorInputsIntel® ICHSMBUS 2.0/I 2 CIntel® High Definition AudioCode®Intel® 82567 GigabitPlatform LANConnectFan Speed Control OutputLPCPCIeGen1TPMSIOPCI BusFour PCIMastersNote:The Intel ® 5500 Chipset IOH has only one X16 PCIe* link and 2 X4 PCIe links.30 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet
1.1 Feature SummaryThe IOH provides the interface between the processor Intel QuickPath Interconnect andindustry-standard PCI Express* components. The two Intel QuickPath Interconnectinterfaces are full-width links (20 lanes in each direction). The two x16 PCI ExpressGen2 ports are also configurable as x8 and x4 links compliant to the PCI Express BaseSpecification, Revision 2.0. The single x4 PCI Express Gen2 port can bifurcate into twoindependent x2 interfaces.In addition, the legacy IOH supports a x4 ESI link interfacefor the legacy bridge. Refer to Figure 1-2 for a high-level view of the IOH and itsinterfaces.The IOH supports the following features and technologies:Intel ® QuickPath Interconnect profileInterface to CPU or other IOH (limited configurations) PCI Express Gen2Intel ® I/O Accelerated Technology (Intel ® I/OAT) and Intel ® Quick DataTechnology (updated DMA engine with virtualization enhancements)Integrated Intel ® Management Engine (Intel ® ME)Figure 1-2.Intel® 5520 Chipset and Intel® 5500 Chipset IOH High-Level Block DiagramNote:The internal IOH interfaces are designed to communicate with each other. Thiscommunication is illustrated in the diagram above as a shared bus; however, this is aconceptual diagram and does not represent actual implementation and connectivity.Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet 31
Page 2: INFORMATION IN THIS DOCUMENT IS PRO
Page 6 and 7: 5.2 PCI Express Link Characteristic
Page 8 and 9: 7.2.1 VGA I/O Addresses ...........
Page 10 and 11: 14.1.3 SMBus.......................
Page 12 and 13: 19.3.3.23SLTCON2: PCI Express Slot
Page 14 and 15: 19.5.9.4 MIERRSV: Miscellaneous Err
Page 16 and 17: 19.8.2 On-Die Throttling Registers
Page 18 and 19: 19.11.2.17INTPIN: Interrupt Pin Reg
Page 20 and 21: 19.13.1.24INV_COMP_EVT_ADDR: Invali
Page 22 and 23: 4-3 Slave to Master Conflict Handli
Page 24 and 25: 19-16 IOH Local Error Map #2 (Dev 2
Page 26 and 27: Revision HistoryRevisionNumberDescr
Page 28 and 29: 28 Intel ® 5520 Chipset and Intel
Page 32 and 33: 1.1.1 Features By Segment based on
Page 34 and 35: Intel ME network accessSystem Defen
Page 36 and 37: Table 1-2. Terminology (Sheet 3 of
Page 40 and 41: Figure 2-1.Example: Intel Xeon 5500
Page 44 and 45: Figure 3-1.Intel QuickPath Intercon
Page 46 and 47: Source Broadcast mode of operation,
Page 48 and 49: 3.3.1 Gen1/Gen2 SupportThe IOH supp
Page 50 and 51: attempted every time the PCI Expres
Page 52 and 53: As a performance optimization, the
Page 54 and 55: 3.4.5.1 PHOLD SupportThe IOH suppor
Page 56 and 57: Table 3-5. Internal SMBus Protocol
Page 58 and 59: Table 3-8.Status Field Encoding for
Page 60 and 61: 3.7.7.2 SMBus Configuration and Mem
Page 62 and 63: 3.7.7.4 Configuration and Memory Wr
Page 64 and 65: Figure 3-14.SMBus Memory (Byte Writ
Page 66 and 67: Table 3-10. JTAG Configuration Regi
Page 68 and 69: 4.2.1 Supported FrequenciesThe freq
Page 70 and 71: A CSR configuration write to the re
Page 72 and 73: It is up to the Protocol Layer to e
Page 74 and 75: The Slave IOH will issue requests f
Page 76 and 77: IOH will never set or use the upper
Page 78 and 79: the appropriate bits. The bits that
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Table 4-8.Non-Coherent Inbound Tran
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Table 4-10. Protocol Transactions S
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4.5.8.2 Peer-to-Peer Across Intel Q
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4.9.1 Tag AllocationTags are used i
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Table 4-13. Local-Local Conflict Ac
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4.11.1.2 Inbound Response versus In
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If (, != ,) {Strap to ltssm = strap
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5.2.6 PCI Express Gen1/Gen2 Speed S
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5.3.8 Configuration Retry Completio
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Table 5-5.Incoming PCI Express Mess
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Table 5-7.Outgoing PCI Express Mess
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5.7.2 AttributesPCI Express support
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5.10.3 Data PoisoningThe IOH suppor
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5.11.4 Flow ControlThe PCI Express
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5.13.2.1 Outbound Memory, I/O and C
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5.13.2.4.3 Intel ® QuickPath Inter
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5.13.5 Completer IDThe CompleterID
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6.2 Inbound Ordering RulesInbound t
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Note:On the Intel QuickPath Interco
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For PCI configuration space, the or
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Figure 7-1.System Address MapTOCM2^
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7.1.2.1 VGA/SMM Memory SpaceAddress
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egisters (LMMIOL and GMMIOL) to sup
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7.1.4.9 FirmwareThe CPUs may also u
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downstream port in the IOH contains
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7.5 IOH Address DecodingIn general,
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7.5.1.5 Summary of Outbound Target
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Figure 7-3.Peer-to-Peer Illustratio
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Table 7-5.Inbound I/O Address Decod
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138 Intel ® 5520 Chipset and Intel
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to the integrated I/OxAPIC in the l
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Table 8-1.Interrupt Sources in I/Ox
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The EOI message is broadcast to all
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Table 8-6.MSI Address Format when R
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Table 8-9.IA-32 Physical APICID to
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IOH adds a value of 1 to the origin
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Table 8-10. IA-32 Interrupt Deliver
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The same rules that govern the coll
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8.5.2.2 Global Intel SMI8.5.3 CPEIN
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Table 9-1.Status Register Location
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Figure 10-1. Throttled Load LineThr
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Note:By limiting transaction proces
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Figure 11-2. Example of typical Pla
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Any of the standard PCI Express por
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Figure 11-3. ICH Timing Diagram for
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11.6.2.3 L1 on Intel QuickPath Inte
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Figure 12-1. Example of Intel ME Co
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under special circumstances defined
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(synchronized CORERST_N assertion o
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13.2 Platform RESET Signal Routing
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Figure 13-6. Hard ResetCORERST_Nich
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14.1.6 CLINK BusThe CLINK reference
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14.1.9.5 PLL Lock TimeThe assertion
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4. PCI Express RASa. Standard PCI E
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Figure 15-2. Error Signal Converted
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Requires immediate logging and repo
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15.4.2.1.4 Time-OutTime-out error i
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15.4.3 IOH Error Registers Overview
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Figure 15-4. Local Error Signaling
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Figure 15-5. Global Error Logging a
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The hardware rules for updating the
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according to the PCI Express Base S
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15.4.4.2.1 Feature RequirementsA re
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15.6.2 Link Retraining and Recovery
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Figure 15-10.PCI Express Error Stan
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Table 15-3.IOH Error Summary (Sheet
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15.8 IOH PCIe Hot Add/Remove Suppor
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Table 15-4. Hot-Plug Interface (She
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Figure 15-12.PCI Express Hot-Plug I
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one port of the external device has
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Some signals or groups of signals h
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Table 17-6. PCI Express Signals (Sh
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Table 17-9. MISC Signals (Sheet 2 o
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Table 17-11. RMII Signals (Sheet 2
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17.4 Suggested Strap Settings for D
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17.5 PCI Express Width StrappingTab
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Pin Name Location ConnectionTESTLO1
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Table 18-1. Clock DC Characteristic
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Table 18-4.CMOS, JTAG, SMBUS, GPIO3
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19.2 Nonexistent Devices/Functions
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19.3 Standard PCI Configuration Spa
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Device: 16, 17Function: 0, 1Device:
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Device:19Function: 0Device: 16, 17F
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Device:19, 21Function: 0Device: 16,
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19.3.2.10 SID: Subsystem Device IDS
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19.3.3.2 NXTPTR: PCI Express Next C
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Device: 20Function: 0-2Offset:48hBi
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Device: 20Function: 0-2Offset:4AhBi
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Device: 20Function: 0-2Offset:5AhBi
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Device: 20Function: 0-2Offset:5ChBi
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19.4 IOxAPIC ControllerTable 19-4.I
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Device: 19Function: 0Offset:04hBit
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Register: PCISTSDevice: 19Function:
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Register:PMCAPDevice:19Function:0Of
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19.4.8 RDWINDOW: Alternate Window t
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19.4.11 ABAR: I/OxAPIC Alternate BA
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Register:PMCSRDevice:19Function:0Of
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Register:IOAPICTETPCDevice:19Functi
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19.4.20 PAR RegisterRegister: PARBA
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19.4.25 BCFGRegister: BCFGBAR: MBAR
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19.5 Intel ® VT, Address Mapping,
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19.5.1 GENPROTRANGE0.BASE: Generic
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19.5.4 IOHMISCSS: IOH MISC StatusRe
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19.5.6 DUALIOAPIC.ABAR.LIMIT: Dual
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19.5.7.4 GENPROTRANGE2.BASE: Generi
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Register:NCMEM.LIMITDevice:20Functi
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Register: DEVHIDE1Device:20Function
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.Register: LIO.BASEDevice:20Functio
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19.5.7.18 LMMIOH.LIMIT: Local MMIOH
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19.5.7.23 GIO.BASE: Global I/O Base
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19.5.7.28 GMMIOH.LIMIT: Global MMIO
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19.5.7.32 GCFGBUS.LIMIT: Global Con
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19.5.7.36 DUAL.NL.MMIOL.LIMIT: Dual
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19.5.7.40 DUAL.NL.IO.LIMIT: Dual No
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19.5.7.43 DUAL.VGA.CTRL: DP Dual IO
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Register: VTGENCTRLDevice:20Functio
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Register: VTUNCERRMSKDevice:20Funct
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RESERVED PCIe Header space 100h IR[
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19.5.8.6 CWR[0:3]: Conditional Writ
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19.5.8.12 IR[0:3]: Increment Regist
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19.5.9 IOH System/Control Status Re
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Table 19-12. IOH Local Error Map #1
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Register:QPIERRSVDevice:20Function:
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Register:IOHERRSVDevice:20Function:
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Register: THRERRSVDevice:20Function
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Register:VIRALDevice:20Function:2Of
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19.5.9.12 VPPCTL: VPP ControlThis r
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19.5.9.17 SYRE: System ResetThis re
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19.6 Global Error RegistersTable 19
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Register: GNERRSTDevice:20Function:
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Register:GERRCTLDevice:20Function:2
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Register:GSYSSTDevice:20Function:2O
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19.6.1.10 GFNERRST: Global Fatal NE
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19.7 IOH Local Error RegistersTable
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Table 19-17. IOH Local Error Map #2
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Register:QPI[1:0]ERRCTLDevice:20Fun
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Register:QPI[1:0]FNERRSTDevice:20Fu
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Register:QPI[1:0]ERRCNTDevice:20Fun
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Register:QPIP[1:0]ERRCTLDevice:20Fu
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19.7.1.16 QPIP[1:0]NFERRST: Intel Q
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Register:QPIP[1:0]ERRCNTSELDevice:2
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19.7.2.4 IOHFNERRST: IOH Core Fatal
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19.7.2.8 IOHERRCNTSEL: IOH Error Co
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Register:THRFFERRSTDevice:20Functio
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19.7.3.7 THRERRCNT: Thermal Error C
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19.7.4.4 MIFNERRST: Miscellaneous F
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19.7.4.9 MIERRCNT: Miscellaneous Er
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19.8 On-Die Throttling Register Map
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19.8.1.4 CGCTRL4L: Clock Gating Con
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19.8.1.10 CGSTAGGER: Clock Gating S
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19.8.2.4 TSTHRLO: On-Die Thermal Se
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19.8.2.10 CTCTRL: On-Die Throttling
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19.10.1 Intel QuickPath Interconnec
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Register:QPI[1:0]LCLDevice:17, 16Fu
Page 420 and 421:
Register:QPI[1:0]LSDevice:17, 16Fun
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Register:QPI[1:0]LP2Device:17, 16Fu
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Register:QPI[1:0]LCL_LATEDevice:17,
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Register:QPI[1:0]LCRDC_LATEDevice:1
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Table 19-21. CSR Intel QPI Routing
Page 430 and 431:
Register:QPIPCTRLDevice:16Function:
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Register:QPIPCTRLDevice:16Function:
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Register:QPIPSTSDevice:16Function:1
Page 436 and 437:
Register:QPIPPOWCTRLDevice:16Functi
Page 438 and 439:
Register:QPIPMADDATADevice:16Functi
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Register:QPIPDCASADDevice:16Functio
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19.10.2.16 QPI[1:0]PORB: QPI[1:0] P
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Register:QPIPLKMCDevice:16Function:
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Register:QPIPQBIOHDevice:16Function
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19.10.2.26 QPIPINITC: Intel® Quick
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Register:QPIPINTRCDevice:17Function
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19.10.3.1 QPI[1:0]PH_CPR: Intel Qui
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19.10.3.3 QPI[1:0]PH_PIS: Intel Qui
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19.10.3.5 QPI[1:0]PH_PRT: Intel Qui
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Figure 19-1. PCI Express Root Port
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Table 19-25. IOH Device 0 (ESI mode
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Table 19-27. IOH Devices 0(PCIe Mod
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Table 19-29. IOH Devices 0-10 Exten
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Register: PCICMDDevice:0-10Function
Page 468 and 469:
Register: PCISTSDevice:0-10Function
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19.11.2.9 PLAT: Primary Latency Tim
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19.11.2.16 INTL: Interrupt Line Reg
Page 474 and 475:
The bottom of the defined I/O addre
Page 476 and 477:
Setting the memory limit less than
Page 478 and 479:
19.11.3.13 BCR: Bridge Control Regi
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19.11.4.3 SVID: Subsystem Vendor ID
Page 482 and 483:
Register: MSIARDevice:1-10Function:
Page 484 and 485:
Register: PXPCAPDevice:0-10Function
Page 486 and 487:
Register: DEVCTRLDevice:0-10Functio
Page 488 and 489:
Register: LNKCAPDevice:0-10Function
Page 490 and 491:
Register: LNKSTSDevice:0-10Function
Page 492 and 493:
Register: SLTCAPDevice:0-10Function
Page 494 and 495:
Register: SLTCONDevice:1-10Function
Page 496 and 497:
Register: SLTSTSDevice:1-10Function
Page 498 and 499:
19.11.4.23 ROOTCAP: PCI Express Roo
Page 500 and 501:
Register: LNKCON2Device:1-10Functio
Page 502 and 503:
Register: PMCSRDevice:1-10Function:
Page 504 and 505:
19.11.5.3 UNCERRMSK: Uncorrectable
Page 506 and 507:
Register: CORERRMSKDevice:0-10Funct
Page 508 and 509:
Register: RPERRSTSDevice:0-10Functi
Page 510 and 511:
19.11.5.14 APICLIMIT: APIC Limit Re
Page 512 and 513:
19.11.5.18 PERFCTRLSTS: Performance
Page 514 and 515:
Register: MISCCTRLSTSDevice: 0Funct
Page 516 and 517:
Register: MISCCTRLSTSDevice: 1-10Fu
Page 518 and 519:
Register:PCIE_IOU0_BIF_CTRLDevice:3
Page 520 and 521:
Register:PCIE_IOU2_BIF_CTRLDevice:1
Page 522 and 523:
Register: XPUNCERRMSKDevice:0-10Fun
Page 524 and 525:
19.12.5.4 RPEDMASK - Root Port Erro
Page 526 and 527:
19.12.8 CTOCTRL: Completion Time-Ou
Page 528 and 529:
19.12.11 XP[10:0]ERRCNT: Error Coun
Page 530 and 531:
IOTLBINV 200h 280h204h284hINVADDRRE
Page 532 and 533:
Register: EXT_VTD_CAPAddr: MMIOBAR:
Page 534 and 535:
Register: GLBSTSAddr: MMIOBAR: VTBA
Page 536 and 537:
Register: FLTSTSAddr: MMIOBAR: VTBA
Page 538 and 539:
19.13.1.11 FLTEVTADDR: Fault Event
Page 540 and 541:
19.13.1.18 INV_QUEUE_HEAD: Invalida
Page 542 and 543:
19.13.1.24 INV_COMP_EVT_ADDR: Inval
Page 544 and 545:
Register:IOTLBINVAddr: MMIOBAR: VTB
Page 546 and 547:
Page 548 and 549:
20.2 Intel® 5520 Chipset Pin List
Page 550 and 551:
Figure 20-4. IOH Ballout Right Side
Page 552 and 553:
Table 20-2. IOH Signals (By Ball Nu
Page 554 and 555:
Table 20-4. IOH Signals (by Ball Nu
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Page 558 and 559:
Page 560 and 561:
Table 20-10. IOH Signals (by Ball N
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Table 20-20. IOH Signals (by Signal
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20.4 Intel® 5500 Chipset IOH Ballo
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Figure 20-7. IOH 24D Ballout Left S
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