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attempted every time the PCI Express link is trained. The events that triggerPCI Express link training are documented in the PCI Express Base Specification,Revision 2.0.IOH-supported degraded modes are shown below. Table 3-3 should be read such thatthe various modes indicated in the different rows would be tried by IOH, but notnecessarily in the order shown in the table. IOH would try a higher width degradedmode before trying any lower width degraded modes. IOH reports entry into or exitfrom degraded mode to software (see Chapter 19 and also records which lane failed.Software can then report the unexpected or erroneous hardware behavior to thesystem operator for attention, by generating a system interrupt per Chapter 15, IOHError Handling Summary.Table 3-3.Supported Degraded ModesOriginal Link Width 1Degraded Mode Link width and Lanes Numbersx16 x8 on either lanes 7-0,0-7,15-8,8-15x4 on either lanes 3-0,0-3,4-7,7-4,8-11,11-8,12-15,15-12x2 on either lanes 1-0,0-1,4-5,5-4,8-9,9-8,12-13,13-12x1 on either lanes 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15x8 x4 on lanes 7-4,4-7,3-0,0-3x2 on lanes 5-4,4-5, 1-0, 0-1x1 on lanes 0,1,2,3,4,5,6,7x4 x2 on lanes 1-0,0-1x1 on lanes 0,1,2,3x2 x1 on lanes 0,1Note:1. This is the native width the link is running at when degraded mode operation kicks-in.3.3.4 Lane ReversalThe IOH supports lane reversal on all PCI Express ports, regardless of the link width(x16, x8, x4, and x2). The IOH allows a x4 or x8 card to be plugged into a x8 slot thatis lane-reversed on the motherboard, and operate at the maximum link width of thecard; similarly for a x4 card plugged into a lane-reversed x4 slot, and a x2 cardplugged into a lane-reversed x2 slot. Note that for the purpose of this discussion, a xNslot refers to a CEM/SIOM slot that is capable of any width higher than or equal to xNbut is electrically wired on the board for only a xN width. A x2 card can be plugged intoa x8, or x4 slot and work as x2 only if lane-reversal is not done on the motherboard;otherwise, it would operate in x1 mode.3.3.5 IOH Performance PoliciesUnless otherwise noted, the performance policies noted in this section apply to astandard PCI Express port on the IOH.3.3.5.1 Max_Payload_SizeThe IOH supports a Max_Payload_Size of 256 Bytes on PCI Express ports and128 Bytes on ESI.50 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet