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Intel ME network accessSystem Defense Feature support enabled by firmware1.1.11 Reliability, Availability, Serviceability (RAS) FeaturesSupports an SMBus Specification, Revision 2.0 slave interface for servermanagement with Packet Error Checking: SMBus and JTAG access to IOH configuration registers for out-of-band servermanagementImproved RAS achieved by protecting internal datapaths through ECC and parityprotection mechanismsSupports PCI Express Base Specification, Revision 2.0 CRC with link-level retrySupports both standard Intel QuickPath Interconnect CRC with link level retryAdvanced Error Reporting capability for PCI Express link interfacesNative PCI Express Hot-Plug supportError injection capabilitiesPerformance monitoring capabilities1.1.12 Power Management Support1.1.13 Security PCI Express Link states (L0, L0s, L1, L2/L3) Intel QuickPath Interconnect Link states (L0, L0s, L1) ESI states (L0, L0s, L1) Intel ME states (M0, M1, Mdisable, Moff) System states (S0, S1, S3, S4, S5)TPM1.2 and Intel VT-d for server security1.1.14 OtherIntegrated IOxAPIC1.2 TerminologyTable 1-2 defines the acronyms, conventions, and terminology used throughout thespecification.Table 1-2. Terminology (Sheet 1 of 3)TermAPICASIC RepeaterBISTBMCDescriptionAdvanced Programmable Interrupt ControllerA chip which intercepts the Intel QuickPath Interconnect traffic. It repeats the traffic,but also sends appropriate data to the logic analyzer.Built-In Self TestBaseboard Management Controller. A microcontroller used for remote platformmanagement.34 Intel ® 5520 Chipset and Intel ® 5500 Chipset Datasheet